diff options
| author | Dave Airlie <airlied@redhat.com> | 2009-11-23 09:09:08 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2010-02-10 10:30:43 +1000 |
| commit | 2e22c360eaf22c1ebf4d5ac5f377400858816c42 (patch) | |
| tree | 7e283865938307260860229803cdc910b6ca3cec | |
| parent | d38a56dc0466eb314d55d3e54d3a97887f18b2a5 (diff) | |
radeontool: add more legacy crtc regs
| -rw-r--r-- | radeon_reg.h | 6 | ||||
| -rw-r--r-- | radeontool.c | 23 |
2 files changed, 29 insertions, 0 deletions
diff --git a/radeon_reg.h b/radeon_reg.h index 06e57ee..5fa1e6d 100644 --- a/radeon_reg.h +++ b/radeon_reg.h @@ -382,6 +382,11 @@ # define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26) # define RADEON_CRTC2_HSYNC_DIS (1 << 28) # define RADEON_CRTC2_VSYNC_DIS (1 << 29) +#define RADEON_CRTC_MORE_CNTL 0x27c +# define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2) +# define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3) +# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) +# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) #define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 #define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 # define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) @@ -854,6 +859,7 @@ # define RADEON_HORZ_AUTO_RATIO (1 << 27) # define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28) # define RADEON_HORZ_AUTO_RATIO_INC (1 << 31) +#define RADEON_FP_HORZ_VERT_ACTIVE 0x0278 #define RADEON_FP_V_SYNC_STRT_WID 0x02c8 #define RADEON_FP_VERT_STRETCH 0x0290 #define RADEON_FP_V2_SYNC_STRT_WID 0x03c8 diff --git a/radeontool.c b/radeontool.c index b8e250d..907927f 100644 --- a/radeontool.c +++ b/radeontool.c @@ -175,10 +175,33 @@ void radeon_cmd_regs(void) SHOW_REG(RADEON_LVDS_PLL_CNTL); SHOW_REG(RADEON_FP_GEN_CNTL); SHOW_REG(RADEON_FP2_GEN_CNTL); + SHOW_CLK_REG(RADEON_PPLL_CNTL); + SHOW_CLK_REG(RADEON_PPLL_REF_DIV); + SHOW_CLK_REG(RADEON_PPLL_DIV_3); SHOW_CLK_REG(RADEON_PIXCLKS_CNTL); + SHOW_CLK_REG(RADEON_P2PLL_CNTL); + SHOW_CLK_REG(RADEON_P2PLL_REF_DIV); + SHOW_CLK_REG(RADEON_P2PLL_DIV_0); + SHOW_CLK_REG(RADEON_VCLK_ECP_CNTL); SHOW_REG(RADEON_MEM_TIMING_CNTL); SHOW_REG(RADEON_TMDS_PLL_CNTL); SHOW_REG(RADEON_TMDS_TRANSMITTER_CNTL); + SHOW_REG(RADEON_CRTC_MORE_CNTL); + SHOW_REG(RADEON_FP_H_SYNC_STRT_WID); + SHOW_REG(RADEON_FP_V_SYNC_STRT_WID); + SHOW_REG(RADEON_FP_CRTC_H_TOTAL_DISP); + SHOW_REG(RADEON_FP_CRTC_V_TOTAL_DISP); + SHOW_REG(RADEON_FP_HORZ_STRETCH); + SHOW_REG(RADEON_FP_VERT_STRETCH); + SHOW_REG(RADEON_FP_HORZ_VERT_ACTIVE); + SHOW_REG(RADEON_CRTC_H_TOTAL_DISP); + SHOW_REG(RADEON_CRTC_H_SYNC_STRT_WID); + SHOW_REG(RADEON_CRTC_V_TOTAL_DISP); + SHOW_REG(RADEON_CRTC_V_SYNC_STRT_WID); + SHOW_REG(RADEON_CRTC2_H_TOTAL_DISP); + SHOW_REG(RADEON_CRTC2_H_SYNC_STRT_WID); + SHOW_REG(RADEON_CRTC2_V_TOTAL_DISP); + SHOW_REG(RADEON_CRTC2_V_SYNC_STRT_WID); } #define REGLIST(r) { "", #r, radeon_get, radeon_set, RADEON_ ## r } |