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authorAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>2019-11-26 08:48:33 -0500
committerTomeu Vizoso <tomeu.vizoso@collabora.co.uk>2019-12-03 04:25:04 +0000
commit8555bffafdbcda9db0424d6ac2091fd3eac19bc5 (patch)
treeea054ed45bcf4f0e42822181de587b86a64ffe93
parentab81a23d36fb4a87f3ac3ef81d333295d54002a1 (diff)
pan/midgard: Splatter on fragment out
Make sure that the fragment is complete when writing it out. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
-rw-r--r--src/panfrost/midgard/midgard_compile.c21
1 files changed, 20 insertions, 1 deletions
diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c
index 2d8145c2ec0..76f53fbabfc 100644
--- a/src/panfrost/midgard/midgard_compile.c
+++ b/src/panfrost/midgard/midgard_compile.c
@@ -1590,7 +1590,26 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
case nir_intrinsic_store_raw_output_pan:
assert (ctx->stage == MESA_SHADER_FRAGMENT);
reg = nir_src_index(ctx, &instr->src[0]);
- emit_fragment_store(ctx, reg, 0);
+
+ if (ctx->quirks & MIDGARD_OLD_BLEND) {
+ /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
+ * reg = r0.x. We want to splatter. So we can do a 32-bit move
+ * of:
+ *
+ * imov r0.xyzw, r0.xxxx
+ */
+
+ unsigned expanded = make_compiler_temp(ctx);
+
+ midgard_instruction splatter = v_mov(reg, expanded);
+
+ for (unsigned c = 0; c < 16; ++c)
+ splatter.swizzle[1][c] = 0;
+
+ emit_mir_instruction(ctx, splatter);
+ emit_fragment_store(ctx, expanded, 0);
+ } else
+ emit_fragment_store(ctx, reg, 0);
break;