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Signed-off-by: Thierry Reding <treding@nvidia.com>
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This test uses the IOCTLs for job submission and fences to fill a sub-
region of the screen to a specific color using gr2d.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v3:
- use convenience gr2d fill helper
- open /dev/dri/card0 by default
Changes in v2:
- free framebuffer when done
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This library provides helpers for common functionality needed by test
programs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v3:
- make drm_tegra_gr2d_fill() more generic
- add simple convenience wrapper
- fix libdrm-test.la link failure
Changes in v2:
- fix a couple of memory leaks and get rid of some unneeded code
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These functions can be used to open channels to engines, manage job
submissions, create push buffers to store command streams in and wait
until jobs have been completed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v3:
- make drm_tegra_fence_wait() a static inline to avoid overhead
- prepare push buffers in sync helper
- add missing sys/ioctl.h include
- remove unused variables
Changes in v2:
- automatically allocate buffer objects as required by pushbuffers
- pushbuffers can now have more than one associated buffer object
- add drm_tegra_pushbuf_prepare() function
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With the recent additon of the .editorconfig file there's an established
coding style that can be followed. Convert the relatively small amount
of Tegra code to the new coding style.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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drmHandleEvent() currently reads events in 1 KiB chunks. Within the
kernel each DRM device is allowed to carry up to 4 KiB of event data,
and the drm_read() implementation will only hand out complete events.
All of this combined could cause applications to go into a busy loop
if drivers queue events larger than 1 KiB, because drm_read() will
requeue the event and drm_poll() would never see the list of queued
events become empty and therefore always return immediately.
This patch increases the buffer for event reads to 4 KiB, so that all
events will be read at once. This ensures that at least one event can
always be dequeued, therefore avoiding the busy loop condition.
A complementary patch will be applied to the kernel to limit the size
of events to 1 KiB to ensure that versions of the libdrm library prior
to this change won't break. Fortunately, there currently aren't any
event producers that exceed the 1 KiB limit.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Fixes crash when/usr/share/libdrm/amdgpu.ids contains ASIC_ID_TABLE_NUM_ENTRIES + 1 entries.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102432
Fixes: 7e6bf88cac315a9fa41818cf72a7b5d18a2cb1fc (amdgpu: move asic id table to a separate file)
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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Fixes the tarball generation.
fixes: 9d133dd08720d80dfc8ce098bf0972 (tests/amdgpu: add uvd encode unit tests)
bug: https://bugs.freedesktop.org/show_bug.cgi?id=102391
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Look up BOs from the name table using the name parameter instead of
req.handle (which at this point is always zero).
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
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Define two macros to avoid building errors.
Fixes: 7e6bf88cac (amdgpu: move asic id table to a separate file)
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
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Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
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Fixes: 7d8c9464081634f053e16e5eac9655a12fae1dc4
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
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Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
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Reviewed-by: Daniel Stone <daniels@collabora.com>
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since bo_reference and bo_internal_free are
all only used by bo_free, so we just merge them
together
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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there is race issue between two threads on amdgpu_bo_reference and
amdgpu_bo_import, this patch tends to fix it by moving the
pthread_mutex_lock out of bo_free_internal and move to bo_reference
to cover the update_reference part.
The mutex_unlock in bo_import should also cover bo refcount
increasement.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Rob Clark <robdclark@gmail.com>
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`ring` cannot be non-null, so the label reduces to a simple return.
Then, there is no point initialising `ring` just to overwrite it before
anyone reads it.
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Rob Clark <robdclark@gmail.com>
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`pipe` cannot be non-null, so the label reduces to a simple return.
Then, there is no point initialising `pipe` just to overwrite it before
anyone reads it.
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Rob Clark <robdclark@gmail.com>
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Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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raven doesn't support VCE
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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raven doesn't support UVD decode
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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GCC 7 started warning when a switch case has neither a `break` nor
a "fallthrough" comment.
Let's be explicit that we meant to fall through here.
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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Analogous to previous commit (and the rest of the codebase), simply
discard the device if we cannot parse it.
Fixes: f8484ccbd12 ("xf86drm: Add USB support")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
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On ChromeOS devices, readdir() processes the directory in
the following order:
-NAME- -TYPE-
. n/a
.. n/a
vgem n/a
card1 DRM_BUS_PLATFORM
renderD129 DRM_BUS_PLATFORM
card0 DRM_BUS_PCI
renderD128 DRM_BUS_PCI
controlD64 DRM_BUS_PCI
In drmGetDevices2, after drmProcessPlatformDevice fails for
/dev/dri/card1, we don't process the remaining directory entries.
As such, Vulkan fails to initialize since Mesa uses drmGetDevices2.
To fix this, continue if drmProcessPlatformDevice fails.
Fixes: 7b1f37f474d ("xf86drm: Add platform and host1x bus support")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
[Emil: correct the host1x platforms as well]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
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Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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This just sends chunks to the kernel API for a single command
stream.
This should provide a more future proof and extensible API
for command submission.
v2: use amdgpu_bo_list_handle, add two helper functions to
access bo and context internals.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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These are just wrappers using the amdgpu device handle.
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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drmMalloc will zero out the memory for us
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
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It is safe to submit the full struct even on older kernels as such
kernels do not process the full struct. Without this change it
becomes quite challenging to extned the submit struct.
Freedreno has no special treatment too. See git commits
- freedreno: sync uapi header
- freedreno: add fence fd support
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Philipp Zabel <p.zabel@pengutronix.de>
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No functional change. Just organizing the code
so it gets clear for future platforms.
Paulo deserves credits becuase he was the one
that just noticed this IS_9XX was in the wrong position
after CNL patches got introduced.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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As far as I understand, IS_9XX should return true for it.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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This got lost on rebase, I believe
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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By the Spec all CNL Y skus are 2+2, i.e. GT2.
This is a copy of merged i915's
commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")
v2: Add kernel commit id for reference.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
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Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.
This is a copy of merged i915's
commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.")
v2: Remove PCI IDs for SKU not mentioned in spec.
v3: Add kernel commit id for reference.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
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Add the PCI IDs for U SKU IN CFL by following the spec.
v2: Update IDs
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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Add the PCI IDs for H SKU IN CFL by following the spec.
v2: Update IDs
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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Add the PCI IDs for S SKU IN CFL by following the spec.
v2: Update IDs.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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These ioctls are now in drm next so add the first set of libdrm APIs.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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This syncs the drm.h header with my drm-next branch as of
6d61e70ccc21606ffb8a0a03bd3aba24f659502b.
It brings over the semaphore API changes.
Generated using make headers_install.
Generated from git://people.freedesktop.org/~airlied/linux drm-next commit 6d61e70ccc2.
[airlied: I split patch in two, split reviewed by across both]
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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This syncs the amdgpu_drm header with my drm-next branch as of
6d61e70ccc21606ffb8a0a03bd3aba24f659502b.
It brings over the VM and semaphore API changes.
Generated using make headers_install.
Generated from git://people.freedesktop.org/~airlied/linux drm-next commit 6d61e70ccc2.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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