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2017-09-04amdgpu: Do not write beyond allocated memory when parsing idsstaging/helpersstaging/baseJan Vesely1-7/+8
Fixes crash when/usr/share/libdrm/amdgpu.ids contains ASIC_ID_TABLE_NUM_ENTRIES + 1 entries. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102432 Fixes: 7e6bf88cac315a9fa41818cf72a7b5d18a2cb1fc (amdgpu: move asic id table to a separate file) Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2017-08-31tests/amdgpu: add missing header to SOURCESAlex Deucher1-1/+2
Fixes the tarball generation. fixes: 9d133dd08720d80dfc8ce098bf0972 (tests/amdgpu: add uvd encode unit tests) bug: https://bugs.freedesktop.org/show_bug.cgi?id=102391 Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-24configure.ac: Bump version to 2.4.83Daniel Stone1-1/+1
2017-08-21etnaviv: fix etna_bo_from_namePhilipp Zabel1-1/+1
Look up BOs from the name table using the name parameter instead of req.handle (which at this point is always zero). Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com> Reviewed-by: Daniel Stone <daniels@collabora.com>
2017-08-21android: amdgpu: fix build breakChih-Wei Huang1-0/+6
Define two macros to avoid building errors. Fixes: 7e6bf88cac (amdgpu: move asic id table to a separate file) Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
2017-08-21android: add rules to build amdgpu.idsChih-Wei Huang1-0/+9
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
2017-08-21drmsltest: Check expected neighboursJan Vesely1-8/+20
Fixes: 7d8c9464081634f053e16e5eac9655a12fae1dc4 Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-16tests/amdgpu: add uvd encode unit testsBoyuan Zhang6-1/+1050
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher at amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2017-08-15drm: Pull new modifier uapi into drm_fourcc and drm_modeJason Ekstrand2-0/+81
Reviewed-by: Daniel Stone <daniels@collabora.com>
2017-08-08amdgpu: merge and cleanup amdgpu_bo_freeMonk Liu2-56/+29
since bo_reference and bo_internal_free are all only used by bo_free, so we just merge them together Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-08amdgpu: fix race issue between two bo functions(v2)Monk Liu2-6/+12
there is race issue between two threads on amdgpu_bo_reference and amdgpu_bo_import, this patch tends to fix it by moving the pthread_mutex_lock out of bo_free_internal and move to bo_reference to cover the update_reference part. The mutex_unlock in bo_import should also cover bo refcount increasement. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-07amdgpu: fix missing mutex unlock before returnMonk Liu1-0/+1
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-07freedreno: prevent deadlock in error pathEric Engestrom1-0/+1
Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Rob Clark <robdclark@gmail.com>
2017-08-07freedreno/msm: remove dead error pathEric Engestrom1-6/+2
`ring` cannot be non-null, so the label reduces to a simple return. Then, there is no point initialising `ring` just to overwrite it before anyone reads it. Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Rob Clark <robdclark@gmail.com>
2017-08-07freedreno: remove dead error pathEric Engestrom1-7/+3
`pipe` cannot be non-null, so the label reduces to a simple return. Then, there is no point initialising `pipe` just to overwrite it before anyone reads it. Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Rob Clark <robdclark@gmail.com>
2017-08-04test/amdgpu: fix test failure for SIFlora Cui3-124/+228
Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-04tests/amdgpu: bypass VCE tests on ravenHawking Zhang1-0/+17
raven doesn't support VCE Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-04tests/amdgpu: bypass UVD CS tests on ravenHawking Zhang1-0/+17
raven doesn't support UVD decode Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-02amdgpu: Add FX-9800P Bristol Ridge iGPU idJan Vesely1-0/+1
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2017-08-01radeon: add fallthrough annotationEric Engestrom1-0/+1
GCC 7 started warning when a switch case has neither a `break` nor a "fallthrough" comment. Let's be explicit that we meant to fall through here. Signed-off-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2017-07-20xf86drm: continue with next device if drmProcessUsbDevice failsEmil Velikov1-1/+1
Analogous to previous commit (and the rest of the codebase), simply discard the device if we cannot parse it. Fixes: f8484ccbd12 ("xf86drm: Add USB support") Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-07-20xf86drm: continue after drmProcessPlatformDevice failureGurchetan Singh1-2/+2
On ChromeOS devices, readdir() processes the directory in the following order: -NAME- -TYPE- . n/a .. n/a vgem n/a card1 DRM_BUS_PLATFORM renderD129 DRM_BUS_PLATFORM card0 DRM_BUS_PCI renderD128 DRM_BUS_PCI controlD64 DRM_BUS_PCI In drmGetDevices2, after drmProcessPlatformDevice fails for /dev/dri/card1, we don't process the remaining directory entries. As such, Vulkan fails to initialize since Mesa uses drmGetDevices2. To fix this, continue if drmProcessPlatformDevice fails. Fixes: 7b1f37f474d ("xf86drm: Add platform and host1x bus support") Reviewed-by: Emil Velikov <emil.velikov@collabora.com> [Emil: correct the host1x platforms as well] Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-07-19configure.ac: bump version for releaseLucas Stach1-1/+1
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2017-07-19amdgpu: add new symbols to tests.Dave Airlie1-0/+7
2017-07-19drm/amdgpu: add new low overhead command submission API. (v2)Dave Airlie2-0/+77
This just sends chunks to the kernel API for a single command stream. This should provide a more future proof and extensible API for command submission. v2: use amdgpu_bo_list_handle, add two helper functions to access bo and context internals. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-07-19drm/amdgpu: add syncobj create/destroy/import/export apisDave Airlie2-1/+92
These are just wrappers using the amdgpu device handle. Acked-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-07-07Remove redundant memclearcoypu1-2/+0
drmMalloc will zero out the memory for us Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-07-06etnaviv: submit full struct drm_etnaviv_gem_submitChristian Gmeiner1-7/+1
It is safe to submit the full struct even on older kernels as such kernels do not process the full struct. Without this change it becomes quite challenging to extned the submit struct. Freedreno has no special treatment too. See git commits - freedreno: sync uapi header - freedreno: add fence fd support Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-06-30intel/intel_chipset: Move IS_9XX below IS_GEN10.Rodrigo Vivi1-9/+9
No functional change. Just organizing the code so it gets clear for future platforms. Paulo deserves credits becuase he was the one that just noticed this IS_9XX was in the wrong position after CNL patches got introduced. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-30intel: add GEN10 to IS_9XX.Paulo Zanoni1-1/+2
As far as I understand, IS_9XX should return true for it. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-30intel/gen10: Add missed gen10 stuffBen Widawsky2-1/+5
This got lost on rebase, I believe Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-30intel: Add Cannonlake PCI IDs for Y-skus.Rodrigo Vivi1-1/+15
By the Spec all CNL Y skus are 2+2, i.e. GT2. This is a copy of merged i915's commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.") v2: Add kernel commit id for reference. Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
2017-06-30intel: Add Cannonlake PCI IDs for U-skus.Rodrigo Vivi1-0/+13
Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is a copy of merged i915's commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.") v2: Remove PCI IDs for SKU not mentioned in spec. v3: Add kernel commit id for reference. Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
2017-06-29intel: PCI Ids for U SKU in CFLAnusha Srivatsa1-1/+11
Add the PCI IDs for U SKU IN CFL by following the spec. v2: Update IDs Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-29intel: PCI Ids for H SKU in CFLAnusha Srivatsa1-1/+7
Add the PCI IDs for H SKU IN CFL by following the spec. v2: Update IDs Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-29intel: PCI Ids for S SKU in CFLAnusha Srivatsa1-1/+16
Add the PCI IDs for S SKU IN CFL by following the spec. v2: Update IDs. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-29libdrm: add drm syncobj create/destroy/import/exportDave Airlie2-0/+89
These ioctls are now in drm next so add the first set of libdrm APIs. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-29drm: update drm.h to latest in drm-next.Dave Airlie1-0/+26
This syncs the drm.h header with my drm-next branch as of 6d61e70ccc21606ffb8a0a03bd3aba24f659502b. It brings over the semaphore API changes. Generated using make headers_install. Generated from git://people.freedesktop.org/~airlied/linux drm-next commit 6d61e70ccc2. [airlied: I split patch in two, split reviewed by across both] Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-27amdgpu: sync amdgpu_drm with kernel.Dave Airlie1-1/+53
This syncs the amdgpu_drm header with my drm-next branch as of 6d61e70ccc21606ffb8a0a03bd3aba24f659502b. It brings over the VM and semaphore API changes. Generated using make headers_install. Generated from git://people.freedesktop.org/~airlied/linux drm-next commit 6d61e70ccc2. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-22headers: Update drm_fourcc and vc4_drm.h with new VC4 tiling UAPI.Eric Anholt2-4/+41
Taken from make headers_install of drm-misc-next (34c8ea400ff6383b028f63df2453914163afc07c) Reviewed-by: Daniel Stone <daniels@collabora.com>
2017-06-13amdgpu: move asic id table to a separate fileXiaojie Yuan10-173/+445
v2: fix an off by one error and leading white spaces v3: use thread safe strtok_r(); initialize len before calling getline(); change printf() to drmMsg(); add initial amdgpu.ids v4: integrate some recent internal changes, including format changes v5: fix line number for empty/commented lines; realloc to save memory; indentation changes v6: remove a line error v7: [Michel Dänzer] * Move amdgpu.ids to new data directory * Remove placeholder entries from amdgpu.ids * Set libdrmdatadir variable in configure.ac instead of Makefile.am [Emil Velikov] * Use isblank() instead of open-coding it [Emil Velikov] * Don't leak asic_id_table memory if realloc fails [Emil Velikov] * Check and bump table_max_size at the beginning of the while loop [Emil Velikov] * Initialize table_max_size to the number of entries in data/amdgpu.ids v8: [Michel Dänzer] * Make sure amdgpu_asic_id.c gets rebuilt when amdgpu.ids changes Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Samuel Li <Samuel.Li@amd.com>
2017-06-13amdgpu: Add .editorconfig file for amdgpu coding styleMichel Dänzer1-0/+9
The .editorconfig file in the toplevel directory doesn't match. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-12tests/amdgpu: s/uvd_messages.h/decode_messages.h/ in Makefile.amMichel Dänzer1-1/+1
Fixes make distcheck with amdgpu enabled. Fixes: ec65d1980912 ("tests/amdgpu: rename uvd messages to decode messages") Trivial.
2017-06-06tests/amdgpu: Fix device_id optionTom St Denis1-9/+9
The device_id option [-d] was badly broken. This commit fixes the width (was 8 is now 16 bits) as well as enables searches without specifying a bus id. It was also comparing "dev" from the bus field which is not the PCI device id. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
2017-06-05tests/amdgpu: implement vcn dec unit testsLeo Liu2-3/+166
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2017-06-05tests/amdgpu: add vcn tests support and setsLeo Liu4-1/+300
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2017-06-05tests/amdgpu: move decode sum to commonLeo Liu2-1/+3
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2017-06-05tests/amdgpu: separate decode messagesLeo Liu2-1/+5
AVC decode messages will be common with VCN decode Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2017-06-05tests/amdgpu: rename uvd messages to decode messagesLeo Liu2-5/+5
It will be shared with VCN decode Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2017-06-03headers: sync drm_sarea.h with airlied/drm-nextEric Engestrom1-0/+8
Adds the C++ extern guards from ebbb0e5cfd2ceb1150b1 drm: add extern C guard for the UAPI headers Generated using `make headers_install` from airlied/drm-next at commit 2a1720376adda5ecf8e636fbfb05339c7dad1c55 Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-08 01:08:08 +0000