diff options
| author | Gwenole Beauchesne <gwenole.beauchesne@intel.com> | 2011-08-24 16:59:38 +0200 |
|---|---|---|
| committer | Gwenole Beauchesne <gwenole.beauchesne@intel.com> | 2011-08-25 14:28:40 +0200 |
| commit | da2f0a4021d81530ce057f7cfbf560e5eb5c3bdd (patch) | |
| tree | e1dc84af45e7c1eb5f15fd1d6f589fd06c5b241c | |
| parent | 8463756b59ab15dabba7e7c3616c23c2c7ca4ee3 (diff) | |
Fix H.264 MC kernel bootstrap for Ironlake.
| -rw-r--r-- | src/shaders/h264/mc/AllAVC.asm | 15 | ||||
| -rw-r--r-- | src/shaders/h264/mc/Makefile.am | 19 |
2 files changed, 27 insertions, 7 deletions
diff --git a/src/shaders/h264/mc/AllAVC.asm b/src/shaders/h264/mc/AllAVC.asm index 045ddf3..17bef16 100644 --- a/src/shaders/h264/mc/AllAVC.asm +++ b/src/shaders/h264/mc/AllAVC.asm @@ -41,7 +41,20 @@ #define HW_SCOREBOARD // HW Scoreboard should be enabled for ILK and beyond
#undef SW_SCOREBOARD // SW Scoreboard should be disabled for ILK and beyond
#endif // DEV_CTG
-#include "export.inc"
+#ifdef BOOTSTRAP
+# ifdef ENABLE_ILDB
+# define ALL_SPAWNED_UV_ILDB_FRAME_IP 0
+# define SLEEP_ENTRY_UV_ILDB_FRAME_IP 0
+# define POST_SLEEP_UV_ILDB_FRAME_IP 0
+# define ALL_SPAWNED_Y_ILDB_FRAME_IP 0
+# define SLEEP_ENTRY_Y_ILDB_FRAME_IP 0
+# define POST_SLEEP_Y_ILDB_FRAME_IP 0
+# endif
+#elif defined(DEV_ILK)
+# include "export.inc.gen5"
+#elif defined(DEV_CTG)
+# include "export.inc"
+#endif
#if defined(_EXPORT)
#include "AllAVC_Export.inc"
#elif defined(_BUILD)
diff --git a/src/shaders/h264/mc/Makefile.am b/src/shaders/h264/mc/Makefile.am index 6608e4d..e514801 100644 --- a/src/shaders/h264/mc/Makefile.am +++ b/src/shaders/h264/mc/Makefile.am @@ -184,14 +184,21 @@ SUFFIXES = .g4a .g4b .gen5.asm rm $*.g4m $(INTEL_MC_GEN5_ASM): $(INTEL_MC_ASM) $(INTEL_MC_INC) $(INTEL_ILDB_ASM) - cpp -D DEV_ILK -I ../ildb/ AllAVC.asm > _mc.$@; \ - ../../gpp.py _mc.$@ $@ ; \ - rm _mc.$@ + cpp -DDEV_ILK -DBOOTSTRAP -I ../ildb/ AllAVC.asm > _mc0.$@ && \ + ../../gpp.py _mc0.$@ $@ && \ + intel-gen4asm -l list -a -e tmp.$(INTEL_MC_EXPORT_GEN5) -g 5 $@ \ + -o /dev/null && \ + mv tmp.$(INTEL_MC_EXPORT_GEN5) $(INTEL_MC_EXPORT_GEN5) && \ + cpp -DDEV_ILK -I ../ildb/ AllAVC.asm > _mc1.$@ && \ + ../../gpp.py _mc1.$@ $@ && \ + rm _mc0.$@ _mc1.$@ $(INTEL_MC_G4B_GEN5): $(INTEL_MC_GEN5_ASM) - intel-gen4asm -l list -a -e _export.inc.gen5 -o $@ -g 5 $<; \ - cat _export.inc.gen5 | sed "s/_IP/_IP_GEN5/g" > $(INTEL_MC_EXPORT_GEN5); \ - rm _export.inc.gen5 + intel-gen4asm -l list -a -e tmp.$(INTEL_MC_EXPORT_GEN5) -g 5 $< \ + -o $@ && \ + cat tmp.$(INTEL_MC_EXPORT_GEN5) | sed "s/_IP/_IP_GEN5/g" \ + > $(INTEL_MC_EXPORT_GEN5) && \ + rm tmp.$(INTEL_MC_EXPORT_GEN5) $(INTEL_G4B): $(INTEL_G4I) |