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authorMarek Olšák <marek.olsak@amd.com>2015-05-15 00:16:41 +0200
committerAlex Deucher <alexander.deucher@amd.com>2015-08-05 13:47:50 -0400
commit7c50f0d9847f855d6d008840931898f001faad8c (patch)
tree110ab5f529c14676193bc25ab72856bd4368cecf /include
parent12a23b1964f04d7451bad4ef246f3daebe2ef12a (diff)
amdgpu: add new AMDGPU_TILING flags
Copied from the kernel. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
Diffstat (limited to 'include')
-rw-r--r--include/drm/amdgpu_drm.h40
1 files changed, 22 insertions, 18 deletions
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 81b495ed..dc4caf16 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -199,24 +199,28 @@ struct drm_amdgpu_gem_userptr {
uint32_t handle;
};
-#define AMDGPU_TILING_MACRO 0x1
-#define AMDGPU_TILING_MICRO 0x2
-#define AMDGPU_TILING_SWAP_16BIT 0x4
-#define AMDGPU_TILING_R600_NO_SCANOUT AMDGPU_TILING_SWAP_16BIT
-#define AMDGPU_TILING_SWAP_32BIT 0x8
-/* this object requires a surface when mapped - i.e. front buffer */
-#define AMDGPU_TILING_SURFACE 0x10
-#define AMDGPU_TILING_MICRO_SQUARE 0x20
-#define AMDGPU_TILING_EG_BANKW_SHIFT 8
-#define AMDGPU_TILING_EG_BANKW_MASK 0xf
-#define AMDGPU_TILING_EG_BANKH_SHIFT 12
-#define AMDGPU_TILING_EG_BANKH_MASK 0xf
-#define AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16
-#define AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf
-#define AMDGPU_TILING_EG_TILE_SPLIT_SHIFT 24
-#define AMDGPU_TILING_EG_TILE_SPLIT_MASK 0xf
-#define AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28
-#define AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
+/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
+#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
+#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
+#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
+#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
+#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
+#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
+#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
+#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
+#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
+#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
+#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
+#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
+#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
+#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
+#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
+#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
+
+#define AMDGPU_TILING_SET(field, value) \
+ (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
+#define AMDGPU_TILING_GET(value, field) \
+ (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2