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2018-03-27broadcom/vc5: Fix padding of NPOT miplevels >= 2.Eric Anholt1-3/+8
2018-03-28ac/radeonsi: pass bindless bool to load_sampler_desc()Timothy Arceri4-5/+14
2018-03-28st/glsl_to_nir: set driver location for bindless images and samplersTimothy Arceri1-1/+2
2018-03-28radeonsi/nir: set uses_bindless_samplers for samplersTimothy Arceri1-0/+3
2018-03-28nir: add bindless to nir dataTimothy Arceri2-0/+7
2018-03-27i965: Drop unnecessary bo->align field.Kenneth Graunke3-10/+0
2018-03-27i965: Drop unused alignment parameter from brw_bo_alloc().Kenneth Graunke14-26/+25
2018-03-27i965: Drop alignment parameter from bo_alloc_internal().Kenneth Graunke1-7/+6
2018-03-27i965: Drop BO_ALLOC_BUSY in intel_miptree_create_for_bo().Kenneth Graunke1-2/+2
2018-03-27i965: Drop PIPE_CONTROL_NO_WRITE from various calls.Kenneth Graunke4-11/+4
2018-03-27nir/intrinsics: Don't report negative dest_componentsJason Ekstrand1-1/+1
2018-03-27intel/fs: Don't emit a des copy for image ops with has_dest == falseJason Ekstrand1-3/+6
2018-03-27nvc0/ir: fix INTERP_* with indirect inputsIlia Mirkin1-3/+4
2018-03-28nir: fix crash in loop unroll corner caseTimothy Arceri1-5/+12
2018-03-28st/glsl_to_nir: correctly handle arrays packed across multiple varsTimothy Arceri1-1/+23
2018-03-28radeonsi/nir: fix input processing for packed varyingsTimothy Arceri1-3/+2
2018-03-28ac/nir_to_llvm: fix component packing for double outputsTimothy Arceri1-1/+3
2018-03-28st/glsl_to_nir: fix driver location for dual-slot packed doublesTimothy Arceri1-6/+16
2018-03-28radeonsi/nir: fix scanning of multi-slot output varyingsTimothy Arceri1-109/+127
2018-03-27broadcom/vc5: Fix RG16I/UI texture sampling.Eric Anholt1-2/+2
2018-03-27nir: fix generated nir_intrinsics.c for MSVCRob Clark1-0/+4
2018-03-27docs: update calendar 18.0.0 is outEmil Velikov1-22/+4
2018-03-27docs: add news item and link release notes for 18.0.0Emil Velikov2-0/+8
2018-03-27docs: add sha256 checksums for 18.0.0Emil Velikov1-1/+2
2018-03-27docs: Update 18.0.0 release notesEmil Velikov2-74/+320
2018-03-27nir: mako all the intrinsicsRob Clark11-619/+727
2018-03-27nir: fix per_vertex_output intrinsicRob Clark1-1/+1
2018-03-27glsl_types: fix build break with intel/msvc compilerRob Clark1-83/+24
2018-03-27mesa: add GL_HALF_FLOAT as supported type to readpixelsLin Johnson1-0/+2
2018-03-26broadcom/vc5: Fix swizzling of RGB10_A2UI render targets.Eric Anholt1-1/+1
2018-03-26broadcom/vc5: Fix extraneous register index in QIR dumping of TLBU writes.Eric Anholt1-0/+1
2018-03-26broadcom/vc5: Implement workaround for GFXH-1431.Eric Anholt1-1/+5
2018-03-26broadcom/vc5: Fix EZ disabling and allow using GT/GE direction as well.Eric Anholt5-21/+111
2018-03-26broadcom/vc5: Disable TF on V3D 4.x when drawing with queries disabled.Eric Anholt2-0/+8
2018-03-26broadcom/vc5: Disable transform feedback on V3D 4.x at the end of the job.Eric Anholt3-5/+29
2018-03-26broadcom/vc5: Move the BCL epilogue code to a per-version compile.Eric Anholt5-24/+67
2018-03-26broadcom/vc5: Fix transform feedback in the presence of point size.Eric Anholt3-4/+23
2018-03-26broadcom/vc5: Split transform feedback specs update from buffers.Eric Anholt1-27/+32
2018-03-26broadcom/vc5: Limit each transform feedback data spec to 16 dwords.Eric Anholt2-14/+31
2018-03-26gallium/u_vbuf: Protect against overflow with large instance divisors.Eric Anholt1-1/+10
2018-03-26st: Allow accelerated CopyTexImage from RGBA to RGB.Eric Anholt1-6/+26
2018-03-26winsys/amdgpu: always allow GTT placements on APUsMarek Olšák1-7/+5
2018-03-26radeonsi: don't reallocate on DMABUF export if local BOs are disabledMarek Olšák4-5/+9
2018-03-27glsl: fix infinite loop caused by bug in loop unrolling passTimothy Arceri1-1/+1
2018-03-26gallium: Do not add -Wframe-address option for gcc <= 4.4.Vinson Lee1-1/+1
2018-03-26gallium: Correct minor typo in header commentsAlyssa Rosenzweig1-1/+1
2018-03-26intel/aubinator_error_decode: Decode more registers.Rafael Antognolli1-0/+12
2018-03-26intel/genxml: Add SAMPLER_INSTDONE register.Rafael Antognolli6-0/+139
2018-03-26intel/genxml: Add ROW_INSTDONE register.Rafael Antognolli6-0/+114
2018-03-26intel/genxml: Add SC_INSTDONE register.Rafael Antognolli6-0/+140
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-08 09:12:33 +0000