diff options
| author | Rafael Antognolli <rafael.antognolli@intel.com> | 2017-10-04 09:51:58 -0700 |
|---|---|---|
| committer | Rafael Antognolli <rafael.antognolli@intel.com> | 2017-10-12 10:28:39 -0700 |
| commit | 05a8386b710f4e620bcaa0cbf6d5cddf0ad02d53 (patch) | |
| tree | d8255367946c51e15397474fe68b6b79e0e36d0f | |
| parent | ae50c3cee03276232d5f7b0367c2da635e490c19 (diff) | |
Use brw_emit_pipe_control_flush with read and write flushes.wip/cnl_wa
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_pipe_control.c | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index 3adccb8867..82abad2eab 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -301,16 +301,6 @@ gen7_emit_cs_stall_flush(struct brw_context *brw) brw->workaround_bo, 0, 0); } -static void -brw_flush_write_caches(struct brw_context *brw) { - brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CACHE_FLUSH_BITS); -} - -static void -brw_flush_read_caches(struct brw_context *brw) { - brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CACHE_INVALIDATE_BITS); -} - /** * From Gen10 Workarounds page in h/w specs: * WaSampleOffsetIZ: @@ -344,8 +334,8 @@ gen10_emit_wa_lri_to_cache_mode_zero(struct brw_context *brw) /* Before changing the value of CACHE_MODE_0 register, GFX pipeline must * be idle; i.e., full flush is required. */ - brw_flush_write_caches(brw); - brw_flush_read_caches(brw); + brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CACHE_FLUSH_BITS | + PIPE_CONTROL_CACHE_INVALIDATE_BITS); /* Write to CACHE_MODE_0 (0x7000) */ BEGIN_BATCH(3); |