radeon: use software tiling if accelerated blit isn't available

1 files changed, 16 insertions, 3 deletions

diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c
index 8d6394a934..2e0de7cd64 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texture.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.c
@@ -45,7 +45,7 @@
 #include "radeon_common.h"
 
 #include "radeon_mipmap_tree.h"
-
+#include "radeon_tile.h"
 
 void copy_rows(void* dst, GLuint dststride, const void* src, GLuint srcstride,
 	GLuint numrows, GLuint rowsize)
@@ -698,13 +698,26 @@ static void radeon_store_teximage(GLcontext* ctx, int dims,
 
 	/* Do the tiled blit to miptree now */
 	if (tiled_texture) {
-		assert(rmesa->vtbl.blit);
+		unsigned succeeded = 0;
 		unsigned alignedWidth = dstRowStride / _mesa_get_format_bytes(texImage->TexFormat);
-		rmesa->vtbl.blit(ctx, tmp_bo, 0, texImage->TexFormat, alignedWidth,
+		if (rmesa->vtbl.blit) {
+			succeeded = rmesa->vtbl.blit(ctx, tmp_bo, 0, texImage->TexFormat, alignedWidth,
 						width, height, 0, 0,
 						image->mt->bo, radeon_miptree_image_offset(image->mt, face, level),
 						texImage->TexFormat, alignedWidth, texImage->Width, texImage->Height,
 						xoffset, yoffset, width, height, 0);
+		}
+
+		if (!succeeded) {
+			radeon_bo_map(tmp_bo, 0);
+			radeon_bo_map(image->mt->bo, 1);
+			/*TODO: for subteximage untile orig, merge orig & new, tile merged */
+			tile_image(tmp_bo->ptr, alignedWidth, image->mt->bo->ptr, alignedWidth,
+					   texImage->TexFormat, texImage->Width, texImage->Height);
+			radeon_bo_unmap(tmp_bo);
+			radeon_bo_unmap(image->mt->bo);
+		}
+
 		radeon_bo_unref(tmp_bo);
 	}
 }