[lanai] Add more tests for assembly of conditional ALU ops

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275081 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 363 insertions, 5 deletions

diff --git a/test/MC/Lanai/conditional_inst.s b/test/MC/Lanai/conditional_inst.s
new file mode 100644
index 00000000000..58d9b634e4b
--- /dev/null
+++ b/test/MC/Lanai/conditional_inst.s
@@ -0,0 +1,77 @@
+! RUN: llvm-mc -arch=lanai -show-encoding -show-inst < %s | FileCheck %s
+
+.text
+   .align 4
+   .global jump1
+
+    bt %r5
+! CHECK: encoding: [0xc1,0x00,0x2d,0x00]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} JR{{$}}
+! CHECK-NEXT:  <MCOperand Reg:12>>
+
+! BR classes
+    bt 0x1234
+! CHECK: encoding: [0xe0,0x00,0x12,0x34]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} BT{{$}}
+! CHECK-NEXT: <MCOperand Imm:4660>
+
+jump1:
+    blt 2000
+! CHECK: encoding: [0xec,0x00,0x07,0xd1]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} BRCC{{$}}
+! CHECK-NEXT: <MCOperand Imm:2000>
+! CHECK-NEXT: <MCOperand Imm:13>
+
+jump2:
+    blt jump1
+! CHECK: encoding: [0b1110110A,A,A,0x01'A']
+! CHECK-NEXT: fixup A - offset: 0, value: jump1, kind: FIXUP_LANAI_25
+! CHECK-NEXT: <MCInst #{{[0-9]+}} BRCC{{$}}
+! CHECK-NEXT: <MCOperand Expr:(jump1)>
+! CHECK-NEXT: <MCOperand Imm:13>
+
+    bpl jump2
+! CHECK: encoding: [0b1110101A,A,A,A]
+! CHECK-NEXT: fixup A - offset: 0, value: jump2, kind: FIXUP_LANAI_25
+! CHECK-NEXT: <MCInst #{{[0-9]+}} BRCC{{$}}
+! CHECK-NEXT: <MCOperand Expr:(jump2)>
+! CHECK-NEXT: <MCOperand Imm:10>
+
+    bt .
+! CHECK:      .Ltmp{{[0-9]+}}
+! CHECK-NEXT:   bt .Ltmp{{[0-9]+}}
+! CHECK:      encoding: [0b1110000A,A,A,A]
+! CHECK-NEXT:   fixup A - offset: 0, value: .Ltmp0, kind: FIXUP_LANAI_25
+! CHECK-NEXT: <MCInst #{{[0-9]+}} BT{{$}}
+! CHECK-NEXT:   <MCOperand Expr:(.Ltmp0)>
+
+! SCC
+    spl %r19
+! CHECK: encoding: [0xea,0x4c,0x00,0x02]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} SCC{{$}}
+! CHECK-NEXT: <MCOperand Reg:26>
+! CHECK-NEXT: <MCOperand Imm:10>
+
+! BRR
+    bf.r 0x456
+! CHECK: encoding: [0xe1,0x00,0x04,0x57]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} BRR{{$}}
+! CHECK-NEXT: <MCOperand Imm:1110>
+! CHECK-NEXT: <MCOperand Imm:1>
+
+! Conditional ALU
+  add.ge %r13, %r14, %r18
+! CHECK: encoding: [0xc9,0x34,0x70,0x06]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} ADD_R
+! CHECK-NEXT:  <MCOperand Reg:25>
+! CHECK-NEXT:  <MCOperand Reg:20>
+! CHECK-NEXT:  <MCOperand Reg:21>
+! CHECK-NEXT:  <MCOperand Imm:12>>
+
+  add.f %r13, %r14, %r18
+! CHECK: encoding: [0xc9,0x36,0x70,0x00]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} ADD_F_R
+! CHECK-NEXT:  <MCOperand Reg:25>
+! CHECK-NEXT:  <MCOperand Reg:20>
+! CHECK-NEXT:  <MCOperand Reg:21>
+! CHECK-NEXT:  <MCOperand Imm:0>>
diff --git a/test/MC/Lanai/ctrl-instructions.s b/test/MC/Lanai/ctrl-instructions.s
index 05e7a958227..2e5b2f263f4 100644
--- a/test/MC/Lanai/ctrl-instructions.s
+++ b/test/MC/Lanai/ctrl-instructions.s
@@ -1,13 +1,13 @@
-// RUN: llvm-mc -triple lanai-unknown-unknown -show-encoding -o - %s | FileCheck %s
+! RUN: llvm-mc -triple lanai-unknown-unknown -show-encoding -o - < %s | FileCheck %s
 
-// CHECK: bt .Ltmp0 ! encoding: [0b1110000A,A,A,A]
-// CHECK-NEXT:      ! fixup A - offset: 0, value: .Ltmp0, kind: FIXUP_LANAI_25
+! CHECK: bt .Ltmp0 ! encoding: [0b1110000A,A,A,A]
+! CHECK-NEXT:      ! fixup A - offset: 0, value: .Ltmp0, kind: FIXUP_LANAI_25
   bt 1f
   nop
 1:
 
-// CHECK: bt foo    ! encoding: [0b1110000A,A,A,A]
-// CHECK-NEXT:      !   fixup A - offset: 0, value: foo, kind: FIXUP_LANAI_25
+! CHECK: bt foo    ! encoding: [0b1110000A,A,A,A]
+! CHECK-NEXT:      !   fixup A - offset: 0, value: foo, kind: FIXUP_LANAI_25
   bt foo
   nop
 
diff --git a/test/MC/Lanai/memory.s b/test/MC/Lanai/memory.s
new file mode 100644
index 00000000000..d34f917c740
--- /dev/null
+++ b/test/MC/Lanai/memory.s
@@ -0,0 +1,247 @@
+! RUN: llvm-mc -arch=lanai -show-encoding -show-inst < %s | FileCheck %s
+
+! Checking the machine instructions generated from ASM instructions for ALU
+! operations.
+
+! RM class
+    ld [%r7], %r6
+! CHECK: encoding: [0x83,0x1c,0x00,0x00]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:13>
+! CHECK-NEXT: <MCOperand Reg:14>
+! CHECK-NEXT: <MCOperand Imm:0>
+! CHECK-NEXT: <MCOperand Imm:0>
+
+    ld [%r6], %r6
+! CHECK: encoding: [0x83,0x18,0x00,0x00]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:13>
+! CHECK-NEXT: <MCOperand Reg:13>
+! CHECK-NEXT: <MCOperand Imm:0>
+! CHECK-NEXT: <MCOperand Imm:0>
+
+     st %r6, [%r7]
+! CHECK: encoding: [0x93,0x1c,0x00,0x00]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} SW_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:13>
+! CHECK-NEXT: <MCOperand Reg:14>
+! CHECK-NEXT: <MCOperand Imm:0>
+! CHECK-NEXT: <MCOperand Imm:0>
+
+    ld 0x123[%r7*], %r6
+! CHECK: encoding: [0x83,0x1d,0x01,0x23]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:13>
+! CHECK-NEXT: <MCOperand Reg:14>
+! CHECK-NEXT: <MCOperand Imm:291>
+! CHECK-NEXT: <MCOperand Imm:128>
+
+    ld [%r7--], %r6
+! CHECK: encoding: [0x83,0x1d,0xff,0xfc]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:13>
+! CHECK-NEXT: <MCOperand Reg:14>
+! CHECK-NEXT: <MCOperand Imm:-4>
+! CHECK-NEXT: <MCOperand Imm:128>
+
+    ld 0x123[%r7], %r6
+! CHECK: encoding: [0x83,0x1e,0x01,0x23]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:13>
+! CHECK-NEXT: <MCOperand Reg:14>
+! CHECK-NEXT: <MCOperand Imm:291>
+! CHECK-NEXT: <MCOperand Imm:0>
+
+    ld 0x123[*%r7], %r6
+! CHECK: encoding: [0x83,0x1f,0x01,0x23]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:13>
+! CHECK-NEXT: <MCOperand Reg:14>
+! CHECK-NEXT: <MCOperand Imm:291>
+! CHECK-NEXT: <MCOperand Imm:64>
+
+    ld [--%r7], %r6
+! CHECK: encoding: [0x83,0x1f,0xff,0xfc]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:13>
+! CHECK-NEXT: <MCOperand Reg:14>
+! CHECK-NEXT: <MCOperand Imm:-4>
+! CHECK-NEXT: <MCOperand Imm:64>
+
+    st %r6, [%r7++]
+! CHECK: encoding: [0x93,0x1d,0x00,0x04]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} SW_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:13>
+! CHECK-NEXT: <MCOperand Reg:14>
+! CHECK-NEXT: <MCOperand Imm:4>
+! CHECK-NEXT: <MCOperand Imm:128>
+
+    st.h %r6, [%r7++]
+! CHECK: encoding: [0xf3,0x1f,0x24,0x02]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} STH_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:13>
+! CHECK-NEXT: <MCOperand Reg:14>
+! CHECK-NEXT: <MCOperand Imm:2>
+! CHECK-NEXT: <MCOperand Imm:128>>
+
+    ld.b [--%r7], %r6
+! CHECK: encoding: [0xf3,0x1f,0x4f,0xff]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDBs_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:13>
+! CHECK-NEXT: <MCOperand Reg:14>
+! CHECK-NEXT: <MCOperand Imm:-1>
+! CHECK-NEXT: <MCOperand Imm:64>>
+
+! Largest RM value before SLS encoding is used
+    ld [0x7fff], %r7
+! CHECK: encoding: [0x83,0x82,0x7f,0xff]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:14>
+! CHECK-NEXT: <MCOperand Reg:7>
+! CHECK-NEXT: <MCOperand Imm:32767>
+! CHECK-NEXT: <MCOperand Imm:0>
+
+    ld [0x8000], %r7
+! CHECK: encoding: [0xf3,0x80,0x80,0x00]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDADDR{{$}}
+! CHECK-NEXT: <MCOperand Reg:14>
+! CHECK-NEXT: <MCOperand Imm:32768>
+
+! Negative RM value
+    ld [0xfffffe8c], %pc
+! CHECK: encoding: [0x81,0x02,0xfe,0x8c]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:2>
+! CHECK-NEXT: <MCOperand Reg:7>
+! CHECK-NEXT: <MCOperand Imm:-372>
+! CHECK-NEXT: <MCOperand Imm:0>
+
+    ld [-372], %pc
+! CHECK: encoding: [0x81,0x02,0xfe,0x8c]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:2>
+! CHECK-NEXT: <MCOperand Reg:7>
+! CHECK-NEXT: <MCOperand Imm:-372>
+! CHECK-NEXT: <MCOperand Imm:0>
+
+! RRM class
+    ld %r9[%r12*], %r20
+! CHECK: encoding: [0xaa,0x31,0x48,0x02]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RR{{$}}
+! CHECK-NEXT: <MCOperand Reg:27>
+! CHECK-NEXT: <MCOperand Reg:19>
+! CHECK-NEXT: <MCOperand Reg:16>
+! CHECK-NEXT: <MCOperand Imm:128>
+
+    ld %r9[%r12], %r20
+! CHECK: encoding: [0xaa,0x32,0x48,0x02]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RR{{$}}
+! CHECK-NEXT: <MCOperand Reg:27>
+! CHECK-NEXT: <MCOperand Reg:19>
+! CHECK-NEXT: <MCOperand Reg:16>
+! CHECK-NEXT: <MCOperand Imm:0>
+
+    ld [%r12 sub %r9], %r20
+! CHECK: encoding: [0xaa,0x32,0x4a,0x02]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RR{{$}}
+! CHECK-NEXT: <MCOperand Reg:27>
+! CHECK-NEXT: <MCOperand Reg:19>
+! CHECK-NEXT: <MCOperand Reg:16>
+! CHECK-NEXT: <MCOperand Imm:2>
+
+    ld %r9[*%r12], %r20
+! CHECK: encoding: [0xaa,0x33,0x48,0x02]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDW_RR{{$}}
+! CHECK-NEXT: <MCOperand Reg:27>
+! CHECK-NEXT: <MCOperand Reg:19>
+! CHECK-NEXT: <MCOperand Reg:16>
+! CHECK-NEXT: <MCOperand Imm:64>
+
+    st %r20, %r9[*%r12]
+! CHECK: encoding: [0xba,0x33,0x48,0x02]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} SW_RR{{$}}
+! CHECK-NEXT: <MCOperand Reg:27>
+! CHECK-NEXT: <MCOperand Reg:19>
+! CHECK-NEXT: <MCOperand Reg:16>
+! CHECK-NEXT: <MCOperand Imm:64>
+
+    ld.b [%r12 sub %r9], %r20
+! CHECK: encoding: [0xaa,0x32,0x4a,0x04]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDBs_RR{{$}}
+! CHECK-NEXT: <MCOperand Reg:27>
+! CHECK-NEXT: <MCOperand Reg:19>
+! CHECK-NEXT: <MCOperand Reg:16>
+! CHECK-NEXT: <MCOperand Imm:2>
+
+    uld.h [%r12 sub %r9], %r20
+! CHECK: encoding: [0xaa,0x32,0x4a,0x01]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDHz_RR{{$}}
+! CHECK-NEXT: <MCOperand Reg:27>
+! CHECK-NEXT: <MCOperand Reg:19>
+! CHECK-NEXT: <MCOperand Reg:16>
+! CHECK-NEXT: <MCOperand Imm:2>
+
+
+! SPLS class
+    st.b %r3, [%r6]
+! CHECK: encoding: [0xf1,0x9b,0x60,0x00]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} STB_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:10>
+! CHECK-NEXT: <MCOperand Reg:13>
+! CHECK-NEXT: <MCOperand Imm:0>
+! CHECK-NEXT: <MCOperand Imm:0>
+
+    st.b %r3, 1[%r6*]
+! CHECK: encoding: [0xf1,0x9b,0x64,0x01]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} STB_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:10>
+! CHECK-NEXT: <MCOperand Reg:13>
+! CHECK-NEXT: <MCOperand Imm:1>
+! CHECK-NEXT: <MCOperand Imm:128>
+
+    st.b %r3, 1[%r6]
+! CHECK: encoding: [0xf1,0x9b,0x68,0x01]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} STB_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:10>
+! CHECK-NEXT: <MCOperand Reg:13>
+! CHECK-NEXT: <MCOperand Imm:1>
+! CHECK-NEXT: <MCOperand Imm:0>
+
+    st.b %r3, 1[*%r6]
+! CHECK: encoding: [0xf1,0x9b,0x6c,0x01]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} STB_RI{{$}}
+! CHECK-NEXT: <MCOperand Reg:10>
+! CHECK-NEXT: <MCOperand Reg:13>
+! CHECK-NEXT: <MCOperand Imm:1>
+! CHECK-NEXT: <MCOperand Imm:64>
+
+! SLS class
+    st %r30, [0x1234]
+! CHECK: encoding: [0xff,0x01,0x12,0x34]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} STADDR{{$}}
+! CHECK-NEXT: <MCOperand Reg:37>
+! CHECK-NEXT: <MCOperand Imm:4660>
+
+    ld [0xfe8c], %pc
+! CHECK: encoding: [0xf1,0x00,0xfe,0x8c]
+! CHECK-NEXT: <MCInst #{{[0-9]+}} LDADDR{{$}}
+! CHECK-NEXT: <MCOperand Reg:2>
+! CHECK-NEXT: <MCOperand Imm:65164>
+
+! SLI class
+    mov hi(x), %r4
+! CHECK: encoding: [0x02,0x01,A,A]
+! CHECK-NEXT: fixup A - offset: 0, value: hi(x), kind: FIXUP_LANAI_HI16{{$}}
+! CHECK-NEXT: <MCInst #{{[0-9]+}} ADD_I_HI
+! CHECK-NEXT: <MCOperand Reg:11>
+! CHECK-NEXT: <MCOperand Reg:7>
+! CHECK-NEXT: <MCOperand Expr:(hi(x))>
+
+    mov hi(l+4), %r7
+! CHECK: encoding: [0x03,0x81,A,A]
+! CHECK-NEXT: fixup A - offset: 0, value: (hi(l))+4, kind: FIXUP_LANAI_HI16{{$}}
+! CHECK-NEXT: <MCInst #{{[0-9]+}} ADD_I_HI
+! CHECK-NEXT: <MCOperand Reg:14>
+! CHECK-NEXT: <MCOperand Reg:7>
+! CHECK-NEXT: <MCOperand Expr:((hi(l))+4)>
+
diff --git a/test/MC/Lanai/v11.s b/test/MC/Lanai/v11.s
index 8991dcb7b64..621c47de023 100644
--- a/test/MC/Lanai/v11.s
+++ b/test/MC/Lanai/v11.s
@@ -840,3 +840,37 @@ spl %r19
 ! CHECK: 0xea,0x4c,0x00,0x02
 bt 0x1234
 ! CHECK: 0xe0,0x00,0x12,0x34
+sel.t %r9, %r15, %r12
+! CHECK: 0xc6,0x24,0x7f,0x00
+sel.f %r9, %r15, %r12
+! CHECK: 0xc6,0x25,0x7f,0x00
+sel.ugt %r9, %r15, %r12
+! CHECK: 0xc6,0x24,0x7f,0x01
+sel.ule %r9, %r15, %r12
+! CHECK: 0xc6,0x25,0x7f,0x01
+sel.ult %r9, %r15, %r12
+! CHECK: 0xc6,0x24,0x7f,0x02
+sel.uge %r9, %r15, %r12
+! CHECK: 0xc6,0x25,0x7f,0x02
+sel.ne %r9, %r15, %r12
+! CHECK: 0xc6,0x24,0x7f,0x03
+sel.eq %r9, %r15, %r12
+! CHECK: 0xc6,0x25,0x7f,0x03
+sel.vc %r9, %r15, %r12
+! CHECK: 0xc6,0x24,0x7f,0x04
+sel.vs %r9, %r15, %r12
+! CHECK: 0xc6,0x25,0x7f,0x04
+sel.pl %r9, %r15, %r12
+! CHECK: 0xc6,0x24,0x7f,0x05
+sel.mi %r9, %r15, %r12
+! CHECK: 0xc6,0x25,0x7f,0x05
+sel.ge %r9, %r15, %r12
+! CHECK: 0xc6,0x24,0x7f,0x06
+sel.lt %r9, %r15, %r12
+! CHECK: 0xc6,0x25,0x7f,0x06
+sel.gt %r9, %r15, %r12
+! CHECK: 0xc6,0x24,0x7f,0x07
+sel.le %r9, %r15, %r12
+! CHECK: 0xc6,0x25,0x7f,0x07
+trailz %r15, %r12
+! CHECK: 0xd6,0x3c,0x00,0x03