diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2019-01-17 14:49:02 -0500 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2019-01-22 12:14:26 -0500 |
| commit | c252273f98fbad8fac123ec69f331bf6749cf178 (patch) | |
| tree | bda09522921beb1f31d64a13ed99875df245fcb9 | |
| parent | a545415eb9765f46e6f358657b15171d07f89842 (diff) | |
radeonsi: don't use WRITE_DATA.DST_SEL == MEM_GRBM on >= CIK
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 6ed45bb767e..b6953b8bd27 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -528,7 +528,8 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, /* Initialize the memory. */ struct radeon_cmdbuf *cs = sctx->gfx_cs; radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); - radeon_emit(cs, S_370_DST_SEL(V_370_MEM_GRBM) | + radeon_emit(cs, S_370_DST_SEL(sctx->chip_class >= CIK ? V_370_MEM + : V_370_MEM_GRBM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(V_370_ME)); radeon_emit(cs, sctx->wait_mem_scratch->gpu_address); diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index ea8c5d054b5..9a80bd81327 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1596,7 +1596,8 @@ void si_trace_emit(struct si_context *sctx) uint32_t trace_id = ++sctx->current_saved_cs->trace_id; radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); - radeon_emit(cs, S_370_DST_SEL(V_370_MEM_GRBM) | + radeon_emit(cs, S_370_DST_SEL(sctx->chip_class >= CIK ? V_370_MEM + : V_370_MEM_GRBM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(V_370_ME)); radeon_emit(cs, va); |