Add file missed in last commit: Bug #748:

- Add Render acceleration for Radeon 100 and 200-series cards, enabled by
    default. Notable performance gains include 27fps in cairogears instead
    of 6fps (compared to 50 with glitz), and my disks are now the
    bottleneck in an ls -lR in gnome-terminal. Only supported in DRI mode
    because the MMIO submission hangs the card so far, but the code is left
    in because it may be supportable soon.
- Add xorg.conf options to disable Render acceleration and to force the
    subpixel order in the server (Hui Yu).
Many thanks to Hui Yu at ATI for the code this was based off of, Michel
    Daenzer for bugfixes and suggestions, and LinuxFund for sponsoring the
    work.

1 files changed, 112 insertions, 332 deletions

diff --git a/src/radeon_render.c b/src/radeon_render.c
index f4cad67..fe19299 100644
--- a/src/radeon_render.c
+++ b/src/radeon_render.c
@@ -62,7 +62,7 @@ static const struct blendinfo RadeonBlendOp[] = {
     {0, 0, RADEON_SRC_BLEND_GL_ONE |
 	   RADEON_DST_BLEND_GL_ONE},
     /* Saturate */
-    {1, 1, RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE |
+    {0, 1, RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE |
 	   RADEON_DST_BLEND_GL_ONE},
     {0, 0, 0},
     {0, 0, 0},
@@ -121,89 +121,39 @@ static CARD32 RADEONTextureFormats[] = {
     PICT_a8,
     PICT_x8r8g8b8,
     PICT_r5g6b5,
-    PICT_a1r5g5b5,
-    PICT_x1r5g5b5,
-    0
-};
-
-static CARD32 RADEONDstFormats[] = {
-    PICT_a8r8g8b8,
-    PICT_x8r8g8b8,
-    PICT_r5g6b5,
-    PICT_a1r5g5b5,
     PICT_x1r5g5b5,
-    0
 };
 
-static CARD32
-RadeonGetTextureFormat(CARD32 format)
+static void RadeonGetTextureFormat(CARD32 format, CARD32 *txformat, int *bytepp)
 {
     switch (format) {
     case PICT_a8r8g8b8:
-	return RADEON_TXFORMAT_ARGB8888 | RADEON_TXFORMAT_ALPHA_IN_MAP;
+	*txformat = RADEON_TXFORMAT_ARGB8888 | RADEON_TXFORMAT_ALPHA_IN_MAP;
+	*bytepp = 4;
+	break;
     case PICT_a8:
-	return RADEON_TXFORMAT_I8 | RADEON_TXFORMAT_ALPHA_IN_MAP;
-    case PICT_x8r8g8b8:
-	return RADEON_TXFORMAT_ARGB8888;
-    case PICT_r5g6b5:
-	return RADEON_TXFORMAT_RGB565;
-    case PICT_a1r5g5b5:
-	return RADEON_TXFORMAT_ARGB1555 | RADEON_TXFORMAT_ALPHA_IN_MAP;
-    case PICT_x1r5g5b5:
-	return RADEON_TXFORMAT_ARGB1555;
-    default:
-	return 0;
-    }
-}
-
-static CARD32
-RadeonGetColorFormat(CARD32 format)
-{
-    switch (format) {
-    case PICT_a8r8g8b8:
+	*txformat = RADEON_TXFORMAT_I8 | RADEON_TXFORMAT_ALPHA_IN_MAP;
+	*bytepp = 1;
+	break;
     case PICT_x8r8g8b8:
-	return RADEON_COLOR_FORMAT_ARGB8888;
+	*txformat = RADEON_TXFORMAT_ARGB8888;
+	*bytepp = 4;
+	break;
     case PICT_r5g6b5:
-	return RADEON_COLOR_FORMAT_RGB565;
+	*txformat = RADEON_TXFORMAT_RGB565;
+	*bytepp = 2;
+	break;
     case PICT_a1r5g5b5:
+	*txformat = RADEON_TXFORMAT_ARGB1555 | RADEON_TXFORMAT_ALPHA_IN_MAP;
+	*bytepp = 2;
+	break;
     case PICT_x1r5g5b5:
-	return RADEON_COLOR_FORMAT_ARGB1555;
-    default:
-	return 0;
+	*txformat = RADEON_TXFORMAT_ARGB1555;
+	*bytepp = 2;
+	break;
     }
 }
 
-/* Returns a RADEON_RB3D_BLENDCNTL value, or 0 if the operation is not
- * supported
- */
-static CARD32
-RadeonGetBlendCntl(CARD8 op, CARD32 dstFormat)
-{
-    CARD32 blend_cntl;
-
-    if (op >= RadeonOpMax || RadeonBlendOp[op].blend_cntl == 0)
-	return 0;
-
-    blend_cntl = RadeonBlendOp[op].blend_cntl;
-	
-    if (RadeonBlendOp[op].dst_alpha && !PICT_FORMAT_A(dstFormat)) {
-	CARD32 srcblend = blend_cntl & RADEON_SRC_BLEND_MASK;
-
-	/* If there's no destination alpha channel, we need to wire the blending
-	 * to treat the alpha channel as always 1.
-	 */
-	if (srcblend == RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA ||
-	    srcblend == RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE)
-	    blend_cntl = (blend_cntl & ~RADEON_SRC_BLEND_MASK) |
-			 RADEON_SRC_BLEND_GL_ZERO;
-	else if (srcblend == RADEON_SRC_BLEND_GL_DST_ALPHA)
-	    blend_cntl = (blend_cntl & ~RADEON_SRC_BLEND_MASK) |
-			 RADEON_SRC_BLEND_GL_ONE;
-    }
-
-    return blend_cntl;
-}
-
 static __inline__ CARD32 F_TO_DW(float val)
 {
     union {
@@ -225,22 +175,16 @@ ATILog2(int val)
 	return bits - 1;
 }
 
-static void RadeonInit3DEngine(ScrnInfoPtr pScrn)
+void RADEONInit3DEngineForRender(ScrnInfoPtr pScrn)
 {
     RADEONInfoPtr info = RADEONPTR (pScrn);
 
 #ifdef XF86DRI
-    if (info->directRenderingEnabled) {
-	RADEONSAREAPrivPtr pSAREAPriv;
-
-	pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
-	pSAREAPriv->ctxOwner = DRIGetContext(pScrn->pScreen);
+    if (info->directRenderingEnabled)
 	RadeonInit3DEngineCP(pScrn);
-    } else
+    else
 #endif
 	RadeonInit3DEngineMMIO(pScrn);
-
-    info->RenderInited3D = TRUE;
 }
 
 static void
@@ -293,46 +237,7 @@ AllocateLinear (
    return (info->RenderTex != NULL);
 }
 
-#if X_BYTE_ORDER == X_BIG_ENDIAN
-static Bool RADEONSetupRenderByteswap(ScrnInfoPtr pScrn, int tex_bytepp)
-{
-    RADEONInfoPtr info = RADEONPTR(pScrn);
-    unsigned char *RADEONMMIO = info->MMIO;
-
-    /* Set up byte swapping for the framebuffer aperture as needed */
-    switch (tex_bytepp) {
-    case 1:
-	OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl &
-				    ~(RADEON_NONSURF_AP0_SWP_32BPP
-				    | RADEON_NONSURF_AP0_SWP_16BPP));
-	break;
-    case 2:
-	OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg.surface_cntl &
-				     ~RADEON_NONSURF_AP0_SWP_32BPP)
-				   | RADEON_NONSURF_AP0_SWP_16BPP);
-	break;
-    case 4:
-	OUTREG(RADEON_SURFACE_CNTL, (info->ModeReg.surface_cntl &
-				     ~RADEON_NONSURF_AP0_SWP_16BPP)
-				   | RADEON_NONSURF_AP0_SWP_32BPP);
-	break;
-    default:
-	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "%s: Don't know what to do for "
-		   "tex_bytepp == %d!\n", __func__, tex_bytepp);
-	return FALSE;
-    }
-    return TRUE;
-}
-
-static void RADEONRestoreByteswap(RADEONInfoPtr info)
-{
-    unsigned char *RADEONMMIO = info->MMIO;
-
-    OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
-}
-#endif	/* X_BYTE_ORDER == X_BIG_ENDIAN */
-
-#endif	/* RENDER_GENERIC_HELPER */
+#endif
 
 #if defined(ACCEL_MMIO) && defined(ACCEL_CP)
 #error Cannot define both MMIO and CP acceleration!
@@ -366,13 +271,8 @@ static void FUNC_NAME(RadeonInit3DEngine)(ScrnInfoPtr pScrn)
 	       (info->ChipFamily == CHIP_FAMILY_RV280) || 
 	       (info->ChipFamily == CHIP_FAMILY_RS300) || 
 	       (info->ChipFamily == CHIP_FAMILY_R200)) {
-
 	BEGIN_ACCEL(7);
-        if (info->ChipFamily == CHIP_FAMILY_RS300) {
-            OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
-        } else {
-            OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0);
-        }
+	OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0);
 	OUT_ACCEL_REG(R200_PP_CNTL_X, 0);
 	OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0);
 	OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0);
@@ -384,11 +284,7 @@ static void FUNC_NAME(RadeonInit3DEngine)(ScrnInfoPtr pScrn)
 	FINISH_ACCEL();
     } else {
 	BEGIN_ACCEL(2);
-        if ((info->ChipFamily == CHIP_FAMILY_RADEON) ||
-            (info->ChipFamily == CHIP_FAMILY_RV200))
-            OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0);
-        else
-            OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
+	OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
 	OUT_ACCEL_REG(RADEON_SE_COORD_FMT,
 	    RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 	    RADEON_VTX_ST0_NONPARAMETRIC |
@@ -409,45 +305,26 @@ static void FUNC_NAME(RadeonInit3DEngine)(ScrnInfoPtr pScrn)
     FINISH_ACCEL();
 }
 
-static Bool FUNC_NAME(R100SetupTexture)(
-	ScrnInfoPtr pScrn,
-	CARD32 format,
+static Bool FUNC_NAME(R100SetupTexture)(ScrnInfoPtr pScrn,
+	int format,
 	CARD8 *src,
 	int src_pitch,
-	unsigned int width,
-	unsigned int height,
+	int width,
+	int height,
 	int flags)
 {
     RADEONInfoPtr info = RADEONPTR(pScrn);
     CARD8 *dst;
     CARD32 tex_size = 0, txformat;
     int dst_pitch, offset, size, i, tex_bytepp;
-#ifdef ACCEL_CP
-    CARD32 buf_pitch;
-    unsigned int hpass;
-    CARD8 *tmp_dst;
-#endif
     ACCEL_PREAMBLE();
 
     if ((width > 2048) || (height > 2048))
 	return FALSE;
 
-    txformat = RadeonGetTextureFormat(format);
-    tex_bytepp = PICT_FORMAT_BPP(format) >> 3;
+    RadeonGetTextureFormat(format, &txformat, &tex_bytepp);
 
-#ifndef ACCEL_CP
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
-    if (!RADEONSetupRenderByteswap(pScrn, tex_bytepp)) {
-	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "%s: RADEONSetupRenderByteswap() "
-		   "failed!\n", __func__);
-	return FALSE;
-    }
-#endif
-
-#endif
-
-    dst_pitch = (width * tex_bytepp + 63) & ~63;
+    dst_pitch = (width * tex_bytepp + 31) & ~31;
     size = dst_pitch * height;
 
     if (!AllocateLinear(pScrn, size))
@@ -462,43 +339,18 @@ static Bool FUNC_NAME(R100SetupTexture)(
     }
 
     offset = info->RenderTex->offset * pScrn->bitsPerPixel / 8;
-    dst = (CARD8*)(info->FB + offset);
-
-    /* Upload texture to card. */
-
-#ifdef ACCEL_CP
-
-    while ( height )
-    {
-    	tmp_dst = RADEONHostDataBlit( pScrn, tex_bytepp, width,
-							dst_pitch, &buf_pitch,
-							&dst, &height, &hpass );
-	RADEONHostDataBlitCopyPass( tmp_dst, src, hpass, buf_pitch, src_pitch );
-	src += hpass * src_pitch;
-    }
-
-    RADEON_PURGE_CACHE();
-    RADEON_WAIT_UNTIL_IDLE();
-
-#else
 
+    /* Upload texture to card.  Should use ImageWrite to avoid syncing. */
     i = height;
-
+    dst = (CARD8*)(info->FB + offset);
     if (info->accel->NeedToSync)
 	info->accel->Sync(pScrn);
-
     while(i--) {
 	memcpy(dst, src, width * tex_bytepp);
 	src += src_pitch;
 	dst += dst_pitch;
     }
 
-#if X_BYTE_ORDER == X_BIG_ENDIAN
-    RADEONRestoreByteswap(info);
-#endif
-
-#endif	/* ACCEL_CP */
-
     BEGIN_ACCEL(5);
     OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, txformat);
     OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0, tex_size);
@@ -522,8 +374,7 @@ FUNC_NAME(R100SetupForCPUToScreenAlphaTexture) (
 	CARD16		green,
 	CARD16		blue,
 	CARD16		alpha,
-	CARD32		maskFormat,
-	CARD32		dstFormat,
+	int		alphaFormat,
 	CARD8		*alphaPtr,
 	int		alphaPitch,
 	int		width,
@@ -532,27 +383,27 @@ FUNC_NAME(R100SetupForCPUToScreenAlphaTexture) (
 ) 
 {
     RADEONInfoPtr info = RADEONPTR(pScrn);
-    CARD32 colorformat, srccolor, blend_cntl;
+    CARD32 format, srccolor;
     ACCEL_PREAMBLE();
 
-    blend_cntl = RadeonGetBlendCntl(op, dstFormat);
-    if (blend_cntl == 0)
+    if (op >= RadeonOpMax || RadeonBlendOp[op].blend_cntl == 0)
 	return FALSE;
-
-    if (!info->RenderInited3D)
-	RadeonInit3DEngine(pScrn);
-
-    if (!FUNC_NAME(R100SetupTexture)(pScrn, maskFormat, alphaPtr, alphaPitch,
+    
+    if (!FUNC_NAME(R100SetupTexture)(pScrn, alphaFormat, alphaPtr, alphaPitch,
 				     width, height, flags))
 	return FALSE;
 
-    colorformat = RadeonGetColorFormat(dstFormat);
+    if (pScrn->bitsPerPixel == 32)
+	format = RADEON_COLOR_FORMAT_ARGB8888;
+    else
+	format = RADEON_COLOR_FORMAT_RGB565;
 
     srccolor = ((alpha & 0xff00) << 16) | ((red & 0xff00) << 8) | (blue >> 8) |
 	(green & 0xff00);
 
-    BEGIN_ACCEL(7);
-    OUT_ACCEL_REG(RADEON_RB3D_CNTL, colorformat | RADEON_ALPHA_BLEND_ENABLE);
+    BEGIN_ACCEL(8);
+    OUT_ACCEL_REG(RADEON_RB3D_CNTL, format | RADEON_ALPHA_BLEND_ENABLE);
+    OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth);
     OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
 				  RADEON_TEX_BLEND_0_ENABLE);
     OUT_ACCEL_REG(RADEON_PP_TFACTOR_0, srccolor);
@@ -562,7 +413,8 @@ FUNC_NAME(R100SetupForCPUToScreenAlphaTexture) (
 					RADEON_ALPHA_ARG_B_T0_ALPHA);
     OUT_ACCEL_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY |
 				     RADEON_SE_VTX_FMT_ST0);
-    OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blend_cntl);
+    OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL,
+	RadeonBlendOp[op].blend_cntl);
     FINISH_ACCEL();
 
     return TRUE;
@@ -573,8 +425,7 @@ static Bool
 FUNC_NAME(R100SetupForCPUToScreenTexture) (
 	ScrnInfoPtr	pScrn,
 	int		op,
-	CARD32		srcFormat,
-	CARD32		dstFormat,
+	int		texFormat,
 	CARD8		*texPtr,
 	int		texPitch,
 	int		width,
@@ -583,34 +434,35 @@ FUNC_NAME(R100SetupForCPUToScreenTexture) (
 )
 {
     RADEONInfoPtr info = RADEONPTR(pScrn);
-    CARD32 colorformat, blend_cntl;
+    CARD32 format;
     ACCEL_PREAMBLE();
 
-    blend_cntl = RadeonGetBlendCntl(op, dstFormat);
-    if (blend_cntl == 0)
+    if (op >= RadeonOpMax || RadeonBlendOp[op].blend_cntl == 0)
 	return FALSE;
     
-    if (!info->RenderInited3D)
-	RadeonInit3DEngine(pScrn);
-
-    if (!FUNC_NAME(R100SetupTexture)(pScrn, srcFormat, texPtr, texPitch, width,
+    if (!FUNC_NAME(R100SetupTexture)(pScrn, texFormat, texPtr, texPitch, width,
 				     height, flags))
 	return FALSE;
 
-    colorformat = RadeonGetColorFormat(dstFormat);
+    if (pScrn->bitsPerPixel == 32)
+	format = RADEON_COLOR_FORMAT_ARGB8888;
+    else
+	format = RADEON_COLOR_FORMAT_RGB565;
     
-    BEGIN_ACCEL(6);
-    OUT_ACCEL_REG(RADEON_RB3D_CNTL, colorformat | RADEON_ALPHA_BLEND_ENABLE);
+    BEGIN_ACCEL(7);
+    OUT_ACCEL_REG(RADEON_RB3D_CNTL, format | RADEON_ALPHA_BLEND_ENABLE);
+    OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth);
     OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
 				  RADEON_TEX_BLEND_0_ENABLE);
-    if (srcFormat != PICT_a8)
+    if (texFormat != PICT_a8)
 	OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_C_T0_COLOR);
     else
 	OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_C_ZERO);
     OUT_ACCEL_REG(RADEON_PP_TXABLEND_0, RADEON_ALPHA_ARG_C_T0_ALPHA);
     OUT_ACCEL_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY |
 				     RADEON_SE_VTX_FMT_ST0);
-    OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blend_cntl);
+    OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL,
+	RadeonBlendOp[op].blend_cntl);
     FINISH_ACCEL();
 
     return TRUE;
@@ -638,36 +490,24 @@ FUNC_NAME(R100SubsequentCPUToScreenTexture) (
     /* Note: we can't simply set up the 3D surface at the same location as the
      * front buffer, because the 2048x2048 limit on coordinates may be smaller
      * than the (MergedFB) screen.
-     * Can't use arbitrary offsets for color tiling
      */ 
-    if (info->tilingEnabled) {
-       /* can't play tricks with x coordinate, or could we - tiling is disabled anyway in that case */
-       fboffset = info->fbLocation + pScrn->fbOffset +
-          (pScrn->displayWidth * (dsty & ~15) * (pScrn->bitsPerPixel >> 3));
-       l = dstx;
-       t = (dsty % 16);
-    }
-    else {
-       byteshift = (pScrn->bitsPerPixel >> 4);
-       fboffset = (info->fbLocation + pScrn->fbOffset +
+    byteshift = (pScrn->bitsPerPixel >> 4);
+    fboffset = (info->fbLocation + pScrn->fbOffset +
 		((pScrn->displayWidth * dsty + dstx) << byteshift)) & ~15;
-       l = ((dstx << byteshift) % 16) >> byteshift;
-       t = 0.0;
-    }
-
+    l = ((dstx << byteshift) % 16) >> byteshift;
+    t = 0.0;
     r = width + l;
-    b = height + t;
+    b = height;
     fl = srcx;
     fr = srcx + width;
     ft = srcy;
     fb = srcy + height;
 
 #ifdef ACCEL_CP
-    BEGIN_RING(25);
+    BEGIN_RING(23);
 
-    OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth |
-	((info->tilingEnabled && (dsty <= pScrn->virtualY)) ? RADEON_COLOR_TILE_ENABLE : 0));
     OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset);
+
     OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD, 17));
     /* RADEON_SE_VTX_FMT */
     OUT_RING(RADEON_CP_VC_FRMT_XY |
@@ -703,10 +543,8 @@ FUNC_NAME(R100SubsequentCPUToScreenTexture) (
 
     ADVANCE_RING();
 #else
-    BEGIN_ACCEL(20);
+    BEGIN_ACCEL(19);
     
-    OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth |
-	((info->tilingEnabled && (dsty <= pScrn->virtualY)) ? RADEON_COLOR_TILE_ENABLE : 0));
     OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset);
 
     OUT_ACCEL_REG(RADEON_SE_VF_CNTL, RADEON_VF_PRIM_TYPE_TRIANGLE_FAN |
@@ -740,45 +578,26 @@ FUNC_NAME(R100SubsequentCPUToScreenTexture) (
 
 }
 
-static Bool FUNC_NAME(R200SetupTexture)(
-	ScrnInfoPtr pScrn,
-	CARD32 format,
+static Bool FUNC_NAME(R200SetupTexture)(ScrnInfoPtr pScrn,
+	int format,
 	CARD8 *src,
 	int src_pitch,
-	unsigned int width,
-	unsigned int height,
+	int width,
+	int height,
 	int flags)
 {
     RADEONInfoPtr info = RADEONPTR(pScrn);
     CARD8 *dst;
     CARD32 tex_size = 0, txformat;
     int dst_pitch, offset, size, i, tex_bytepp;
-#ifdef ACCEL_CP
-    CARD32 buf_pitch;
-    unsigned int hpass;
-    CARD8 *tmp_dst;
-#endif
     ACCEL_PREAMBLE();
 
     if ((width > 2048) || (height > 2048))
 	return FALSE;
 
-    txformat = RadeonGetTextureFormat(format);
-    tex_bytepp = PICT_FORMAT_BPP(format) >> 3;
+    RadeonGetTextureFormat(format, &txformat, &tex_bytepp);
 
-#ifndef ACCEL_CP
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
-    if (!RADEONSetupRenderByteswap(pScrn, tex_bytepp)) {
-	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "%s: RADEONSetupRenderByteswap() "
-		   "failed!\n", __func__);
-	return FALSE;
-    }
-#endif
-
-#endif
-
-    dst_pitch = (width * tex_bytepp + 63) & ~63;
+    dst_pitch = (width * tex_bytepp + 31) & ~31;
     size = dst_pitch * height;
 
     if (!AllocateLinear(pScrn, size))
@@ -793,42 +612,18 @@ static Bool FUNC_NAME(R200SetupTexture)(
     }
 
     offset = info->RenderTex->offset * pScrn->bitsPerPixel / 8;
-    dst = (CARD8*)(info->FB + offset);
-
-    /* Upload texture to card. */
-
-#ifdef ACCEL_CP
-
-    while ( height )
-    {
-        tmp_dst = RADEONHostDataBlit( pScrn, tex_bytepp, width,
-							dst_pitch, &buf_pitch,
-							&dst, &height, &hpass );
-	RADEONHostDataBlitCopyPass( tmp_dst, src, hpass, buf_pitch, src_pitch );
-	src += hpass * src_pitch;
-    }
-
-    RADEON_PURGE_CACHE();
-    RADEON_WAIT_UNTIL_IDLE();
-
-#else
 
+    /* Upload texture to card.  Should use ImageWrite to avoid syncing. */
     i = height;
+    dst = (CARD8*)(info->FB + offset);
     if (info->accel->NeedToSync)
 	info->accel->Sync(pScrn);
-
     while(i--) {
 	memcpy(dst, src, width * tex_bytepp);
 	src += src_pitch;
 	dst += dst_pitch;
     }
 
-#if X_BYTE_ORDER == X_BIG_ENDIAN
-    RADEONRestoreByteswap(info);
-#endif
-
-#endif	/* ACCEL_CP */
-
     BEGIN_ACCEL(6);
     OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat);
     OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0);
@@ -853,8 +648,7 @@ FUNC_NAME(R200SetupForCPUToScreenAlphaTexture) (
 	CARD16		green,
 	CARD16		blue,
 	CARD16		alpha,
-	CARD32		maskFormat,
-	CARD32		dstFormat,
+	int		alphaFormat,
 	CARD8		*alphaPtr,
 	int		alphaPitch,
 	int		width,
@@ -863,27 +657,27 @@ FUNC_NAME(R200SetupForCPUToScreenAlphaTexture) (
 ) 
 {
     RADEONInfoPtr  info = RADEONPTR(pScrn);
-    CARD32 colorformat, srccolor, blend_cntl;
+    CARD32 format, srccolor;
     ACCEL_PREAMBLE();
 
-    blend_cntl = RadeonGetBlendCntl(op, dstFormat);
-    if (blend_cntl == 0)
+    if (op >= RadeonOpMax || RadeonBlendOp[op].blend_cntl == 0)
 	return FALSE;
 
-    if (!info->RenderInited3D)
-	RadeonInit3DEngine(pScrn);
-
-    if (!FUNC_NAME(R200SetupTexture)(pScrn, maskFormat, alphaPtr, alphaPitch,
+    if (!FUNC_NAME(R200SetupTexture)(pScrn, alphaFormat, alphaPtr, alphaPitch,
 				     width, height, flags))
 	return FALSE;
 
-    colorformat = RadeonGetColorFormat(dstFormat);
+    if (pScrn->bitsPerPixel == 32)
+	format = RADEON_COLOR_FORMAT_ARGB8888;
+    else
+	format = RADEON_COLOR_FORMAT_RGB565;
 
     srccolor = ((alpha & 0xff00) << 16) | ((red & 0xff00) << 8) | (blue >> 8) |
 	(green & 0xff00);
 
-    BEGIN_ACCEL(10);
-    OUT_ACCEL_REG(RADEON_RB3D_CNTL, colorformat | RADEON_ALPHA_BLEND_ENABLE);
+    BEGIN_ACCEL(11);
+    OUT_ACCEL_REG(RADEON_RB3D_CNTL, format | RADEON_ALPHA_BLEND_ENABLE);
+    OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth);
     OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
 				  RADEON_TEX_BLEND_0_ENABLE);
     OUT_ACCEL_REG(R200_PP_TFACTOR_0, srccolor);
@@ -895,7 +689,8 @@ FUNC_NAME(R200SetupForCPUToScreenAlphaTexture) (
     OUT_ACCEL_REG(R200_PP_TXABLEND2_0, R200_TXA_OUTPUT_REG_R0);
     OUT_ACCEL_REG(R200_SE_VTX_FMT_0, 0);
     OUT_ACCEL_REG(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
-    OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blend_cntl);
+    OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL,
+	RadeonBlendOp[op].blend_cntl);
     FINISH_ACCEL();
 
     return TRUE;
@@ -905,8 +700,7 @@ static Bool
 FUNC_NAME(R200SetupForCPUToScreenTexture) (
 	ScrnInfoPtr	pScrn,
 	int		op,
-	CARD32		srcFormat,
-	CARD32		dstFormat,
+	int		texFormat,
 	CARD8		*texPtr,
 	int		texPitch,
 	int		width,
@@ -915,27 +709,27 @@ FUNC_NAME(R200SetupForCPUToScreenTexture) (
 )
 {
     RADEONInfoPtr  info       = RADEONPTR(pScrn);
-    CARD32 colorformat, blend_cntl;
+    CARD32 format;
     ACCEL_PREAMBLE();
 
-    blend_cntl = RadeonGetBlendCntl(op, dstFormat);
-    if (blend_cntl == 0)
+    if (op >= RadeonOpMax || RadeonBlendOp[op].blend_cntl == 0)
 	return FALSE;
 
-    if (!info->RenderInited3D)
-	RadeonInit3DEngine(pScrn);
-
-    if (!FUNC_NAME(R200SetupTexture)(pScrn, srcFormat, texPtr, texPitch, width,
+    if (!FUNC_NAME(R200SetupTexture)(pScrn, texFormat, texPtr, texPitch, width,
 				     height, flags))
 	return FALSE;
 
-    colorformat = RadeonGetColorFormat(dstFormat);
+    if (pScrn->bitsPerPixel == 32)
+	format = RADEON_COLOR_FORMAT_ARGB8888;
+    else
+	format = RADEON_COLOR_FORMAT_RGB565;
 
-    BEGIN_ACCEL(9);
-    OUT_ACCEL_REG(RADEON_RB3D_CNTL, colorformat | RADEON_ALPHA_BLEND_ENABLE);
+    BEGIN_ACCEL(10);
+    OUT_ACCEL_REG(RADEON_RB3D_CNTL, format | RADEON_ALPHA_BLEND_ENABLE);
+    OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth);
     OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
 				  RADEON_TEX_BLEND_0_ENABLE);
-    if (srcFormat != PICT_a8)
+    if (texFormat != PICT_a8)
 	OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_C_R0_COLOR);
     else
 	OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_C_ZERO);
@@ -944,7 +738,8 @@ FUNC_NAME(R200SetupForCPUToScreenTexture) (
     OUT_ACCEL_REG(R200_PP_TXABLEND2_0, R200_TXA_OUTPUT_REG_R0);
     OUT_ACCEL_REG(R200_SE_VTX_FMT_0, 0);
     OUT_ACCEL_REG(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
-    OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blend_cntl);
+    OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL,
+	RadeonBlendOp[op].blend_cntl);
     FINISH_ACCEL();
 
     return TRUE;
@@ -970,25 +765,14 @@ FUNC_NAME(R200SubsequentCPUToScreenTexture) (
     /* Note: we can't simply set up the 3D surface at the same location as the
      * front buffer, because the 2048x2048 limit on coordinates may be smaller
      * than the (MergedFB) screen.
-     * Can't use arbitrary offsets for color tiling
      */ 
-    if (info->tilingEnabled) {
-       /* can't play tricks with x coordinate, or could we - tiling is disabled anyway in that case */
-       fboffset = info->fbLocation + pScrn->fbOffset +
-          (pScrn->displayWidth * (dsty & ~15) * (pScrn->bitsPerPixel >> 3));
-       l = dstx;
-       t = (dsty % 16);
-    }
-    else {
-       byteshift = (pScrn->bitsPerPixel >> 4);
-       fboffset = (info->fbLocation + pScrn->fbOffset +
-		((pScrn->displayWidth * dsty + dstx) << byteshift)) & ~15;
-       l = ((dstx << byteshift) % 16) >> byteshift;
-       t = 0.0;
-    }
-    
+    byteshift = (pScrn->bitsPerPixel >> 4);
+    fboffset = (info->fbLocation + pScrn->fbOffset + ((pScrn->displayWidth *
+	dsty + dstx) << byteshift)) & ~15;
+    l = ((dstx << byteshift) % 16) >> byteshift;
+    t = 0.0;
     r = width + l;
-    b = height + t;
+    b = height;
     fl = srcx;
     fr = srcx + width;
     ft = srcy;
@@ -997,8 +781,6 @@ FUNC_NAME(R200SubsequentCPUToScreenTexture) (
 #ifdef ACCEL_CP
     BEGIN_RING(24);
 
-    OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth |
-	((info->tilingEnabled && (dsty <= pScrn->virtualY)) ? RADEON_COLOR_TILE_ENABLE : 0));
     OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset);
 
     OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, 16));
@@ -1031,13 +813,11 @@ FUNC_NAME(R200SubsequentCPUToScreenTexture) (
 
     ADVANCE_RING();
 #else
-    BEGIN_ACCEL(20);
+    BEGIN_ACCEL(19);
     
     /* Note: we can't simply setup 3D surface at the same location as the front buffer,
        some apps may draw offscreen pictures out of the limitation of radeon 3D surface.
     */ 
-    OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth |
-	((info->tilingEnabled && (dsty <= pScrn->virtualY)) ? RADEON_COLOR_TILE_ENABLE : 0));
     OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, fboffset);
 
     OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST |