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2013-11-17Add DRI3 and miSyncShm supportdri3Keith Packard7-6/+321
Signed-off-by: Keith Packard <keithp@keithp.com>
2013-11-13radeon/kms: add Hawaii pci idsAlex Deucher6-0/+72
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-13radeon: add support for HawaiiAlex Deucher3-1/+6
Disabled by default until the acceleration code stablizes. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-04radeon: enable tiling on SI by default (v2)Alex Deucher2-6/+6
Now that mesa 9.2 is out with support for tiling on SI asics, we can enable it here. Tiling improves memory bandwidth utilization. V2: update man page Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-01radeon: disable 2D tiling on buffers < 128 pixelsVadim Girlin1-1/+1
Seems to run into alignment problems with certain card configurations. bug: https://bugs.freedesktop.org/show_bug.cgi?id=70675 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-10-31radeon/glamor: with new pixmap for dri2 drawable no need to create new textureJerome Glisse2-12/+7
When creating a new pixmap/bo for dri2 drawable there is no need to create a new texture, instead the texture associated with the new pixmap should be use otherwise there is a missmatch between the bo backing the texture for the drawable and the bo used by dri2 client. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-10-01EXA/evergreen: Paranoia around linear tiling. (v2)Christopher James Halse Rogers3-10/+22
The last two bytes of tiling_mode contain the actual tiling mode; the rest are extra tiling configuration bits. These configuration bits are not necessarily zero for a linear buffer, so mask them out before checking for linearity v2: Also fix up evergreen_textured_videofuncs.c agd5f: remove trailing whitespace Signed-off-by: Christopher James Halse Rogers <raof@ubuntu.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-10-01radeon: fix the non-glamor build harder...Alex Deucher1-1/+1
I need to stop pushing patches first thing in the morning. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-10-01drm/radeon: fix non-glamor buildAlex Deucher1-1/+1
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-30radeon: use glamor Xv support if present.Dave Airlie4-2/+18
This creates adaptors using glamor if possible. Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-30Revert "radeon: add glamor Xv support (v2)"Alex Deucher2-17/+4
This causes problems if glamor doesn't have Xv support enabled. I just noticed that Dave has a better version, so use that instead. This reverts commit 4fc1fa920584ace2c84d75af82d06962d0c84ec8.
2013-09-27radeon: add glamor Xv support (v2)Alex Deucher2-4/+17
v2: guard new glamor Xv bits with USE_GLAMOR Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-09-27radeon: fix limit handling for cards with >4G of ramAlex Deucher3-7/+11
We can overflow the 32-bit limit. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-09-18DRI2: Install client callback only onceMichel Dänzer2-7/+7
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60182 Acked-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-16glamor: require 0.5.1 or newerAlex Deucher1-1/+1
0.5.1 fixes a number of issues. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-16radeon: enable glamor by default (v4)Alex Deucher1-3/+3
It's required for newer asics, so enable it by default. v2: update the autoconf help. Require --disable-glamor to build without glamor support. v3: default to yes rather than auto v4: fix help text Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-09-06radeon/kms: add berlin pci idsAlex Deucher6-0/+126
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-22Fix shadowfb on big-endian machinesMark Kettenis2-0/+6
For shadowfb, the framebuffer needs to have the RADEON_TILING_SURFACE flag set, otherwise the appropriate byte swapping won't happen. See https://bugs.freedesktop.org/show_bug.cgi?id=66663 Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-22radeon: disallow glamor on pre-R600 asicsAlex Deucher1-0/+6
I'm not sure they can handle the shaders properly, especially only older parts like r300. This will avoid display corruption problems reported by people using glamor on older asics by falling back to EXA if they try and enable glamor. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-08-07bump version post releaseMaarten Lankhorst1-1/+1
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
2013-08-07radeon: bump version for releaseMaarten Lankhorst1-1/+1
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
2013-08-07add bicubic_table.py to EXTRA_DISTMaarten Lankhorst1-0/+1
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
2013-08-07kill unused radeon_driver.cMaarten Lankhorst2-103/+1
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
2013-08-05drmmode: add support for multi-screen reverse optimusAlex Deucher2-9/+44
Initial reverse optimus didn't consider multiple screens, so this overhauls the code to use the new X server interface, and allows for multiple outputs on the dGPU to be used with the iGPU doing the rendering. Ported from Dave's nouveau patch. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-05radeon: add support for reverse prime (v2)Dave Airlie2-2/+42
This adds support for reverse prime configurations v2: fix compilation with older xservers Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2013-08-05radeon: fix naming clashes with multiple GPUs (v3)Alex Deucher1-24/+39
The compat naming code for UMS causes problems with multiple GPU as you may end up with the same output name on multiple GPUs. Adjust the naming on secondary GPUs to avoid conflicts. v2: integrate Dave's fixes for nouveau v3: keep compat with existing naming on primary GPU Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-31EXA/evergreen/ni: replace magic numberGrigori Goronzy1-1/+1
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2013-07-30EXA/6xx/7xx: optimize non-overlapping CopyRaul Fernandes1-1/+6
In case dst and src rectangles of a Copy operation in the same surface don't overlap, it is safe to skip the scratch surface. This is a common case. Based on evergreen/ni patch from Grigori Goronzy. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-22EXA/evergreen/ni: accelerate PictOpOver with component alphaGrigori Goronzy3-2/+34
Subpixel text rendering is typically done with a solid src and a pixmap mask. Traditionally, this cannot be accelerated in a single pass and requires two passes [1]. However, we can cheat a little with a constant blend color. We can use: const.A = src.A / src.A const.R = src.R / src.A const.G = src.G / src.A const.B = src.B / src.A dst.A = const.A * (src.A * mask.A) + (1 - (src.A * mask.A)) * dst.A dst.R = const.R * (src.A * mask.R) + (1 - (src.A * mask.R)) * dst.R dst.G = const.G * (src.A * mask.G) + (1 - (src.A * mask.G)) * dst.G dst.B = const.B * (src.A * mask.B) + (1 - (src.A * mask.B)) * dst.B This only needs a single source value. src.A is cancelled down in the right places. [1] http://anholt.livejournal.com/32058.html
2013-07-22EXA/evergreen/ni: fast solid pixmap supportGrigori Goronzy3-482/+962
Solid pixmaps are currently implemented with scratch pixmaps, which is slow. This replaces the hack with a proper implementation. The Composite shader can now either sample a src/mask or use a constant value.
2013-07-22EXA/evergreen/ni: optimize non-overlapping CopyGrigori Goronzy1-1/+6
In case dst and src rectangles of a Copy operation in the same surface don't overlap, it is safe to skip the scratch surface. This is a common case.
2013-07-22Fix RADEON_FALLBACK loggingGrigori Goronzy3-10/+10
2013-07-10Always go through DFS/UTS when byte swapping is needed.Mark Kettenis1-1/+1
Before commit ef9bfb262db7004bef3704e5d914687e50d3fca4 and e5bd99faa3b6629a55168386d5dfa936ee4e97ae, byte swapping for the front buffer used to be done in hardware. Now that this no longer happens we need to let DFS/UTS ihandle the byte swapping. See https://bugs.freedesktop.org/show_bug.cgi?id=66663 . Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2013-07-07radeon: bump libdrm requirement to 2.4.46 for CIK supportAlex Deucher1-1/+1
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28radeon/kms: add kabini pci idsAlex Deucher6-0/+96
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28radeon/kms: add bonaire pci idsAlex Deucher6-0/+48
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28radeon: update cursor handling for CIKAlex Deucher3-8/+37
CIK asics have 128x128 hw cursors Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28radeon: add family ids for CIKAlex Deucher2-0/+12
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-17radeon: fix a memory leak in get_modes() callback.Leo Liu1-1/+2
leak happens when looping xrandr prop. Signed-off-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2013-06-17man: fix up previous commitAlex Deucher1-3/+3
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2013-06-07Fix some incomplete list entries.Eric S. Raymond1-0/+6
This necessarily involved adding some content, which I was able to Google for. Please review, correct, and make more specific. Bodiless .TP entries screw up doclifter's page parsing. Please don't do that anymore.
2013-06-06autogen.sh: Restore passing --enable-maintainer-mode to configureMichel Dänzer1-1/+1
Looks like this was accidentally dropped when the GNOME Build API was implemented.
2013-06-03radeon: use direct mapping for fast fb access.Samuel Li5-5/+42
Signed-off-by: Samuel Li <samuel.li@amd.com>
2013-05-29DRI2: add interpolated blanks to frame number in event handlersIlija Hadzic1-0/+8
The 'frame' argument passed to event handlers is the plain CRTC vblank counter that stops progressing when the associated display is in DPMS-off mode. If we have a DPMS-off period the frame counter and MSC will diverge, which can cause some higher-level functions to return incorrect values. This patch fixes the problem by adding interpolated vblanks to the frame counter before using it in handler functions. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-29DRI2: support scheduling emulated events with zero delayIlija Hadzic1-8/+17
Now that we fully emulating a running CRTC through DPMS-off state it is possible to come up with a zero delay when scheduling a swap or MSC-wait (e.g., if a call into respective wait function was entered very late). This patch wraps the TimerSet function into our own radeon_dri2_schedule_event such that the latter calls the event right away if zero delay is specified. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-29DRI2: make wait_msc and get_msc work on disabled CRTCsIlija Hadzic1-14/+54
Now that the running CRTC is emulated through DPMS-off states, wait_msc and get_msc must also work on disabled CRTCs. When CRTC is disabled, we must extrapolate the MSC count from present time and last MSC when CRTC was running and also use timers facility in wait_msc. v2: CRTC-private now stores frame rate instead of nominal vblank period. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-29DRI2: move rename and rework radeon_dri2_deferred_swapIlija Hadzic1-12/+65
radeon_dri2_deferred_swap will be used to generate real events (not just fallbacks) so now it needs to generate real timestamp and frame counter. Also this function will be used both by schedule_swap and wait_msc, so give it a more generic name: radeon_dri2_deferred_event v2: - Extrapolate the frame number from the time of actual execution of the function instead of using the MSC calculated (extrapolated) at event scheduling time. - CRTC-private now stores frame rate instead of nominal vblank period. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-29DRI2: track CRTC in event recordIlija Hadzic1-0/+4
Tracking the CRTC associated with an event will save us some lookups later in event handlers. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-29DRI2: hook up vblank extrapolation to schedule_swapIlija Hadzic1-6/+8
This patch hooks up swap-scheduling function with vblank-extrapolation function. Rather than waiting for fixed time, we calculate exactly how much we should wait and what we should update target_msc to using radeon_dri2_extrapolate_msc_delay helper function and schedule the swap completion using DIX's timer facility. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-29DRI2: add vblank extrapolation functionIlija Hadzic1-0/+76
Implement a helper function that will be called when emulating the running CRTC. The function should be called only when CRTC is in DPMS-off state. It will look at the vblank count and the time that was recorded last time the CRTC was running and calculate how long one must wait (from present time) until the target_msc is reached if the CRTC were running. v2: - CRTC-private now stores frame rate instead of nominal vblank period. - DIX's timer facility can sometimes wake up the scheduled functions more than a millisecond earlier. To avoid generating an old MSC, we have to add more margin when converting the delay in microseconds to milliseconds. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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