diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2013-09-26 11:00:49 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-09-27 17:29:50 -0400 |
| commit | 41dfe327ac8740ac2cd84def96b5947224e422e7 (patch) | |
| tree | e9abb83f2897922184362d2aa726c1723dac3edd /src | |
| parent | c45e728107269c6f51599dad4f6a02ccfef703f1 (diff) | |
radeon: fix limit handling for cards with >4G of ram
We can overflow the 32-bit limit.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/drmmode_display.c | 2 | ||||
| -rw-r--r-- | src/radeon.h | 2 | ||||
| -rw-r--r-- | src/radeon_kms.c | 14 |
3 files changed, 11 insertions, 7 deletions
diff --git a/src/drmmode_display.c b/src/drmmode_display.c index 921b7ba9..76b79d8c 100644 --- a/src/drmmode_display.c +++ b/src/drmmode_display.c @@ -1478,7 +1478,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height) ScreenPtr screen = xf86ScrnToScreen(scrn); uint32_t old_fb_id; int i, pitch, old_width, old_height, old_pitch; - int screen_size; + uint32_t screen_size; int cpp = info->pixel_bytes; struct radeon_bo *front_bo; struct radeon_surface surface; diff --git a/src/radeon.h b/src/radeon.h index 46608938..f1817e74 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -524,7 +524,7 @@ extern void radeon_cs_flush_indirect(ScrnInfoPtr pScrn); extern void radeon_ddx_cs_start(ScrnInfoPtr pScrn, int num, const char *file, const char *func, int line); -void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size); +void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, uint32_t new_fb_size); extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn); drmVBlankSeqType radeon_populate_vbl_request_type(xf86CrtcPtr crtc); diff --git a/src/radeon_kms.c b/src/radeon_kms.c index 82e88d44..9708dc75 100644 --- a/src/radeon_kms.c +++ b/src/radeon_kms.c @@ -1450,7 +1450,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen) RADEONInfoPtr info = RADEONPTR(pScrn); xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); int cpp = info->pixel_bytes; - int screen_size; + uint32_t screen_size; int pitch, base_align; uint32_t tiling_flags = 0; struct radeon_surface surface; @@ -1600,11 +1600,11 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen) return TRUE; } -void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size) +void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, uint32_t new_fb_size) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); RADEONInfoPtr info = RADEONPTR(pScrn); - int remain_size_bytes; + uint64_t remain_size_bytes; int c; for (c = 0; c < xf86_config->num_crtc; c++) { @@ -1615,9 +1615,13 @@ void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size) remain_size_bytes = info->vram_size - new_fb_size; remain_size_bytes = (remain_size_bytes / 10) * 9; - radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_VRAM, remain_size_bytes); + if (remain_size_bytes > 0xffffffff) + remain_size_bytes = 0xffffffff; + radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_VRAM, + (uint32_t)remain_size_bytes); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %dK\n", remain_size_bytes / 1024); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %uK\n", + (uint32_t)remain_size_bytes / 1024); } /* Used to disallow modes that are not supported by the hardware */ |