diff options
| -rw-r--r-- | audio/ossaudio.c | 2 | ||||
| -rw-r--r-- | hw/display/qxl.c | 33 | ||||
| -rw-r--r-- | hw/display/qxl.h | 3 | ||||
| -rw-r--r-- | hw/i386/pc.c | 47 |
4 files changed, 34 insertions, 51 deletions
diff --git a/audio/ossaudio.c b/audio/ossaudio.c index 007c64115..3e04a5837 100644 --- a/audio/ossaudio.c +++ b/audio/ossaudio.c @@ -932,7 +932,7 @@ struct audio_driver oss_audio_driver = { .init = oss_audio_init, .fini = oss_audio_fini, .pcm_ops = &oss_pcm_ops, - .can_be_default = 1, + .can_be_default = 0, .max_voices_out = INT_MAX, .max_voices_in = INT_MAX, .voice_size_out = sizeof (OSSVoiceOut), diff --git a/hw/display/qxl.c b/hw/display/qxl.c index 5977d526d..efdefd662 100644 --- a/hw/display/qxl.c +++ b/hw/display/qxl.c @@ -1701,15 +1701,9 @@ static const MemoryRegionOps qxl_io_ops = { }, }; -static void pipe_read(void *opaque) +static void qxl_update_irq_bh(void *opaque) { PCIQXLDevice *d = opaque; - char dummy; - int len; - - do { - len = read(d->pipe[0], &dummy, sizeof(dummy)); - } while (len == sizeof(dummy)); qxl_update_irq(d); } @@ -1730,28 +1724,7 @@ static void qxl_send_events(PCIQXLDevice *d, uint32_t events) if ((old_pending & le_events) == le_events) { return; } - if (qemu_thread_is_self(&d->main)) { - qxl_update_irq(d); - } else { - if (write(d->pipe[1], d, 1) != 1) { - dprint(d, 1, "%s: write to pipe failed\n", __func__); - } - } -} - -static void init_pipe_signaling(PCIQXLDevice *d) -{ - if (pipe(d->pipe) < 0) { - fprintf(stderr, "%s:%s: qxl pipe creation failed\n", - __FILE__, __func__); - exit(1); - } - fcntl(d->pipe[0], F_SETFL, O_NONBLOCK); - fcntl(d->pipe[1], F_SETFL, O_NONBLOCK); - fcntl(d->pipe[0], F_SETOWN, getpid()); - - qemu_thread_get_self(&d->main); - qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d); + qemu_bh_schedule(d->update_irq); } /* graphics console */ @@ -2044,7 +2017,7 @@ static int qxl_init_common(PCIQXLDevice *qxl) } qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); - init_pipe_signaling(qxl); + qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl); qxl_reset_state(qxl); qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl); diff --git a/hw/display/qxl.h b/hw/display/qxl.h index 84f018238..c5de3d707 100644 --- a/hw/display/qxl.h +++ b/hw/display/qxl.h @@ -81,8 +81,7 @@ typedef struct PCIQXLDevice { QemuMutex track_lock; /* thread signaling */ - QemuThread main; - int pipe[2]; + QEMUBH *update_irq; /* ram pci bar */ QXLRam *ram; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index dee409d27..12c436e7f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -90,7 +90,9 @@ struct e820_table { struct e820_entry entry[E820_NR_ENTRIES]; } QEMU_PACKED __attribute((__aligned__(4))); -static struct e820_table e820_table; +static struct e820_table e820_reserve; +static struct e820_entry *e820_table; +static unsigned e820_entries; struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; void gsi_handler(void *opaque, int n, int level) @@ -577,19 +579,32 @@ static void handle_a20_line_change(void *opaque, int irq, int level) int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) { - int index = le32_to_cpu(e820_table.count); + int index = le32_to_cpu(e820_reserve.count); struct e820_entry *entry; - if (index >= E820_NR_ENTRIES) - return -EBUSY; - entry = &e820_table.entry[index++]; + if (type != E820_RAM) { + /* old FW_CFG_E820_TABLE entry -- reservations only */ + if (index >= E820_NR_ENTRIES) { + return -EBUSY; + } + entry = &e820_reserve.entry[index++]; + + entry->address = cpu_to_le64(address); + entry->length = cpu_to_le64(length); + entry->type = cpu_to_le32(type); - entry->address = cpu_to_le64(address); - entry->length = cpu_to_le64(length); - entry->type = cpu_to_le32(type); + e820_reserve.count = cpu_to_le32(index); + } - e820_table.count = cpu_to_le32(index); - return index; + /* new "etc/e820" file -- include ram too */ + e820_table = g_realloc(e820_table, + sizeof(struct e820_entry) * (e820_entries+1)); + e820_table[e820_entries].address = cpu_to_le64(address); + e820_table[e820_entries].length = cpu_to_le64(length); + e820_table[e820_entries].type = cpu_to_le32(type); + e820_entries++; + + return e820_entries; } /* Calculates the limit to CPU APIC ID values @@ -640,7 +655,9 @@ static FWCfgState *bochs_bios_init(void) fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, smbios_table, smbios_len); fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, - &e820_table, sizeof(e820_table)); + &e820_reserve, sizeof(e820_reserve)); + fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, + sizeof(struct e820_entry) * e820_entries); fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); /* allocate memory for the NUMA channel: one (64bit) word for the number @@ -1157,13 +1174,7 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory, memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 0, below_4g_mem_size); memory_region_add_subregion(system_memory, 0, ram_below_4g); - if (0) { - /* - * Ideally we should do that too, but that would ruin the e820 - * reservations added by seabios before initializing fw_cfg. - */ - e820_add_entry(0, below_4g_mem_size, E820_RAM); - } + e820_add_entry(0, below_4g_mem_size, E820_RAM); if (above_4g_mem_size > 0) { ram_above_4g = g_malloc(sizeof(*ram_above_4g)); memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, |