diff options
| author | Dave Gordon <david.s.gordon@intel.com> | 2016-03-08 13:39:51 +0000 |
|---|---|---|
| committer | John Harrison <John.C.Harrison@Intel.com> | 2016-06-28 17:19:30 +0100 |
| commit | 42d3dd0df58107f214aeb97697a2dcc93eeda1c3 (patch) | |
| tree | c444e6eb75f88a67fd434ba1ab598049b8f9aa57 | |
| parent | c91ff93be86b1f929f648ac6f09788d152377e0b (diff) | |
drm/i915: Tweaking PIPE_CONTROL instructions
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_lrc.c | 44 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 15 |
2 files changed, 50 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index e55e8b9a21c6..6e0ca5bef7a7 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1587,6 +1587,14 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | + PIPE_CONTROL_STALL_AT_SCOREBOARD)); + wa_ctx_emit(batch, index, 0); + wa_ctx_emit(batch, index, 0); + wa_ctx_emit(batch, index, 0); + wa_ctx_emit(batch, index, 0); + + wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); + wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | PIPE_CONTROL_L3_DC_FLUSH)); wa_ctx_emit(batch, index, 0); wa_ctx_emit(batch, index, 0); @@ -1599,6 +1607,14 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256); wa_ctx_emit(batch, index, 0); + wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); + wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | + PIPE_CONTROL_POSTSYNC_FLUSH)); + wa_ctx_emit(batch, index, 0); + wa_ctx_emit(batch, index, 0); + wa_ctx_emit(batch, index, 0); + wa_ctx_emit(batch, index, 0); + return index; } @@ -1673,10 +1689,27 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine, scratch_addr = engine->scratch.gtt_offset + 2*CACHELINE_BYTES; wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); - wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | - PIPE_CONTROL_GEN7_GLOBAL_GTT | - PIPE_CONTROL_CS_STALL | - PIPE_CONTROL_QW_WRITE)); + wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | + PIPE_CONTROL_STALL_AT_SCOREBOARD)); + wa_ctx_emit(batch, index, 0); + wa_ctx_emit(batch, index, 0); + wa_ctx_emit(batch, index, 0); + wa_ctx_emit(batch, index, 0); + + wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); + wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | + PIPE_CONTROL_L3_DC_FLUSH | + PIPE_CONTROL_FLUSH_L3)); + wa_ctx_emit(batch, index, 0); + wa_ctx_emit(batch, index, 0); + wa_ctx_emit(batch, index, 0); + wa_ctx_emit(batch, index, 0); + + wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); + wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | + PIPE_CONTROL_POSTSYNC_FLUSH | + PIPE_CONTROL_QW_WRITE | + PIPE_CONTROL_GEN7_GLOBAL_GTT)); wa_ctx_emit(batch, index, scratch_addr); wa_ctx_emit(batch, index, 0); wa_ctx_emit(batch, index, 0); @@ -2147,7 +2180,8 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request, if (vf_flush_wa) { intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); - intel_logical_ring_emit(ringbuf, 0); + intel_logical_ring_emit(ringbuf, (PIPE_CONTROL_CS_STALL | + PIPE_CONTROL_STALL_AT_SCOREBOARD)); intel_logical_ring_emit(ringbuf, 0); intel_logical_ring_emit(ringbuf, 0); intel_logical_ring_emit(ringbuf, 0); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 24ab3da2a0ab..466c328c78ac 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -293,15 +293,18 @@ gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) struct intel_engine_cs *engine = req->engine; int ret; - ret = intel_ring_begin(req, 4); + ret = intel_ring_begin(req, 6); if (ret) return ret; - intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); + intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD); intel_ring_emit(engine, 0); intel_ring_emit(engine, 0); + intel_ring_emit(engine, 0); + intel_ring_emit(engine, MI_NOOP); + intel_ring_advance(engine); return 0; @@ -358,14 +361,17 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req, gen7_render_ring_cs_stall_wa(req); } - ret = intel_ring_begin(req, 4); + ret = intel_ring_begin(req, 6); if (ret) return ret; - intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); + intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); intel_ring_emit(engine, flags); intel_ring_emit(engine, scratch_addr); intel_ring_emit(engine, 0); + intel_ring_emit(engine, 0); + intel_ring_emit(engine, MI_NOOP); + intel_ring_advance(engine); return 0; @@ -388,6 +394,7 @@ gen8_emit_pipe_control(struct drm_i915_gem_request *req, intel_ring_emit(engine, 0); intel_ring_emit(engine, 0); intel_ring_emit(engine, 0); + intel_ring_advance(engine); return 0; |