diff options
| author | Rohan Garg <rohan.garg@intel.com> | 2024-03-28 11:17:03 +0100 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2024-03-28 19:53:40 +0000 |
| commit | 467ee9d27ab97476ca8bd4640a663851e1886560 (patch) | |
| tree | 61601bb6415fc2c77df165931d69393563e38ff5 | |
| parent | c4b38c717de208dd64dabc21cfc03357bcc6292a (diff) | |
intel/brw: Xe2+ can do SIMD16 for extended math on HF types
BSpec 56797:
Math operation rules when half-floats are used on both source and
destination operands and both source and destinations are packed.
The execution size must be 16.
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27235>
| -rw-r--r-- | src/intel/compiler/brw_fs_lower_simd_width.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/intel/compiler/brw_fs_lower_simd_width.cpp b/src/intel/compiler/brw_fs_lower_simd_width.cpp index 2582b810640..26c5cf026bc 100644 --- a/src/intel/compiler/brw_fs_lower_simd_width.cpp +++ b/src/intel/compiler/brw_fs_lower_simd_width.cpp @@ -287,8 +287,8 @@ brw_fs_get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst) * The execution size must be 16. */ if (is_half_float_src_dst(inst)) - return MIN2(8, inst->exec_size); - + return devinfo->ver < 20 ? MIN2(8, inst->exec_size) : + MIN2(16, inst->exec_size); return MIN2(16, inst->exec_size); } |