intel/isl: Add and use _isl_surf_info_supports_ccs

Replace a lot of open-coded checks which determine if CCS might be
enabled during surface layout.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29167>

2 files changed, 39 insertions, 26 deletions

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 9902452e51c..7600a048edd 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1117,9 +1117,7 @@ isl_surf_choose_tiling(const struct isl_device *dev,
    }
 
    if (intel_needs_workaround(dev->info, 22015614752) &&
-       isl_format_supports_ccs_e(dev->info, info->format) &&
-       !INTEL_DEBUG(DEBUG_NO_CCS) &&
-       !(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT) &&
+       _isl_surf_info_supports_ccs(dev, info->format, info->usage) &&
        (info->levels > 1 || info->depth > 1 || info->array_len > 1)) {
       /* There are issues with multiple engines accessing the same CCS
        * cacheline in parallel. This can happen if this image has multiple
@@ -1726,9 +1724,7 @@ isl_choose_miptail_start_level(const struct isl_device *dev,
       return 15;
 
    if (intel_needs_workaround(dev->info, 22015614752) &&
-       isl_format_supports_ccs_e(dev->info, info->format) &&
-       !INTEL_DEBUG(DEBUG_NO_CCS) &&
-       !(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) {
+       _isl_surf_info_supports_ccs(dev, info->format, info->usage)) {
       /* There are issues with multiple engines accessing the same CCS
        * cacheline in parallel. If we're here, Tile64 is use, providing enough
        * spacing between each miplevel. We must disable miptails to maintain
@@ -2262,9 +2258,9 @@ isl_calc_row_pitch_alignment(const struct isl_device *dev,
        * matches CCS expectations.
        */
       if (ISL_GFX_VER(dev) >= 12 &&
-          isl_format_supports_ccs_e(dev->info, surf_info->format) &&
+          _isl_surf_info_supports_ccs(dev, surf_info->format,
+                                      surf_info->usage) &&
           tile_info->tiling != ISL_TILING_X &&
-          !(surf_info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT) &&
           surf_info->row_pitch_B == 0) {
          return isl_align(tile_info->phys_extent_B.width, 512);
       }
@@ -2696,9 +2692,7 @@ isl_calc_base_alignment(const struct isl_device *dev,
       if (tile_info->tiling == ISL_TILING_GFX12_CCS)
          base_alignment_B = MAX(base_alignment_B, 4096);
 
-      if (isl_format_supports_ccs_e(dev->info, info->format) &&
-          !INTEL_DEBUG(DEBUG_NO_CCS) &&
-          !(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) {
+      if (_isl_surf_info_supports_ccs(dev, info->format, info->usage)) {
          /* Wa_22015614752:
           *
           * Due to L3 cache being tagged with (engineID, vaID) and the CCS
@@ -2983,18 +2977,39 @@ isl_surf_get_mcs_surf(const struct isl_device *dev,
 }
 
 bool
-isl_surf_supports_ccs(const struct isl_device *dev,
-                      const struct isl_surf *surf,
-                      const struct isl_surf *hiz_or_mcs_surf)
+_isl_surf_info_supports_ccs(const struct isl_device *dev,
+                            enum isl_format format,
+                            isl_surf_usage_flags_t usage)
 {
-   if (INTEL_DEBUG(DEBUG_NO_CCS))
+   if (!isl_format_supports_ccs_d(dev->info, format) &&
+       !isl_format_supports_ccs_e(dev->info, format))
+      return false;
+
+   /* CCS is only for color images on Gfx7-11 */
+   if (ISL_GFX_VER(dev) <= 11 && isl_surf_usage_is_depth_or_stencil(usage))
+      return false;
+
+   if (usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)
       return false;
 
-   if (surf->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)
+   /* TODO: Disable for now, as we're not sure about the meaning of
+    * 3DSTATE_CPSIZE_CONTROL_BUFFER::CPCBCompressionEnable
+    */
+   if (isl_surf_usage_is_cpb(usage))
+      return false;
+
+   if (INTEL_DEBUG(DEBUG_NO_CCS))
       return false;
 
-   if (!isl_format_supports_ccs_d(dev->info, surf->format) &&
-       !isl_format_supports_ccs_e(dev->info, surf->format))
+   return true;
+}
+
+bool
+isl_surf_supports_ccs(const struct isl_device *dev,
+                      const struct isl_surf *surf,
+                      const struct isl_surf *hiz_or_mcs_surf)
+{
+   if (!_isl_surf_info_supports_ccs(dev, surf->format, surf->usage))
       return false;
 
    /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
@@ -3019,12 +3034,6 @@ isl_surf_supports_ccs(const struct isl_device *dev,
    if (surf->tiling == ISL_TILING_LINEAR)
       return false;
 
-   /* TODO: Disable for now, as we're not sure about the meaning of
-    * 3DSTATE_CPSIZE_CONTROL_BUFFER::CPCBCompressionEnable
-    */
-   if (isl_surf_usage_is_cpb(surf->usage))
-      return false;
-
    /* SKL PRMs, Volume 5: Memory Views, Tiling and Mip Tails for 2D Surfaces:
     *
     *    "Lossless compression must not be used on surfaces which have MIP
@@ -3184,8 +3193,7 @@ isl_surf_supports_ccs(const struct isl_device *dev,
          return false;
 
       /* CCS is only for color images on Gfx7-11 */
-      if (isl_surf_usage_is_depth_or_stencil(surf->usage))
-         return false;
+      assert(!isl_surf_usage_is_depth_or_stencil(surf->usage));
 
       /* We're single-sampled color so having HiZ or MCS makes no sense */
       assert(hiz_or_mcs_surf == NULL || hiz_or_mcs_surf->size_B == 0);
diff --git a/src/intel/isl/isl_priv.h b/src/intel/isl/isl_priv.h
index 0eb54264bf5..7d036281936 100644
--- a/src/intel/isl/isl_priv.h
+++ b/src/intel/isl/isl_priv.h
@@ -213,6 +213,11 @@ isl_extent3d_el_to_sa(enum isl_format fmt, struct isl_extent3d extent_el)
    };
 }
 
+bool
+_isl_surf_info_supports_ccs(const struct isl_device *dev,
+                            enum isl_format format,
+                            isl_surf_usage_flags_t usage);
+
 void
 _isl_memcpy_linear_to_tiled(uint32_t xt1, uint32_t xt2,
                             uint32_t yt1, uint32_t yt2,