From d52d28f7a946af87b37fe83f7e1e51c88acea14c Mon Sep 17 00:00:00 2001 From: Jordan Justen Date: Wed, 28 May 2014 09:05:37 -0700 Subject: i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LOD gen6 does not support multiple miplevels with separate stencil/hiz. Therefore we need to layout its miptree with no mipmap spacing between the slices of each miplevel. v3: * Use new array_layout enum Signed-off-by: Jordan Justen Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_fbo.c | 3 ++- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 31 +++++++++++++++++--------- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 +++-- src/mesa/drivers/dri/i965/intel_tex.c | 3 ++- src/mesa/drivers/dri/i965/intel_tex_image.c | 3 ++- src/mesa/drivers/dri/i965/intel_tex_subimage.c | 3 ++- src/mesa/drivers/dri/i965/intel_tex_validate.c | 3 ++- 7 files changed, 35 insertions(+), 17 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 164d6c18f7..dc13283d3c 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -980,7 +980,8 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw, width, height, depth, true, irb->mt->num_samples, - INTEL_MIPTREE_TILING_ANY); + INTEL_MIPTREE_TILING_ANY, + false); if (brw_is_hiz_depth_format(brw, new_mt->format)) { intel_miptree_alloc_hiz(brw, new_mt); diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 646717757f..924792b5be 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -232,7 +232,8 @@ intel_miptree_create_layout(struct brw_context *brw, GLuint height0, GLuint depth0, bool for_bo, - GLuint num_samples) + GLuint num_samples, + bool force_all_slices_at_each_lod) { struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1); if (!mt) @@ -368,7 +369,8 @@ intel_miptree_create_layout(struct brw_context *brw, mt->logical_depth0, true, num_samples, - INTEL_MIPTREE_TILING_ANY); + INTEL_MIPTREE_TILING_ANY, + false); if (!mt->stencil_mt) { intel_miptree_release(&mt); return NULL; @@ -386,6 +388,9 @@ intel_miptree_create_layout(struct brw_context *brw, } } + if (force_all_slices_at_each_lod) + mt->array_layout = ALL_SLICES_AT_EACH_LOD; + brw_miptree_layout(brw, mt); return mt; @@ -540,7 +545,8 @@ intel_miptree_create(struct brw_context *brw, GLuint depth0, bool expect_accelerated_upload, GLuint num_samples, - enum intel_miptree_tiling_mode requested_tiling) + enum intel_miptree_tiling_mode requested_tiling, + bool force_all_slices_at_each_lod) { struct intel_mipmap_tree *mt; mesa_format tex_format = format; @@ -554,7 +560,8 @@ intel_miptree_create(struct brw_context *brw, mt = intel_miptree_create_layout(brw, target, format, first_level, last_level, width0, height0, depth0, - false, num_samples); + false, num_samples, + force_all_slices_at_each_lod); /* * pitch == 0 || height == 0 indicates the null texture */ @@ -665,7 +672,7 @@ intel_miptree_create_for_bo(struct brw_context *brw, mt = intel_miptree_create_layout(brw, GL_TEXTURE_2D, format, 0, 0, width, height, 1, - true, 0 /* num_samples */); + true, 0, false); if (!mt) { free(mt); return mt; @@ -774,7 +781,7 @@ intel_miptree_create_for_renderbuffer(struct brw_context *brw, mt = intel_miptree_create(brw, target, format, 0, 0, width, height, depth, true, num_samples, - INTEL_MIPTREE_TILING_ANY); + INTEL_MIPTREE_TILING_ANY, false); if (!mt) goto fail; @@ -1275,7 +1282,8 @@ intel_miptree_alloc_mcs(struct brw_context *brw, mt->logical_depth0, true, 0 /* num_samples */, - INTEL_MIPTREE_TILING_Y); + INTEL_MIPTREE_TILING_Y, + false); /* From the Ivy Bridge PRM, Vol 2 Part 1 p326: * @@ -1332,7 +1340,8 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, mt->logical_depth0, true, 0 /* num_samples */, - INTEL_MIPTREE_TILING_Y); + INTEL_MIPTREE_TILING_Y, + false); return mt->mcs_mt; } @@ -1388,7 +1397,8 @@ intel_miptree_alloc_hiz(struct brw_context *brw, mt->logical_depth0, true, mt->num_samples, - INTEL_MIPTREE_TILING_ANY); + INTEL_MIPTREE_TILING_ANY, + false); if (!mt->hiz_mt) return false; @@ -1765,7 +1775,8 @@ intel_miptree_map_blit(struct brw_context *brw, 0, 0, map->w, map->h, 1, false, 0, - INTEL_MIPTREE_TILING_NONE); + INTEL_MIPTREE_TILING_NONE, + false); if (!map->mt) { fprintf(stderr, "Failed to allocate blit temporary\n"); goto fail; diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index be1bcb8e2e..c6eb9f499f 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -469,7 +469,8 @@ struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw, GLuint depth0, bool expect_accelerated_upload, GLuint num_samples, - enum intel_miptree_tiling_mode); + enum intel_miptree_tiling_mode, + bool force_all_slices_at_each_lod); struct intel_mipmap_tree * intel_miptree_create_layout(struct brw_context *brw, @@ -481,7 +482,8 @@ intel_miptree_create_layout(struct brw_context *brw, GLuint height0, GLuint depth0, bool for_bo, - GLuint num_samples); + GLuint num_samples, + bool force_all_slices_at_each_lod); struct intel_mipmap_tree * intel_miptree_create_for_bo(struct brw_context *brw, diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c index 556b787c3f..549d9b833c 100644 --- a/src/mesa/drivers/dri/i965/intel_tex.c +++ b/src/mesa/drivers/dri/i965/intel_tex.c @@ -145,7 +145,8 @@ intel_alloc_texture_storage(struct gl_context *ctx, width, height, depth, false, /* expect_accelerated */ num_samples, - INTEL_MIPTREE_TILING_ANY); + INTEL_MIPTREE_TILING_ANY, + false); if (intel_texobj->mt == NULL) { return false; diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c index 029d59b7ba..331777919c 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_image.c +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c @@ -81,7 +81,8 @@ intel_miptree_create_for_teximage(struct brw_context *brw, depth, expect_accelerated_upload, intelImage->base.Base.NumSamples, - INTEL_MIPTREE_TILING_ANY); + INTEL_MIPTREE_TILING_ANY, + false); } /* XXX: Do this for TexSubImage also: diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c index 875190ff73..a121816dce 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c @@ -133,7 +133,8 @@ intel_blit_texsubimage(struct gl_context * ctx, intel_miptree_create(brw, GL_TEXTURE_2D, texImage->TexFormat, 0, 0, width, height, 1, - false, 0, INTEL_MIPTREE_TILING_NONE); + false, 0, INTEL_MIPTREE_TILING_NONE, + false); if (!temp_mt) goto err; diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c index 07f3174414..7dee0b23f5 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_validate.c +++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c @@ -142,7 +142,8 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit) depth, true, 0 /* num_samples */, - INTEL_MIPTREE_TILING_ANY); + INTEL_MIPTREE_TILING_ANY, + false); if (!intelObj->mt) return false; } -- cgit v1.2.3