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authorJordan Justen <jordan.l.justen@intel.com>2013-07-09 15:19:55 -0700
committerJordan Justen <jordan.l.justen@intel.com>2014-07-30 11:49:36 -0700
commitbf673f4a0a1cf25c5f9868554a16fe38acea89f5 (patch)
treebae840a1bfb1635704b61d11f12876affdadffad
parentc856cbc8045c506d3e5dde96d580057f5a03ad00 (diff)
i965/gen6 depth surface: calculate LOD being rendered to
(08ef1dd for gen6) This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
-rw-r--r--src/mesa/drivers/dri/i965/gen6_blorp.cpp3
-rw-r--r--src/mesa/drivers/dri/i965/gen6_depth_state.c3
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 20ba31e58a..131c4aa44c 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -794,6 +794,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
uint32_t surftype;
unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
GLenum gl_target = params->depth.mt->target;
+ unsigned int lod;
switch (gl_target) {
case GL_TEXTURE_CUBE_MAP_ARRAY:
@@ -817,6 +818,8 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
NULL,
&tile_mask_x, &tile_mask_y);
+ lod = params->depth.level - params->depth.mt->first_level;
+
/* 3DSTATE_DEPTH_BUFFER */
{
uint32_t tile_x = draw_x & tile_mask_x;
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 8bc0073eda..8ee7c008b9 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -49,6 +49,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
uint32_t surftype;
unsigned int depth = 1;
GLenum gl_target = GL_TEXTURE_2D;
+ unsigned int lod;
const struct intel_renderbuffer *irb = NULL;
const struct gl_renderbuffer *rb = NULL;
@@ -99,6 +100,8 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
break;
}
+ lod = irb ? irb->mt_level - irb->mt->first_level : 0;
+
unsigned int len;
if (brw->gen >= 6)
len = 7;