diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2017-09-07 13:54:52 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-09-07 13:54:52 +0100 |
| commit | 1d2091bc75ab7f9e2c43082f361a528a63c79527 (patch) | |
| tree | 9061bfc54e70d192b4525baf445fdcf9b17cb366 /target | |
| parent | 1e577cc7cffd3de14dbd321de5c3ef191c6ab07f (diff) | |
target/arm: Register second AddressSpace for secure v8M CPUs
If a v8M CPU supports the security extension then we need to
give it two AddressSpaces, the same way we do already for
an A profile core with EL3.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-5-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/cpu.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f32317ec7c..ae866be11a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -843,22 +843,21 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) init_cpreg_list(cpu); #ifndef CONFIG_USER_ONLY - if (cpu->has_el3) { - cs->num_ases = 2; - } else { - cs->num_ases = 1; - } - - if (cpu->has_el3) { + if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { AddressSpace *as; + cs->num_ases = 2; + if (!cpu->secure_memory) { cpu->secure_memory = cs->memory; } as = address_space_init_shareable(cpu->secure_memory, "cpu-secure-memory"); cpu_address_space_init(cs, as, ARMASIdx_S); + } else { + cs->num_ases = 1; } + cpu_address_space_init(cs, address_space_init_shareable(cs->memory, "cpu-memory"), |