diff options
| author | Grazvydas Ignotas <notasas@gmail.com> | 2015-12-22 04:12:07 +0200 |
|---|---|---|
| committer | Emil Velikov <emil.l.velikov@gmail.com> | 2016-01-08 12:05:26 +0200 |
| commit | e468d4b1d69bd8cd290bb5d8fbef72ae28428a6e (patch) | |
| tree | 53421f62dd681dfca2c1162d734dc8d5ac0d5d2c | |
| parent | b95dc1a5c8fb7ff9698c86529cccf43378ccdf3f (diff) | |
r600: fix constant buffer size programming
When buffer size is less than 16, zero ends up being programmed as
size, which prevents the hardware from fetching the correct values.
Fix it by combining shift and align so that the value is always
rounded up.
Cc: "11.1 11.0 10.6" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92229
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit da0e216e069bd064199ed04b52de6fb23d810806)
| -rw-r--r-- | src/gallium/drivers/r600/evergreen_state.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/r600_state.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 8d8cb71905..21ed9970cb 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1944,7 +1944,7 @@ static void evergreen_emit_constant_buffers(struct r600_context *rctx, if (!gs_ring_buffer) { radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4, - ALIGN_DIVUP(cb->buffer_size >> 4, 16), pkt_flags); + ALIGN_DIVUP(cb->buffer_size, 256), pkt_flags); radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8, pkt_flags); } diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 1f9ae912d4..b59d17286b 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -1768,7 +1768,7 @@ static void r600_emit_constant_buffers(struct r600_context *rctx, if (!gs_ring_buffer) { radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4, - ALIGN_DIVUP(cb->buffer_size >> 4, 16)); + ALIGN_DIVUP(cb->buffer_size, 256)); radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8); } |