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| author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2021-03-30 14:50:58 +0200 |
|---|---|---|
| committer | Marge Bot <eric+marge@anholt.net> | 2021-04-05 08:54:55 +0000 |
| commit | 2ded998a573843846e099633ef997f0e6b846820 (patch) | |
| tree | 72d014740937d82e32c2ac0aed1a73966579dd83 | |
| parent | 65bca137bd6e99d3113f1e983a95b666e107e93a (diff) | |
radv: allow DCC for storage images on GFX10.3 with RADV_PERFTEST=dccstores
It's not enabled by default because it requires performance testing.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9919>
| -rw-r--r-- | docs/envvars.rst | 2 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_debug.h | 1 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_device.c | 1 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 6 |
4 files changed, 9 insertions, 1 deletions
diff --git a/docs/envvars.rst b/docs/envvars.rst index 49b1e9fbbf1..8ffc53974d9 100644 --- a/docs/envvars.rst +++ b/docs/envvars.rst @@ -631,6 +631,8 @@ RADV driver environment variables enable wave32 for compute shaders (GFX10+) ``dccmsaa`` enable DCC for MSAA images + ``dccstores`` + enable DCC for storage images (for performance testing on GFX10.3 only) ``dfsm`` enable DFSM ``gewave32`` diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h index 65928b69093..1569fcb108e 100644 --- a/src/amd/vulkan/radv_debug.h +++ b/src/amd/vulkan/radv_debug.h @@ -76,6 +76,7 @@ enum { RADV_PERFTEST_DFSM = 1u << 7, RADV_PERFTEST_NO_SAM = 1u << 8, RADV_PERFTEST_SAM = 1u << 9, + RADV_PERFTEST_DCC_STORES = 1u << 10, }; bool diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index a860b8cba24..2f56ae12798 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -818,6 +818,7 @@ static const struct debug_control radv_perftest_options[] = { {"dfsm", RADV_PERFTEST_DFSM}, {"nosam", RADV_PERFTEST_NO_SAM}, {"sam", RADV_PERFTEST_SAM}, + {"dccstores", RADV_PERFTEST_DCC_STORES}, {NULL, 0} }; diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 4b30ae85d7d..44963dd308b 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -294,7 +294,11 @@ bool radv_image_use_dcc_image_stores(const struct radv_device *device, * * DCC with MSAA > 2 samples results in CTS failures (some of dEQP-VK.pipeline.multisample.storage_image.*). */ - return device->physical_device->rad_info.chip_class == GFX10 && image->info.samples <= 2; + return (device->physical_device->rad_info.chip_class == GFX10 || + (device->physical_device->rad_info.chip_class == GFX10_3 && + (device->instance->perftest_flags & RADV_PERFTEST_DCC_STORES) && + !device->physical_device->use_llvm)) && + image->info.samples <= 2; } /* |