diff options
author | Ian Romanick <ian.d.romanick@intel.com> | 2020-11-13 19:11:56 -0800 |
---|---|---|
committer | Ian Romanick <ian.d.romanick@intel.com> | 2021-12-14 13:28:02 -0800 |
commit | f445c5a3f2435e27a734bf8f6688f8789d435bae (patch) | |
tree | a2a7788749c3bb1f04a15d5ee7686f7d2e071864 | |
parent | 807000b37a366b81bb5dd1ad0cf638a1ebcf9caf (diff) |
intel/fs: Constant fold SHL
Without "intel/fs: Combine constants for integer instructions too", this
commit won't do anything. While looking at one of the shaders hurt by
that commit for instructions, I notied some things like:
mov(1) g25.1<1>D 4D
...
shl(8) g80<1>UD g25.1<0,1,0>D 0x00000001UD
or(8) g11<1>UD g80<8,8,1>UD g50<8,8,1>UW
send(8) nullUD g10UD nullUD 0x060ac2fd 0x00000000
data MsgDesc: ( DC DWORD scatterd write, 253, 2) mlen 3 ex_mlen 0 rlen 0
This looks like some sort of address or offset calculation that is added
in the backend.
shader-db results:
All Gen8+ platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 20027279 -> 20021249 (-0.03%)
instructions in affected programs: 31442 -> 25412 (-19.18%)
helped: 12
HURT: 0
helped stats (abs) min: 18 max: 1152 x̄: 502.50 x̃: 360
helped stats (rel) min: 5.75% max: 23.87% x̄: 18.73% x̃: 19.06%
95% mean confidence interval for instructions value: -717.87 -287.13
95% mean confidence interval for instructions %-change: -22.00% -15.46%
Instructions are helped.
total cycles in shared programs: 978895243 -> 978872081 (<.01%)
cycles in affected programs: 6528787 -> 6505625 (-0.35%)
helped: 12
HURT: 0
helped stats (abs) min: 60 max: 4298 x̄: 1930.17 x̃: 1691
helped stats (rel) min: 0.06% max: 8.13% x̄: 2.11% x̃: 0.40%
95% mean confidence interval for cycles value: -2745.02 -1115.32
95% mean confidence interval for cycles %-change: -3.99% -0.23%
Cycles are helped.
Haswell
total instructions in shared programs: 16389292 -> 16383768 (-0.03%)
instructions in affected programs: 29757 -> 24233 (-18.56%)
helped: 11
HURT: 0
helped stats (abs) min: 18 max: 1171 x̄: 502.18 x̃: 360
helped stats (rel) min: 5.22% max: 23.90% x̄: 18.30% x̃: 18.25%
95% mean confidence interval for instructions value: -745.63 -258.74
95% mean confidence interval for instructions %-change: -22.08% -14.52%
Instructions are helped.
total cycles in shared programs: 1034797073 -> 1034770429 (<.01%)
cycles in affected programs: 6468869 -> 6442225 (-0.41%)
helped: 11
HURT: 0
helped stats (abs) min: 30 max: 6162 x̄: 2422.18 x̃: 2168
helped stats (rel) min: 0.03% max: 8.14% x̄: 2.17% x̃: 0.55%
95% mean confidence interval for cycles value: -3752.79 -1091.58
95% mean confidence interval for cycles %-change: -4.24% -0.10%
Cycles are helped.
total spills in shared programs: 16509 -> 16503 (-0.04%)
spills in affected programs: 1208 -> 1202 (-0.50%)
helped: 2
HURT: 0
total fills in shared programs: 20255 -> 20239 (-0.08%)
fills in affected programs: 168 -> 152 (-9.52%)
helped: 2
HURT: 0
LOST: 0
GAINED: 2
No changes on any earlier platforms.
fossil-db results:
Tiger Lake
Instructions in all programs: 160832341 -> 160827821 (-0.0%)
SENDs in all programs: 6814052 -> 6814052 (+0.0%)
Loops in all programs: 38224 -> 38224 (+0.0%)
Cycles in all programs: 7635756412 -> 7635807190 (+0.0%)
Spills in all programs: 187040 -> 187040 (+0.0%)
Fills in all programs: 292482 -> 292482 (+0.0%)
Ice Lake
Instructions in all programs: 145135276 -> 145132927 (-0.0%)
SENDs in all programs: 6865190 -> 6865190 (+0.0%)
Loops in all programs: 38219 -> 38219 (+0.0%)
Cycles in all programs: 9028602846 -> 9028597718 (-0.0%)
Spills in all programs: 206953 -> 206953 (+0.0%)
Fills in all programs: 313159 -> 313159 (+0.0%)
Skylake
Instructions in all programs: 135836531 -> 135834156 (-0.0%)
SENDs in all programs: 6805651 -> 6805651 (+0.0%)
Loops in all programs: 38216 -> 38216 (+0.0%)
Cycles in all programs: 8649436861 -> 8649426779 (-0.0%)
Spills in all programs: 193981 -> 193981 (+0.0%)
Fills in all programs: 300098 -> 300098 (+0.0%)
-rw-r--r-- | src/intel/compiler/brw_fs.cpp | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 41449b7a536..c70a6e6e329 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -2655,6 +2655,30 @@ fs_visitor::opt_algebraic() progress = true; } break; + case BRW_OPCODE_SHL: + if (inst->src[0].file == IMM && inst->src[1].file == IMM) { + fs_reg result; + + switch (type_sz(inst->src[0].type)) { + case 2: + result = brw_imm_uw(0x0ffff & (inst->src[0].ud << (inst->src[1].ud & 0x0f))); + break; + case 4: + result = brw_imm_ud(inst->src[0].ud << (inst->src[1].ud & 0x1f)); + break; + case 8: + result = brw_imm_uq(inst->src[0].u64 << (inst->src[1].ud & 0x2f)); + break; + } + + inst->opcode = BRW_OPCODE_MOV; + inst->src[0] = retype(result, inst->dst.type); + inst->src[1] = reg_undef; + + progress = true; + } + break; + case SHADER_OPCODE_BROADCAST: if (is_uniform(inst->src[0])) { inst->opcode = BRW_OPCODE_MOV; |