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authorChris Wilson <chris@chris-wilson.co.uk>2020-11-11 14:51:55 +0000
committerChris Wilson <chris@chris-wilson.co.uk>2021-01-31 22:21:04 +0000
commitf7d6c5a691444691f504cd5b5f9896015da33d08 (patch)
tree49f7d8845ba2eaa2a084826969bfa83173733940
parentf590b2f632759267df83a735f152442e750f275d (diff)
HAX x86/rapl: Treat Tigerlake like Icelake
Since Tigerlake seems to have inherited its cstates and other rapl power caps from Icelake, assume it also follows Icelake for its rapl events. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
-rw-r--r--arch/x86/events/rapl.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c
index 7dbbeaacd995..63fb7dac73d1 100644
--- a/arch/x86/events/rapl.c
+++ b/arch/x86/events/rapl.c
@@ -801,6 +801,8 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &model_skl),
X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &model_skl),
X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &model_spr),
+ X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &model_skl),
+ X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &model_skl),
X86_MATCH_VENDOR_FAM(AMD, 0x17, &model_amd_fam17h),
X86_MATCH_VENDOR_FAM(HYGON, 0x18, &model_amd_fam17h),
X86_MATCH_VENDOR_FAM(AMD, 0x19, &model_amd_fam17h),