From efc8d00e4dbe3387db60c3d127b52e0d613ca54d Mon Sep 17 00:00:00 2001 From: "Xiang, Haihao" Date: Fri, 11 Nov 2016 01:42:44 +0800 Subject: Add a new gpe function gen8_gpe_pipe_control() for GEN8 Signed-off-by: Xiang, Haihao Reviewed-by: Zhao Yakui --- src/i965_gpe_utils.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++ src/i965_gpe_utils.h | 19 ++++++++++++++ src/intel_driver.h | 6 +++++ 3 files changed, 98 insertions(+) diff --git a/src/i965_gpe_utils.c b/src/i965_gpe_utils.c index f26d738..1e2f9f3 100644 --- a/src/i965_gpe_utils.c +++ b/src/i965_gpe_utils.c @@ -2440,3 +2440,76 @@ gen8_gpe_mi_conditional_batch_buffer_end(VADriverContextP ctx, param->offset); } + +void +gen8_gpe_pipe_control(VADriverContextP ctx, + struct intel_batchbuffer *batch, + struct gpe_pipe_control_parameter *param) +{ + int render_target_cache_flush_enable = CMD_PIPE_CONTROL_WC_FLUSH; + int dc_flush_enable = 0; + int state_cache_invalidation_enable = 0; + int constant_cache_invalidation_enable = 0; + int vf_cache_invalidation_enable = 0; + int instruction_cache_invalidation_enable = 0; + int post_sync_operation = CMD_PIPE_CONTROL_NOWRITE; + int use_global_gtt = CMD_PIPE_CONTROL_GLOBAL_GTT_GEN8; + int cs_stall_enable = !param->disable_cs_stall; + + switch (param->flush_mode) { + case PIPE_CONTROL_FLUSH_WRITE_CACHE: + render_target_cache_flush_enable = CMD_PIPE_CONTROL_WC_FLUSH; + dc_flush_enable = CMD_PIPE_CONTROL_DC_FLUSH; + break; + + case PIPE_CONTROL_FLUSH_READ_CACHE: + render_target_cache_flush_enable = 0; + state_cache_invalidation_enable = CMD_PIPE_CONTROL_SC_INVALIDATION_GEN8; + constant_cache_invalidation_enable = CMD_PIPE_CONTROL_CC_INVALIDATION_GEN8; + vf_cache_invalidation_enable = CMD_PIPE_CONTROL_VFC_INVALIDATION_GEN8; + instruction_cache_invalidation_enable = CMD_PIPE_CONTROL_IS_FLUSH; + break; + + case PIPE_CONTROL_FLUSH_NONE: + default: + render_target_cache_flush_enable = 0; + break; + } + + if (param->bo) { + post_sync_operation = CMD_PIPE_CONTROL_WRITE_QWORD; + use_global_gtt = CMD_PIPE_CONTROL_LOCAL_PGTT_GEN8; + } else { + post_sync_operation = CMD_PIPE_CONTROL_NOWRITE; + render_target_cache_flush_enable = CMD_PIPE_CONTROL_WC_FLUSH; + state_cache_invalidation_enable = CMD_PIPE_CONTROL_SC_INVALIDATION_GEN8; + constant_cache_invalidation_enable = CMD_PIPE_CONTROL_CC_INVALIDATION_GEN8; + vf_cache_invalidation_enable = CMD_PIPE_CONTROL_VFC_INVALIDATION_GEN8; + instruction_cache_invalidation_enable = CMD_PIPE_CONTROL_IS_FLUSH; + } + + __OUT_BATCH(batch, CMD_PIPE_CONTROL | (6 - 2)); + __OUT_BATCH(batch, (render_target_cache_flush_enable | + dc_flush_enable | + state_cache_invalidation_enable | + constant_cache_invalidation_enable | + vf_cache_invalidation_enable | + instruction_cache_invalidation_enable | + post_sync_operation | + use_global_gtt | + cs_stall_enable | + CMD_PIPE_CONTROL_FLUSH_ENABLE)); + + if (param->bo) + __OUT_RELOC64(batch, + param->bo, + I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_RENDER, + param->offset); + else { + __OUT_BATCH(batch, 0); + __OUT_BATCH(batch, 0); + } + + __OUT_BATCH(batch, param->dw0); + __OUT_BATCH(batch, param->dw1); +} diff --git a/src/i965_gpe_utils.h b/src/i965_gpe_utils.h index debc1f9..f8ee228 100644 --- a/src/i965_gpe_utils.h +++ b/src/i965_gpe_utils.h @@ -73,6 +73,20 @@ struct gpe_dynamic_state_parameter unsigned int sampler_offset; }; +#define PIPE_CONTROL_FLUSH_NONE 0 +#define PIPE_CONTROL_FLUSH_WRITE_CACHE 1 +#define PIPE_CONTROL_FLUSH_READ_CACHE 2 + +struct gpe_pipe_control_parameter +{ + dri_bo *bo; + unsigned int offset; + unsigned int flush_mode; + unsigned int disable_cs_stall; + unsigned int dw0; + unsigned int dw1; +}; + struct i965_gpe_context { struct { @@ -537,4 +551,9 @@ gen8_gpe_mi_conditional_batch_buffer_end(VADriverContextP ctx, struct intel_batchbuffer *batch, struct gpe_mi_conditional_batch_buffer_end_parameter *param); +extern void +gen8_gpe_pipe_control(VADriverContextP ctx, + struct intel_batchbuffer *batch, + struct gpe_pipe_control_parameter *param); + #endif /* _I965_GPE_UTILS_H_ */ diff --git a/src/intel_driver.h b/src/intel_driver.h index dcdc03b..4ff707d 100644 --- a/src/intel_driver.h +++ b/src/intel_driver.h @@ -76,12 +76,18 @@ #define CMD_PIPE_CONTROL_IS_FLUSH (1 << 11) #define CMD_PIPE_CONTROL_TC_FLUSH (1 << 10) #define CMD_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) +#define CMD_PIPE_CONTROL_FLUSH_ENABLE (1 << 7) #define CMD_PIPE_CONTROL_DC_FLUSH (1 << 5) #define CMD_PIPE_CONTROL_GLOBAL_GTT (1 << 2) #define CMD_PIPE_CONTROL_LOCAL_PGTT (0 << 2) #define CMD_PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1) #define CMD_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) +#define CMD_PIPE_CONTROL_GLOBAL_GTT_GEN8 (1 << 24) +#define CMD_PIPE_CONTROL_LOCAL_PGTT_GEN8 (0 << 24) +#define CMD_PIPE_CONTROL_VFC_INVALIDATION_GEN8 (1 << 4) +#define CMD_PIPE_CONTROL_CC_INVALIDATION_GEN8 (1 << 3) +#define CMD_PIPE_CONTROL_SC_INVALIDATION_GEN8 (1 << 2) struct intel_batchbuffer; -- cgit v1.2.3