From b8bb1cfb3a6ff990aef345dcf5777142936184a2 Mon Sep 17 00:00:00 2001 From: Jerome Glisse Date: Sat, 20 Feb 2010 11:00:18 +0100 Subject: move toward shader being stored in bo --- r600_atom.c | 34 ++++++++++++++++++---------------- r600_atom_kernel.h | 6 ++++-- r600_batch.c | 19 ------------------- radeon_device.h | 2 -- test.c | 28 +++++++++++++++++++++++++--- 5 files changed, 47 insertions(+), 42 deletions(-) diff --git a/r600_atom.c b/r600_atom.c index 4e90568..62af283 100644 --- a/r600_atom.c +++ b/r600_atom.c @@ -649,15 +649,9 @@ int r600_vs_shader_emit(struct radeon_device *rdev, void *data, struct radeon_ib *ib) { - struct drm_r600_vs_shader *vs_shader = atom->state; - struct r600_batch *batch = (struct r600_batch *)data; - u32 *opcodes = batch->shaders->ptr, ndwords; int r; - memcpy(&opcodes[batch->shaders_idx], vs_shader->opcodes, vs_shader->ndwords * 4); - atom->pkts[2] = batch->shaders_idx >> 6; - atom->pkts[4] = radeon_ib_reloc(ib, batch->shaders, RADEON_GEM_DOMAIN_GTT); - batch->shaders_idx += (vs_shader->ndwords + 63) & 0xFFFFFFC0; + atom->pkts[4] = radeon_ib_reloc(ib, atom->bo[0], RADEON_GEM_DOMAIN_GTT); r = radeon_ib_copy(ib, atom->pkts, atom->npkts); return r; } @@ -672,11 +666,18 @@ int r600_vs_shader_create(struct radeon_device *rdev, struct radeon_atom *atom, if (vs_shader == NULL) return -ENOMEM; memcpy(vs_shader, data, sizeof(struct drm_r600_vs_shader)); + atom->bo[0] = radeon_bo_lookup(rdev, vs_shader->handle); + atom->flags[0] = 0x08000000; + if (atom->bo[0] == NULL) { + return -EINVAL; + } + atom->nbo = 1; + atom->nflushes = 1; atom->state = vs_shader; /* SQ_PGM_START_VS */ atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1); atom->pkts[atom->npkts++] = 0x00000216; - atom->pkts[atom->npkts++] = 0x00000000; + atom->pkts[atom->npkts++] = vs_shader->offset; atom->pkts[atom->npkts++] = PKT3(PKT3_NOP, 0); atom->pkts[atom->npkts++] = 0x00000000; /* SQ_PGM_RESOURCES_VS */ @@ -725,15 +726,9 @@ int r600_ps_shader_emit(struct radeon_device *rdev, void *data, struct radeon_ib *ib) { - struct drm_r600_ps_shader *ps_shader = atom->state; - struct r600_batch *batch = (struct r600_batch *)data; - u32 *opcodes = batch->shaders->ptr; int r; - memcpy(&opcodes[batch->shaders_idx], ps_shader->opcodes, ps_shader->ndwords * 4); - atom->pkts[2] = batch->shaders_idx >> 6; - atom->pkts[4] = radeon_ib_reloc(ib, batch->shaders, RADEON_GEM_DOMAIN_GTT); - batch->shaders_idx += (ps_shader->ndwords + 63) & 0xFFFFFFC0; + atom->pkts[4] = radeon_ib_reloc(ib, atom->bo[0], RADEON_GEM_DOMAIN_GTT); r = radeon_ib_copy(ib, atom->pkts, atom->npkts); return r; } @@ -749,10 +744,17 @@ int r600_ps_shader_create(struct radeon_device *rdev, struct radeon_atom *atom, return -ENOMEM; memcpy(ps_shader, data, sizeof(struct drm_r600_ps_shader)); atom->state = ps_shader; + atom->bo[0] = radeon_bo_lookup(rdev, ps_shader->handle); + atom->flags[0] = 0x08000000; + if (atom->bo[0] == NULL) { + return -EINVAL; + } + atom->nbo = 1; + atom->nflushes = 1; /* SQ_PGM_START_PS */ atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1); atom->pkts[atom->npkts++] = 0x00000210; - atom->pkts[atom->npkts++] = 0x00000000; + atom->pkts[atom->npkts++] = ps_shader->offset; atom->pkts[atom->npkts++] = PKT3(PKT3_NOP, 0); atom->pkts[atom->npkts++] = 0x00000000; /* SQ_PGM_RESOURCES_PS */ diff --git a/r600_atom_kernel.h b/r600_atom_kernel.h index dc3dcf4..63ee9f3 100644 --- a/r600_atom_kernel.h +++ b/r600_atom_kernel.h @@ -174,7 +174,8 @@ struct drm_r600_vs_shader { u8 fog_output_id; u8 noutputs; u32 ndwords; - u32 opcodes[512]; + u32 handle; + u32 offset; }; /* ps_shader - pixel shader */ @@ -185,7 +186,8 @@ struct drm_r600_ps_shader { u32 sq_pgm_resources_ps; u32 sq_pgm_exports_ps; u32 ndwords; - u32 opcodes[512]; + u32 handle; + u32 offset; }; struct drm_r600_vs_buffer { diff --git a/r600_batch.c b/r600_batch.c index a322430..2349145 100644 --- a/r600_batch.c +++ b/r600_batch.c @@ -95,7 +95,6 @@ static int r600_batch_alloc(struct r600_batch **batch) INIT_LIST_HEAD(&rbatch->pre_flushes); INIT_LIST_HEAD(&rbatch->post_flushes); rbatch->nemit_atoms = 0; - rbatch->shaders_idx = 0; rbatch->nfs_resources = 0; *batch = rbatch; return 0; @@ -146,8 +145,6 @@ static void r600_batches_clear_locked(struct radeon_device *rdev, struct r600_ba radeon_atom_flush_cleanup(&batch->pre_flushes); radeon_atom_flush_cleanup(&batch->post_flushes); list_del(&batch->list); - radeon_bo_unmap(batch->shaders); - radeon_bo_unref(batch->shaders); free(batch); } INIT_LIST_HEAD(&batches->batches); @@ -179,8 +176,6 @@ static int r600_batches_flush_locked(struct radeon_device *rdev, struct r600_bat list_for_each_entry(flush, &batch->pre_flushes, list) { r600_emit_flush(rdev, batches->ib, flush->bo, flush->flags); } - /* FIXME shader flush should be conditional */ - r600_emit_flush(rdev, batches->ib, batch->shaders, 0x08000000); for (i = 0; i < batch->nemit_atoms; i++) { r = batch->emit_atoms[i]->emit(rdev, batch->emit_atoms[i], batch, batches->ib); if (r) @@ -225,18 +220,6 @@ int r600_batches_queue(struct radeon_device *rdev, struct r600_request *rq) fprintf(stderr, "invalid batch\n"); return -EINVAL; } - rbatch->shaders = radeon_bo_open(rdev->bom, 0, 4096 * 16, 0, RADEON_GEM_DOMAIN_GTT, 0); - if (rbatch->shaders == NULL) { - free(rbatch); - fprintf(stderr, "can't create buffer for shaders\n"); - return -ENOMEM; - } - r = radeon_bo_map(rbatch->shaders, 1); - if (r) { - free(rbatch); - fprintf(stderr, "can't map buffer for shaders\n"); - return r; - } rbatch->atoms[i++] = batch->blend; kref_get(&batch->blend->kref); rbatch->atoms[i++] = batch->cb_cntl; kref_get(&batch->cb_cntl->kref); rbatch->atoms[i++] = batch->pa; kref_get(&batch->pa->kref); @@ -320,8 +303,6 @@ out_err: if (rbatch->atoms[i]) radeon_atom_put(rbatch->atoms[i]); } - radeon_bo_unmap(rbatch->shaders); - radeon_bo_unref(rbatch->shaders); free(rbatch); return r; } diff --git a/radeon_device.h b/radeon_device.h index b943e0e..e8704f8 100644 --- a/radeon_device.h +++ b/radeon_device.h @@ -124,8 +124,6 @@ struct r600_batch { u32 nemit_atoms; u32 nflushes; u32 npkts; - struct radeon_bo *shaders; - u32 shaders_idx; u32 nfs_resources; struct r600_vs_input inputs; }; diff --git a/test.c b/test.c index e76efbc..bd95914 100644 --- a/test.c +++ b/test.c @@ -104,6 +104,8 @@ int r600_tri_flat(struct radeon *radeon) struct drm_r600_ps_shader ps_shader; struct drm_r600_batch batch; struct radeon_bo *vbo1; + struct radeon_bo *vs; + struct radeon_bo *ps; int r; vbo1 = radeon_bo_open(radeon->bom, 0, 4096, 0, RADEON_GEM_DOMAIN_GTT, 0); @@ -112,7 +114,21 @@ int r600_tri_flat(struct radeon *radeon) return -ENOMEM; } memset_bo(vbo1, 0); - memcpy_bo(vbo1, (u32*)rvbo1, 32); + memcpy_bo(vbo1, (u32*)rvbo1, 32 * 4); + vs = radeon_bo_open(radeon->bom, 0, 4096, 0, RADEON_GEM_DOMAIN_GTT, 0); + if (vs == NULL) { + fprintf(stderr, "Failed to create vs bo\n"); + return -ENOMEM; + } + memset_bo(vs, 0); + memcpy_bo(vs, (u32*)vsshaders, 20 * 4); + ps = radeon_bo_open(radeon->bom, 0, 4096, 0, RADEON_GEM_DOMAIN_GTT, 0); + if (ps == NULL) { + fprintf(stderr, "Failed to create ps bo\n"); + return -ENOMEM; + } + memset_bo(ps, 0); + memcpy_bo(ps, (u32*)psshaders, 64 * 4); r = radeon_device_init(&rdev, radeon->bom, radeon->fd); if (r) @@ -259,7 +275,10 @@ int r600_tri_flat(struct radeon *radeon) vs_shader.output_semantic[0] = 4; vs_shader.sq_pgm_resources_vs = 0x00000106; vs_shader.ndwords = 64; - memcpy(vs_shader.opcodes, vsshaders, vs_shader.ndwords * 4); + vs_shader.handle = vs->handle; + vs_shader.offset = 0; + rq.bo[0] = vs; + rq.nbo = 1; rq.type = R600_ATOM_VS_SHADER; rq.data = &vs_shader; batch.vs_shader = r600_atom_create(rdev, &rq); @@ -271,7 +290,10 @@ int r600_tri_flat(struct radeon *radeon) ps_shader.sq_pgm_resources_ps = 0x00000003; ps_shader.sq_pgm_exports_ps = 0x00000002; ps_shader.ndwords = 20; - memcpy(ps_shader.opcodes, psshaders, ps_shader.ndwords * 4); + ps_shader.handle = ps->handle; + ps_shader.offset = 0; + rq.bo[0] = ps; + rq.nbo = 1; rq.type = R600_ATOM_PS_SHADER; rq.data = &ps_shader; batch.ps_shader = r600_atom_create(rdev, &rq); -- cgit v1.2.3