/*
 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * on the rights to use, copy, modify, merge, publish, distribute, sub
 * license, and/or sell copies of the Software, and to permit persons to whom
 * the Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *      Jerome Glisse
 */
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include "radeon_pci.h"
#include "reg.h"

int main(int argc, char *argv[])
{
    struct radeon_pci pradeon;
    struct dump dump = {0, };
    struct range range = {0, };

    if (radeon_pci_init(&pradeon)) {
        return -1;
    }

    printf("0x0E50_SRBM_STATUS                0x%08x\n", radeon_mmio_rd32(&pradeon, 0x0e50));
    printf("0x8010_GRBM_STATUS                0x%08x\n", radeon_mmio_rd32(&pradeon, 0x8010));
    printf("0x8014_GRBM_STATUS_SE0            0x%08x\n", radeon_mmio_rd32(&pradeon, 0x8014));
    printf("0x8018_GRBM_STATUS_SE1            0x%08x\n", radeon_mmio_rd32(&pradeon, 0x8018));

    printf("0x98F4_CC_RB_BACKEND_DISABLE      0x%08x\n", radeon_mmio_rd32(&pradeon, 0x98F4));
    printf("0x98F8_GB_ADDR_CONFIG             0x%08x\n", radeon_mmio_rd32(&pradeon, 0x98F8));
    printf("0x98FC_GB_BACKEND_MAP             0x%08x\n", radeon_mmio_rd32(&pradeon, 0x98FC));

    printf("0x8950_CC_GC_SHADER_PIPE_CONFIG   0x%08x\n", radeon_mmio_rd32(&pradeon, 0x8950));
    printf("0x8954_GC_USER_SHADER_PIPE_CONFIG 0x%08x\n", radeon_mmio_rd32(&pradeon, 0x8954));

    /* general reg */
#if 0
    range.foffset = 0x0008;
    range.loffset = 0x0800;
    range.stride = 4;
    dump_range(&dump, &pradeon, &range);
    dump_print(&dump);
    dump_fini(&dump);
#endif
    /* general reg */
#if 0
    range.foffset = 0x0c00;
    range.loffset = 0x1000;
    range.stride = 4;
    dump_range(&dump, &pradeon, &range);
    dump_print(&dump);
    dump_fini(&dump);
#endif
#if 0
    /* config reg */
    range.foffset = 0x8000;
    range.loffset = 0xac00;
    range.stride = 4;
    dump_range(&dump, &pradeon, &range);
    dump_print(&dump);
    dump_fini(&dump);
#endif
#if 0
    /* context reg */
    range.foffset = 0x29000;
    range.loffset = 0x2A000;
    range.stride = 4;
    dump_range(&dump, &pradeon, &range);
    dump_print(&dump);
    dump_fini(&dump);
#endif

    radeon_pci_fini(&pradeon);
    return 0;
}