/* * Copyright 2009 Advanced Micro Devices, Inc. * Copyright 2012 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * on the rights to use, copy, modify, merge, publish, distribute, sub * license, and/or sell copies of the Software, and to permit persons to whom * the Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * Authors: * Alex Deucher * Jerome Glisse */ #include #include #include #include #include "replayx.h" #include "xf86drm.h" #include "radeon_drm.h" #include "radeon_family.h" #include "r6xx.h" #include "r6xxd.h" void r6xx_emit_reloc(struct r6xx_blit *blit, struct ctx_bo *bo) { unsigned i; for (i = 0; i < 3; i++) { if (blit->relocs[i].handle == bo->handle) { blit->cs[blit->cdw++] = PKT3(IT_NOP, 1); blit->cs[blit->cdw++] = i * 4; return; } } } int r6xx_sq_conf(struct r6xx_blit *blit) { struct r6xx_sq_conf *sq_conf = &blit->sq_conf; sq_conf->ps_prio = 0; sq_conf->vs_prio = 1; sq_conf->gs_prio = 2; sq_conf->es_prio = 3; /* need to set stack/thread/gpr limits based on the asic * for now just set them low enough so any card will work * see r600_cp.c in the drm */ switch (blit->ctx->family) { case CHIP_R600: sq_conf->num_ps_gprs = 192; sq_conf->num_vs_gprs = 56; sq_conf->num_temp_gprs = 4; sq_conf->num_gs_gprs = 0; sq_conf->num_es_gprs = 0; sq_conf->num_ps_threads = 136; sq_conf->num_vs_threads = 48; sq_conf->num_gs_threads = 4; sq_conf->num_es_threads = 4; sq_conf->num_ps_stack_entries = 128; sq_conf->num_vs_stack_entries = 128; sq_conf->num_gs_stack_entries = 0; sq_conf->num_es_stack_entries = 0; break; case CHIP_RV630: case CHIP_RV635: sq_conf->num_ps_gprs = 84; sq_conf->num_vs_gprs = 36; sq_conf->num_temp_gprs = 4; sq_conf->num_gs_gprs = 0; sq_conf->num_es_gprs = 0; sq_conf->num_ps_threads = 144; sq_conf->num_vs_threads = 40; sq_conf->num_gs_threads = 4; sq_conf->num_es_threads = 4; sq_conf->num_ps_stack_entries = 40; sq_conf->num_vs_stack_entries = 40; sq_conf->num_gs_stack_entries = 32; sq_conf->num_es_stack_entries = 16; break; case CHIP_RV610: case CHIP_RV620: case CHIP_RS780: case CHIP_RS880: default: sq_conf->num_ps_gprs = 84; sq_conf->num_vs_gprs = 36; sq_conf->num_temp_gprs = 4; sq_conf->num_gs_gprs = 0; sq_conf->num_es_gprs = 0; sq_conf->num_ps_threads = 136; sq_conf->num_vs_threads = 48; sq_conf->num_gs_threads = 4; sq_conf->num_es_threads = 4; sq_conf->num_ps_stack_entries = 40; sq_conf->num_vs_stack_entries = 40; sq_conf->num_gs_stack_entries = 32; sq_conf->num_es_stack_entries = 16; break; case CHIP_RV670: sq_conf->num_ps_gprs = 144; sq_conf->num_vs_gprs = 40; sq_conf->num_temp_gprs = 4; sq_conf->num_gs_gprs = 0; sq_conf->num_es_gprs = 0; sq_conf->num_ps_threads = 136; sq_conf->num_vs_threads = 48; sq_conf->num_gs_threads = 4; sq_conf->num_es_threads = 4; sq_conf->num_ps_stack_entries = 40; sq_conf->num_vs_stack_entries = 40; sq_conf->num_gs_stack_entries = 32; sq_conf->num_es_stack_entries = 16; break; case CHIP_RV770: sq_conf->num_ps_gprs = 192; sq_conf->num_vs_gprs = 56; sq_conf->num_temp_gprs = 4; sq_conf->num_gs_gprs = 0; sq_conf->num_es_gprs = 0; sq_conf->num_ps_threads = 188; sq_conf->num_vs_threads = 60; sq_conf->num_gs_threads = 0; sq_conf->num_es_threads = 0; sq_conf->num_ps_stack_entries = 256; sq_conf->num_vs_stack_entries = 256; sq_conf->num_gs_stack_entries = 0; sq_conf->num_es_stack_entries = 0; break; case CHIP_RV730: case CHIP_RV740: sq_conf->num_ps_gprs = 84; sq_conf->num_vs_gprs = 36; sq_conf->num_temp_gprs = 4; sq_conf->num_gs_gprs = 0; sq_conf->num_es_gprs = 0; sq_conf->num_ps_threads = 188; sq_conf->num_vs_threads = 60; sq_conf->num_gs_threads = 0; sq_conf->num_es_threads = 0; sq_conf->num_ps_stack_entries = 128; sq_conf->num_vs_stack_entries = 128; sq_conf->num_gs_stack_entries = 0; sq_conf->num_es_stack_entries = 0; break; case CHIP_RV710: sq_conf->num_ps_gprs = 192; sq_conf->num_vs_gprs = 56; sq_conf->num_temp_gprs = 4; sq_conf->num_gs_gprs = 0; sq_conf->num_es_gprs = 0; sq_conf->num_ps_threads = 144; sq_conf->num_vs_threads = 48; sq_conf->num_gs_threads = 0; sq_conf->num_es_threads = 0; sq_conf->num_ps_stack_entries = 128; sq_conf->num_vs_stack_entries = 128; sq_conf->num_gs_stack_entries = 0; sq_conf->num_es_stack_entries = 0; break; } /* SQ setup */ switch (blit->ctx->family) { case CHIP_RV610: case CHIP_RV620: case CHIP_RS780: case CHIP_RS880: case CHIP_RV710: /* no vertex cache (VC) */ sq_conf->sq_config = SQ_CONFIG__VC_ENABLE(0); break; default: sq_conf->sq_config = SQ_CONFIG__VC_ENABLE(1); break; } sq_conf->sq_config |= SQ_CONFIG__DX9_CONSTS(1) | SQ_CONFIG__ALU_INST_PREFER_VECTOR(1) | SQ_CONFIG__PS_PRIO(sq_conf->ps_prio) | SQ_CONFIG__VS_PRIO(sq_conf->vs_prio) | SQ_CONFIG__GS_PRIO(sq_conf->gs_prio) | SQ_CONFIG__ES_PRIO(sq_conf->es_prio); return 0; } int r6xx_set_vport_scissor(struct r6xx_blit *blit, unsigned id, int x1, int y1, int x2, int y2) { unsigned cdw = blit->cdw + 4; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 3); blit->cs[blit->cdw++] = ((PA_SC_VPORT_SCISSOR_0_TL + id * PA_SC_VPORT_SCISSOR_0_TL__STRIDE) - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = PA_SC_VPORT_SCISSOR_0_TL__TL_X(x1) | PA_SC_VPORT_SCISSOR_0_TL__TL_Y(y1) | PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE(1); blit->cs[blit->cdw++] = PA_SC_VPORT_SCISSOR_0_BR__BR_X(x2) | PA_SC_VPORT_SCISSOR_0_BR__BR_Y(y2); if (blit->cdw != cdw) { fprintf(stderr, "%s %d cdw missmatch expected %d got %d\n", __func__, __LINE__, cdw, blit->cdw); return -EFBIG; } return 0; } int r6xx_set_generic_scissor(struct r6xx_blit *blit, int x1, int y1, int x2, int y2) { unsigned cdw = blit->cdw + 4; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 3); blit->cs[blit->cdw++] = (PA_SC_GENERIC_SCISSOR_TL - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = PA_SC_GENERIC_SCISSOR_TL__TL_X(x1) | PA_SC_GENERIC_SCISSOR_TL__TL_Y(y1) | PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE(1); blit->cs[blit->cdw++] = PA_SC_GENERIC_SCISSOR_BR__BR_X(x2) | PA_SC_GENERIC_SCISSOR_BR__BR_Y(y2); if (blit->cdw != cdw) { fprintf(stderr, "%s %d cdw missmatch expected %d got %d\n", __func__, __LINE__, cdw, blit->cdw); return -EFBIG; } return 0; } int r6xx_set_window_scissor(struct r6xx_blit *blit, int x1, int y1, int x2, int y2) { unsigned cdw = blit->cdw + 4; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 3); blit->cs[blit->cdw++] = (PA_SC_WINDOW_SCISSOR_TL - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = PA_SC_WINDOW_SCISSOR_TL__TL_X(x1) | PA_SC_WINDOW_SCISSOR_TL__TL_Y(y1) | PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE(1); blit->cs[blit->cdw++] = PA_SC_WINDOW_SCISSOR_BR__BR_X(x2) | PA_SC_WINDOW_SCISSOR_BR__BR_Y(y2); if (blit->cdw != cdw) { fprintf(stderr, "%s %d cdw missmatch expected %d got %d\n", __func__, __LINE__, cdw, blit->cdw); return -EFBIG; } return 0; } int r6xx_set_screen_scissor(struct r6xx_blit *blit, int x1, int y1, int x2, int y2) { unsigned cdw = blit->cdw + 4; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 3); blit->cs[blit->cdw++] = (PA_SC_SCREEN_SCISSOR_TL - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = PA_SC_SCREEN_SCISSOR_TL__TL_X(x1) | PA_SC_SCREEN_SCISSOR_TL__TL_Y(y1); blit->cs[blit->cdw++] = PA_SC_SCREEN_SCISSOR_BR__BR_X(x2) | PA_SC_SCREEN_SCISSOR_BR__BR_Y(y2); if (blit->cdw != cdw) { fprintf(stderr, "%s %d cdw missmatch expected %d got %d\n", __func__, __LINE__, cdw, blit->cdw); return -EFBIG; } return 0; } int r6xx_set_clip_rect(struct r6xx_blit *blit, unsigned id, int x1, int y1, int x2, int y2) { unsigned cdw = blit->cdw + 4; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 3); blit->cs[blit->cdw++] = ((PA_SC_CLIPRECT_0_TL + id * PA_SC_CLIPRECT_0_TL__STRIDE) - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = PA_SC_CLIPRECT_0_TL__TL_X(x1) | PA_SC_CLIPRECT_0_TL__TL_Y(y1); blit->cs[blit->cdw++] = PA_SC_CLIPRECT_0_BR__BR_X(x2) | PA_SC_CLIPRECT_0_BR__BR_Y(y2); if (blit->cdw != cdw) { fprintf(stderr, "%s %d cdw missmatch expected %d got %d\n", __func__, __LINE__, cdw, blit->cdw); return -EFBIG; } return 0; } int r6xx_set_render_target(struct r6xx_blit *blit, struct ctx_bo *bo) { uint32_t cb_color_info; unsigned pitch, slice; unsigned cdw = blit->cdw + 50; pitch = bo->pitch; slice = bo->h * pitch; cb_color_info = CB_COLOR0_INFO__FORMAT(bo->hw_format)| CB_COLOR0_INFO__COMP_SWAP(SWAP_ALT); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = ((CB_COLOR0_BASE) - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; r6xx_emit_reloc(blit, bo); /* rv6xx workaround */ if ((blit->ctx->family > CHIP_R600) && (blit->ctx->family < CHIP_RV770)) { cdw += 2; blit->cs[blit->cdw++] = PKT3(IT_SURFACE_BASE_UPDATE, 1); blit->cs[blit->cdw++] = (1 << 1); } /* set CMASK & TILE buffer to the offset of color buffer as * we don't use those this shouldn't cause any issue and we * then have a valid cmd stream */ blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = ((CB_COLOR0_TILE) - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; r6xx_emit_reloc(blit, bo); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = ((CB_COLOR0_FRAG) - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; r6xx_emit_reloc(blit, bo); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = ((CB_COLOR0_SIZE) - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = CB_COLOR0_SIZE__PITCH_TILE_MAX((pitch >> 3) - 1) | CB_COLOR0_SIZE__SLICE_TILE_MAX((slice >> 6) - 1); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = ((CB_COLOR0_VIEW) - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = CB_COLOR0_VIEW__SLICE_START(0) | CB_COLOR0_VIEW__SLICE_MAX(0); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = ((CB_COLOR0_MASK) - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = CB_COLOR0_MASK__CMASK_BLOCK_MAX(0) | CB_COLOR0_MASK__FMASK_TILE_MAX(0); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = ((CB_COLOR0_INFO) - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = cb_color_info; r6xx_emit_reloc(blit, bo); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = ((CB_TARGET_MASK) - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = CB_TARGET_MASK__TARGET0_ENABLE(0xf); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = ((CB_COLOR_CONTROL) - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = CB_COLOR_CONTROL__ROP3(ROP3_COPY); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = ((CB_BLEND_CONTROL) - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; r6xx_set_generic_scissor(blit, 0, 0, bo->w, bo->h); r6xx_set_screen_scissor(blit, 0, 0, bo->w, bo->h); r6xx_set_window_scissor(blit, 0, 0, bo->w, bo->h); if (blit->cdw != cdw) { fprintf(stderr, "%s %d cdw missmatch expected %d got %d\n", __func__, __LINE__, cdw, blit->cdw); return -EFBIG; } return 0; } int r6xx_fs_setup(struct r6xx_blit *blit, struct ctx_bo *bo, unsigned offset, unsigned ngprs, unsigned stack_size) { unsigned cdw = blit->cdw + 11; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (SQ_PGM_START_FS - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = offset >> 8; r6xx_emit_reloc(blit, bo); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (SQ_PGM_CF_OFFSET_FS - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (SQ_PGM_RESOURCES_FS - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = SQ_PGM_RESOURCES_FS__NUM_GPRS(ngprs) | SQ_PGM_RESOURCES_FS__STACK_SIZE(stack_size); if (blit->cdw != cdw) { fprintf(stderr, "%s %d cdw missmatch expected %d got %d\n", __func__, __LINE__, cdw, blit->cdw); return -EFBIG; } return 0; } int r6xx_vs_setup(struct r6xx_blit *blit, struct ctx_bo *bo, unsigned offset, unsigned ngprs, unsigned stack_size, unsigned cs_export_count) { unsigned cdw = blit->cdw + 17; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (SQ_PGM_START_VS - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = offset >> 8; r6xx_emit_reloc(blit, bo); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (SQ_PGM_CF_OFFSET_VS - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (SQ_PGM_RESOURCES_VS - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = SQ_PGM_RESOURCES_VS__NUM_GPRS(ngprs) | SQ_PGM_RESOURCES_VS__STACK_SIZE(stack_size) | SQ_PGM_RESOURCES_VS__UNCACHED_FIRST_INST(1); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (SQ_PGM_CF_OFFSET_VS - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; /* Interpolator setup */ blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (SPI_VS_OUT_CONFIG - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT(cs_export_count); if (blit->cdw != cdw) { fprintf(stderr, "%s %d cdw missmatch expected %d got %d\n", __func__, __LINE__, cdw, blit->cdw); return -EFBIG; } return 0; } void r6xx_ps_setup(struct r6xx_blit *blit, struct ctx_bo *bo, unsigned offset, unsigned ngprs, unsigned stack_size, unsigned export_mode, unsigned num_interp) { blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (SQ_PGM_START_PS - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = offset >> 8; r6xx_emit_reloc(blit, bo); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (SQ_PGM_CF_OFFSET_PS - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (SQ_PGM_RESOURCES_PS - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = SQ_PGM_RESOURCES_PS__NUM_GPRS(ngprs) | SQ_PGM_RESOURCES_PS__STACK_SIZE(stack_size) | SQ_PGM_RESOURCES_PS__UNCACHED_FIRST_INST(1); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (SQ_PGM_CF_OFFSET_PS - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (SQ_PGM_EXPORTS_PS - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = SQ_PGM_EXPORTS_PS__EXPORT_MODE(export_mode); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 4); blit->cs[blit->cdw++] = (SPI_PS_IN_CONTROL_0 - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = SPI_PS_IN_CONTROL_0__NUM_INTERP(num_interp); blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 3); blit->cs[blit->cdw++] = (SPI_PS_INPUT_CNTL_0 - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = 0; } int r6xx_set_alu_consts(struct r6xx_blit *blit, unsigned id, unsigned count, float *cst) { unsigned cdw = blit->cdw + count * 4 + 2; unsigned i; blit->cs[blit->cdw++] = PKT3(IT_SET_ALU_CONST, count * 4 + 1); blit->cs[blit->cdw++] = id * 4; for (i = 0; i < count * 4; i++) { blit->cs[blit->cdw++] = fui(cst[i]); } if (blit->cdw != cdw) { fprintf(stderr, "%s %d cdw missmatch expected %d got %d\n", __func__, __LINE__, cdw, blit->cdw); return -EFBIG; } return 0; } void r6xx_set_default_sampler(struct r6xx_blit *blit, unsigned id) { blit->cs[blit->cdw++] = PKT3(IT_SET_SAMPLER, 4); blit->cs[blit->cdw++] = id * 3; blit->cs[blit->cdw++] = SQ_TEX_SAMPLER_WORD0_0__CLAMP_X(SQ_TEX_CLAMP_LAST_TEXEL) | SQ_TEX_SAMPLER_WORD0_0__CLAMP_Y(SQ_TEX_CLAMP_LAST_TEXEL) | SQ_TEX_SAMPLER_WORD0_0__CLAMP_Z(SQ_TEX_WRAP) | SQ_TEX_SAMPLER_WORD0_0__XY_MAG_FILTER(SQ_TEX_XY_FILTER_POINT) | SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER(SQ_TEX_XY_FILTER_POINT) | SQ_TEX_SAMPLER_WORD0_0__Z_FILTER(SQ_TEX_Z_FILTER_NONE) | SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER(SQ_TEX_Z_FILTER_NONE) | SQ_TEX_SAMPLER_WORD0_0__BORDER_COLOR_TYPE(0); blit->cs[blit->cdw++] = SQ_TEX_SAMPLER_WORD1_0__MIN_LOD(0) | SQ_TEX_SAMPLER_WORD1_0__MAX_LOD(0) | SQ_TEX_SAMPLER_WORD1_0__MAX_LOD(0) | SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS(0); blit->cs[blit->cdw++] = SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_SEC(0) | SQ_TEX_SAMPLER_WORD2_0__MC_COORD_TRUNCATE(1) | SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA(0) | SQ_TEX_SAMPLER_WORD2_0__HIGH_PRECISION_FILTER(0) | SQ_TEX_SAMPLER_WORD2_0__TYPE(0); } void r6xx_set_tex_resource(struct r6xx_blit *blit, unsigned id, struct ctx_bo *bo) { blit->cs[blit->cdw++] = PKT3(IT_SET_RESOURCE, 8); blit->cs[blit->cdw++] = id * 7; blit->cs[blit->cdw++] = SQ_TEX_RESOURCE_WORD0_0__DIM(SQ_TEX_DIM_2D) | SQ_TEX_RESOURCE_WORD0_0__TILE_MODE(bo->hw_tile) | SQ_TEX_RESOURCE_WORD0_0__PITCH((bo->pitch >> 3) - 1) | SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH(bo->w - 1); blit->cs[blit->cdw++] = SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT(bo->hw_format) | SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT(bo->h - 1); blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = SQ_TEX_RESOURCE_WORD4_0__REQUEST_SIZE(1) | SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X(SQ_SEL_X) | SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y(SQ_SEL_Y) | SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z(SQ_SEL_Z) | SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W(SQ_SEL_W); blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = SQ_VTX_CONSTANT_WORD6_0__TYPE(SQ_TEX_VTX_VALID_TEXTURE); r6xx_emit_reloc(blit, bo); r6xx_emit_reloc(blit, bo); } int r6xx_set_vtx_resource(struct r6xx_blit *blit, unsigned id, struct r6xx_vbo *vbo) { unsigned cdw = blit->cdw + 11; blit->cs[blit->cdw++] = PKT3(IT_SET_RESOURCE, 8); blit->cs[blit->cdw++] = id * 7; blit->cs[blit->cdw++] = vbo->offset; blit->cs[blit->cdw++] = vbo->ndw * 4; blit->cs[blit->cdw++] = SQ_VTX_CONSTANT_WORD2_0__STRIDE(vbo->stride) | SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT(vbo->data_format) | SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL(vbo->num_format_all) | SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL(vbo->format_comp_all) | SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL(vbo->srf_mode_all) | SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP(vbo->endian_swap); blit->cs[blit->cdw++] = SQ_VTX_CONSTANT_WORD3_0__MEM_REQUEST_SIZE(vbo->mem_request_size); blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = SQ_VTX_CONSTANT_WORD6_0__TYPE(SQ_TEX_VTX_VALID_BUFFER); r6xx_emit_reloc(blit, vbo->bo); if (blit->cdw != cdw) { fprintf(stderr, "%s %d cdw missmatch expected %d got %d\n", __func__, __LINE__, cdw, blit->cdw); return -EFBIG; } return 0; } int r6xx_draw_auto(struct r6xx_blit *blit, struct r6xx_draw *draw) { unsigned cdw = blit->cdw + 10; blit->cs[blit->cdw++] = PKT3(IT_SET_CONFIG_REG, 2); blit->cs[blit->cdw++] = (VGT_PRIMITIVE_TYPE - SET_CONFIG_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = draw->primitive_type; blit->cs[blit->cdw++] = PKT3(IT_INDEX_TYPE, 1); blit->cs[blit->cdw++] = draw->index_type; blit->cs[blit->cdw++] = PKT3(IT_NUM_INSTANCES, 1); blit->cs[blit->cdw++] = draw->num_instances; blit->cs[blit->cdw++] = PKT3(IT_DRAW_INDEX_AUTO, 2); blit->cs[blit->cdw++] = draw->num_indices; blit->cs[blit->cdw++] = draw->vgt_draw_initiator; if (blit->cdw != cdw) { fprintf(stderr, "%s %d cdw missmatch expected %d got %d\n", __func__, __LINE__, cdw, blit->cdw); return -EFBIG; } return 0; } int r6xx_disable_depth(struct r6xx_blit *blit) { unsigned cdw = blit->cdw + 6; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (DB_DEPTH_INFO - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (DB_DEPTH_CONTROL - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; if (blit->cdw != cdw) { fprintf(stderr, "%s %d cdw missmatch expected %d got %d\n", __func__, __LINE__, cdw, blit->cdw); return -EFBIG; } return 0; } int r6xx_surface_sync(struct r6xx_blit *blit, struct ctx_bo *bo, unsigned sync_type) { unsigned cdw = blit->cdw + 5; unsigned size = 0xffffffff; if (bo) { size = (bo->size + 255) >> 8; cdw += 2; } blit->cs[blit->cdw++] = PKT3(IT_SURFACE_SYNC, 4); blit->cs[blit->cdw++] = sync_type; blit->cs[blit->cdw++] = size; blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = 10; if (bo) { r6xx_emit_reloc(blit, bo); } if (blit->cdw != cdw) { fprintf(stderr, "%s %d cdw missmatch expected %d got %d\n", __func__, __LINE__, cdw, blit->cdw); return -EFBIG; } return 0; } int r6xx_event(struct r6xx_blit *blit, unsigned event_iniator) { unsigned cdw = blit->cdw + 2; blit->cs[blit->cdw++] = PKT3(IT_EVENT_WRITE, 1); blit->cs[blit->cdw++] = event_iniator; if (blit->cdw != cdw) { fprintf(stderr, "%s %d cdw missmatch expected %d got %d\n", __func__, __LINE__, cdw, blit->cdw); return -EFBIG; } return 0; } int r6xx_set_default_state(struct r6xx_blit *blit) { struct r6xx_sq_conf *sq_conf = &blit->sq_conf; unsigned cdw = blit->cdw + 234, i; if (blit->ctx->family < CHIP_RV770) { blit->cs[blit->cdw++] = PKT3(IT_START_3D_CMDBUF, 1); blit->cs[blit->cdw++] = 0; } blit->cs[blit->cdw++] = PKT3(IT_CONTEXT_CONTROL, 2); blit->cs[blit->cdw++] = 0x80000000; blit->cs[blit->cdw++] = 0x80000000; blit->cs[blit->cdw++] = PKT3(IT_SET_CONFIG_REG, 7); blit->cs[blit->cdw++] = (SQ_CONFIG - SET_CONFIG_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = sq_conf->sq_config; blit->cs[blit->cdw++] = SQ_GPR_RESOURCE_MGMT_1__NUM_PS_GPRS(sq_conf->num_ps_gprs) | SQ_GPR_RESOURCE_MGMT_1__NUM_VS_GPRS(sq_conf->num_vs_gprs) | SQ_GPR_RESOURCE_MGMT_1__NUM_CLAUSE_TEMP_GPRS(sq_conf->num_temp_gprs); blit->cs[blit->cdw++] = SQ_GPR_RESOURCE_MGMT_2__NUM_GS_GPRS(sq_conf->num_gs_gprs) | SQ_GPR_RESOURCE_MGMT_2__NUM_ES_GPRS(sq_conf->num_es_gprs); blit->cs[blit->cdw++] = SQ_THREAD_RESOURCE_MGMT__NUM_PS_THREADS(sq_conf->num_ps_threads) | SQ_THREAD_RESOURCE_MGMT__NUM_VS_THREADS(sq_conf->num_vs_threads) | SQ_THREAD_RESOURCE_MGMT__NUM_GS_THREADS(sq_conf->num_gs_threads) | SQ_THREAD_RESOURCE_MGMT__NUM_ES_THREADS(sq_conf->num_es_threads); blit->cs[blit->cdw++] = SQ_STACK_RESOURCE_MGMT_1__NUM_PS_STACK_ENTRIES(sq_conf->num_ps_stack_entries) | SQ_STACK_RESOURCE_MGMT_1__NUM_VS_STACK_ENTRIES(sq_conf->num_vs_stack_entries); blit->cs[blit->cdw++] = SQ_STACK_RESOURCE_MGMT_2__NUM_GS_STACK_ENTRIES(sq_conf->num_gs_stack_entries) | SQ_STACK_RESOURCE_MGMT_2__NUM_ES_STACK_ENTRIES(sq_conf->num_es_stack_entries); blit->cs[blit->cdw++] = PKT3(IT_SET_CONFIG_REG, 2); blit->cs[blit->cdw++] = (VC_ENHANCE - SET_CONFIG_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = PKT3(IT_SET_CONFIG_REG, 2); blit->cs[blit->cdw++] = (DB_DEBUG - SET_CONFIG_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0x80000000; blit->cs[blit->cdw++] = PKT3(IT_SET_CONFIG_REG, 2); blit->cs[blit->cdw++] = (DB_WATERMARKS - SET_CONFIG_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = DB_WATERMARKS__DEPTH_FREE(4) | DB_WATERMARKS__DEPTH_FLUSH(16) | DB_WATERMARKS__FORCE_SUMMARIZE(0) | DB_WATERMARKS__DEPTH_PENDING_FREE(4) | DB_WATERMARKS__DEPTH_CACHELINE_FREE(16); blit->cs[blit->cdw++] = PKT3(IT_SET_CTL_CONST, 3); blit->cs[blit->cdw++] = (SQ_VTX_BASE_VTX_LOC - SET_CTL_CONST__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 10); blit->cs[blit->cdw++] = (SQ_ESGS_RING_ITEMSIZE - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; // SQ_ESGS_RING_ITEMSIZE blit->cs[blit->cdw++] = 0; // SQ_GSVS_RING_ITEMSIZE blit->cs[blit->cdw++] = 0; // SQ_ESTMP_RING_ITEMSIZE blit->cs[blit->cdw++] = 0; // SQ_GSTMP_RING_ITEMSIZE blit->cs[blit->cdw++] = 0; // SQ_VSTMP_RING_ITEMSIZE blit->cs[blit->cdw++] = 0; // SQ_PSTMP_RING_ITEMSIZE blit->cs[blit->cdw++] = 0; // SQ_FBUF_RING_ITEMSIZE blit->cs[blit->cdw++] = 0; // SQ_REDUC_RING_ITEMSIZE blit->cs[blit->cdw++] = 0; // SQ_GS_VERT_ITEMSIZE blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 5); blit->cs[blit->cdw++] = (CB_CLRCMP_CONTROL - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = CB_CLRCMP_CONTROL__CLRCMP_FCN_SEL(CLRCMP_SEL_SRC); blit->cs[blit->cdw++] = 0; // CB_CLRCMP_SRC blit->cs[blit->cdw++] = 0; // CB_CLRCMP_DST blit->cs[blit->cdw++] = 0; // CB_CLRCMP_MSK blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (CB_SHADER_MASK - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = CB_SHADER_MASK__OUTPUT0_ENABLE(0xf); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 6); blit->cs[blit->cdw++] = (SX_ALPHA_TEST_CONTROL - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; // SX_ALPHA_TEST_CONTROL blit->cs[blit->cdw++] = 0; // CB_BLEND_RED blit->cs[blit->cdw++] = 0; // CB_BLEND_GREEN blit->cs[blit->cdw++] = 0; // CB_BLEND_BLUE blit->cs[blit->cdw++] = 0; // CB_BLEND_ALPHA blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (PA_SC_WINDOW_OFFSET - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET(0) | PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET(0); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (PA_SC_CLIPRECT_RULE - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = PA_SC_CLIPRECT_RULE__CLIP_RULE(0xfffff); /* clip boolean is set to always visible -> doesn't matter */ for (i = 0; i < PA_SC_CLIPRECT_0_TL__NUM; i++) { r6xx_set_clip_rect(blit, i, 0, 0, 8192, 8192); } for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL__NUM; i++) { r6xx_set_vport_scissor(blit, i, 0, 0, 8192, 8192); } blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 3); blit->cs[blit->cdw++] = (PA_SC_MPASS_PS_CNTL - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = PA_SC_MODE_CNTL__FORCE_EOV_CNTDWN_ENABLE(1) | PA_SC_MODE_CNTL__FORCE_EOV_REZ_ENABLE(1) | PA_SC_MODE_CNTL__TILE_COVER_DISABLE(0) | PA_SC_MODE_CNTL__TILE_COVER_NO_SCISSOR(1) | 0x00500000; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 10); blit->cs[blit->cdw++] = (PA_SC_LINE_CNTL - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; // PA_SC_LINE_CNTL blit->cs[blit->cdw++] = 0; // PA_SC_AA_CONFIG blit->cs[blit->cdw++] = PA_SU_VTX_CNTL__ROUND_MODE(X_TRUNCATE) | PA_SU_VTX_CNTL__PIX_CENTER(1) | /* round to even, fixed point 1/256 */ PA_SU_VTX_CNTL__QUANT_MODE(X_1_256TH); blit->cs[blit->cdw++] = fui(1.0); // PA_CL_GB_VERT_CLIP_ADJ blit->cs[blit->cdw++] = fui(1.0); // PA_CL_GB_VERT_DISC_ADJ blit->cs[blit->cdw++] = fui(1.0); // PA_CL_GB_HORZ_CLIP_ADJ blit->cs[blit->cdw++] = fui(1.0); // PA_CL_GB_HORZ_DISC_ADJ blit->cs[blit->cdw++] = 0; // PA_SC_AA_SAMPLE_LOCS_MCTX blit->cs[blit->cdw++] = 0; // PA_SC_AA_SAMPLE_LOCS_8S_WD1_M blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (PA_SC_AA_MASK - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0xFFFFFFFF; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 6); blit->cs[blit->cdw++] = (PA_CL_CLIP_CNTL - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = PA_CL_CLIP_CNTL__CLIP_DISABLE(1) | PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE(0) | PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE(0); blit->cs[blit->cdw++] = PA_SU_SC_MODE_CNTL__FACE(1); blit->cs[blit->cdw++] = PA_CL_VTE_CNTL__VTX_XY_FMT(1) | PA_CL_VTE_CNTL__VTX_Z_FMT(0) | PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA(1) | PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA(1); blit->cs[blit->cdw++] = 0; // PA_CL_VS_OUT_CNTL blit->cs[blit->cdw++] = 0; // PA_CL_NANINF_CNTL blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (PA_CL_VPORT_ZSCALE_0 - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = fui(1.0); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (PA_CL_VPORT_ZOFFSET_0 - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = fui(0.0); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 7); blit->cs[blit->cdw++] = (PA_SU_POLY_OFFSET_DB_FMT_CNTL - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0xe8; // PA_SU_POLY_OFFSET_DB_FMT_CNTL blit->cs[blit->cdw++] = 0; // PA_SU_POLY_OFFSET_CLAMP blit->cs[blit->cdw++] = 0; // PA_SU_POLY_OFFSET_FRONT_SCALE blit->cs[blit->cdw++] = 0; // PA_SU_POLY_OFFSET_FRONT_OFFSET blit->cs[blit->cdw++] = 0; // PA_SU_POLY_OFFSET_BACK_SCALE blit->cs[blit->cdw++] = 0; // PA_SU_POLY_OFFSET_BACK_OFFSET /* default Interpolator setup */ blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (SPI_VS_OUT_ID_0 - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = SPI_VS_OUT_ID_0__SEMANTIC_0(0) | SPI_VS_OUT_ID_0__SEMANTIC_1(1); /* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */ blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 3); blit->cs[blit->cdw++] = (SPI_PS_INPUT_CNTL_0 - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = SPI_PS_INPUT_CNTL_0__SEMANTIC(0) | SPI_PS_INPUT_CNTL_0__DEFAULT_VAL(0x01) | SPI_PS_INPUT_CNTL_0__SEL_CENTROID(1); /* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */ blit->cs[blit->cdw++] = SPI_PS_INPUT_CNTL_0__SEMANTIC(1) | SPI_PS_INPUT_CNTL_0__DEFAULT_VAL(0x01) | SPI_PS_INPUT_CNTL_0__SEL_CENTROID(1); blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 5); blit->cs[blit->cdw++] = (SPI_INPUT_Z - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; // SPI_INPUT_Z blit->cs[blit->cdw++] = 0; // SPI_FOG_CNTL blit->cs[blit->cdw++] = 0; // SPI_FOG_FUNC_SCALE blit->cs[blit->cdw++] = 0; // SPI_FOG_FUNC_BIAS /* VGT */ blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 5); blit->cs[blit->cdw++] = (VGT_MAX_VTX_INDX - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0xffffff; // VGT_MAX_VTX_INDX blit->cs[blit->cdw++] = 0; // VGT_MIN_VTX_INDX blit->cs[blit->cdw++] = 0; // VGT_INDX_OFFSET blit->cs[blit->cdw++] = 0; // VGT_MULTI_PRIM_IB_RESET_INDX blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (VGT_PRIMITIVEID_EN - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (VGT_MULTI_PRIM_IB_RESET_EN - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 3); blit->cs[blit->cdw++] = (VGT_INSTANCE_STEP_RATE_0 - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; // VGT_INSTANCE_STEP_RATE_0 blit->cs[blit->cdw++] = 0; // VGT_INSTANCE_STEP_RATE_1 blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 18); blit->cs[blit->cdw++] = (PA_SU_POINT_SIZE - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; // PA_SU_POINT_SIZE blit->cs[blit->cdw++] = 0; // PA_SU_POINT_MINMAX blit->cs[blit->cdw++] = PA_SU_LINE_CNTL__WIDTH(8); blit->cs[blit->cdw++] = 0; // PA_SC_LINE_STIPPLE blit->cs[blit->cdw++] = 0; // VGT_OUTPUT_PATH_CNTL blit->cs[blit->cdw++] = 0; // VGT_HOS_CNTL blit->cs[blit->cdw++] = 0; // VGT_HOS_MAX_TESS_LEVEL blit->cs[blit->cdw++] = 0; // VGT_HOS_MIN_TESS_LEVEL blit->cs[blit->cdw++] = 0; // VGT_HOS_REUSE_DEPTH blit->cs[blit->cdw++] = 0; // VGT_GROUP_PRIM_TYPE blit->cs[blit->cdw++] = 0; // VGT_GROUP_FIRST_DECR blit->cs[blit->cdw++] = 0; // VGT_GROUP_DECR blit->cs[blit->cdw++] = 0; // VGT_GROUP_VECT_0_CNTL blit->cs[blit->cdw++] = 0; // VGT_GROUP_VECT_1_CNTL blit->cs[blit->cdw++] = 0; // VGT_GROUP_VECT_0_FMT_CNTL blit->cs[blit->cdw++] = 0; // VGT_GROUP_VECT_1_FMT_CNTL blit->cs[blit->cdw++] = 0; // VGT_GS_MODE blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 4); blit->cs[blit->cdw++] = (VGT_STRMOUT_EN - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; // VGT_STRMOUT_EN blit->cs[blit->cdw++] = VGT_REUSE_OFF__REUSE_OFF(1); // VGT_REUSE_OFF blit->cs[blit->cdw++] = 0; // VGT_VTX_CNT_EN blit->cs[blit->cdw++] = PKT3(IT_SET_CONTEXT_REG, 2); blit->cs[blit->cdw++] = (VGT_STRMOUT_BUFFER_EN - SET_CONTEXT_REG__OFFSET) >> 2; blit->cs[blit->cdw++] = 0; if (blit->cdw != cdw) { fprintf(stderr, "%s %d cdw missmatch expected %d got %d\n", __func__, __LINE__, cdw, blit->cdw); return -EFBIG; } return 0; } /* solid vs */ unsigned r6xx_solid_vs(uint32_t *shader) { unsigned i = 0; /* 0 */ shader[i++] = SQ_CF_WORD0__ADDR(4); shader[i++] = SQ_CF_WORD1__CF_INST(SQ_CF_INST_VTX) | SQ_CF_WORD1__POP_COUNT(0) | SQ_CF_WORD1__CF_CONST(0) | SQ_CF_WORD1__COND(SQ_CF_COND_ACTIVE) | SQ_CF_WORD1__COUNT(0) | SQ_CF_WORD1__VALID_PIXEL_MODE(0) | SQ_CF_WORD1__END_OF_PROGRAM (0) | SQ_CF_WORD1__WHOLE_QUAD_MODE(0) | SQ_CF_WORD1__BARRIER(0); /* 1 */ shader[i++] = SQ_CF_ALLOC_EXPORT_WORD0__ARRAY_BASE(SQ_EXPORT_POS0) | SQ_CF_ALLOC_EXPORT_WORD0__TYPE(SQ_EXPORT_POS) | SQ_CF_ALLOC_EXPORT_WORD0__RW_GPR(0) | SQ_CF_ALLOC_EXPORT_WORD0__RW_REL(0) | SQ_CF_ALLOC_EXPORT_WORD0__INDEX_GPR(0) | SQ_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE(3); shader[i++] = SQ_CF_ALLOC_EXPORT_WORD1__CF_INST(SQ_CF_INST_EXPORT_DONE) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_X(SQ_SEL_X) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Y(SQ_SEL_Y) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Z(SQ_SEL_0) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_W(SQ_SEL_1) | SQ_CF_ALLOC_EXPORT_WORD1__BURST_COUNT(0) | SQ_CF_ALLOC_EXPORT_WORD1__END_OF_PROGRAM(0) | SQ_CF_ALLOC_EXPORT_WORD1__WHOLE_QUAD_MODE(0) | SQ_CF_ALLOC_EXPORT_WORD1__BARRIER(1); /* 2 */ shader[i++] = SQ_CF_ALLOC_EXPORT_WORD0__ARRAY_BASE(SQ_EXPORT_PARAM0) | SQ_CF_ALLOC_EXPORT_WORD0__TYPE(SQ_EXPORT_PARAM) | SQ_CF_ALLOC_EXPORT_WORD0__RW_GPR(0) | SQ_CF_ALLOC_EXPORT_WORD0__RW_REL(0) | SQ_CF_ALLOC_EXPORT_WORD0__INDEX_GPR(0) | SQ_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE(0); shader[i++] = SQ_CF_ALLOC_EXPORT_WORD1__CF_INST(SQ_CF_INST_EXPORT_DONE) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_X(SQ_SEL_Z) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Y(SQ_SEL_W) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Z(SQ_SEL_0) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_W(SQ_SEL_0) | SQ_CF_ALLOC_EXPORT_WORD1__BURST_COUNT(0) | SQ_CF_ALLOC_EXPORT_WORD1__END_OF_PROGRAM(1) | SQ_CF_ALLOC_EXPORT_WORD1__WHOLE_QUAD_MODE(0) | SQ_CF_ALLOC_EXPORT_WORD1__BARRIER(0); /* 3 */ shader[i++] = 0x00000000; shader[i++] = 0x00000000; /* 4/5 */ shader[i++] = SQ_VTX_WORD0__VTX_INST(SQ_VTX_INST_FETCH) | SQ_VTX_WORD0__FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA) | SQ_VTX_WORD0__FETCH_WHOLE_QUAD(0) | SQ_VTX_WORD0__BUFFER_ID(0) | SQ_VTX_WORD0__SRC_GPR(0) | SQ_VTX_WORD0__SRC_REL(0) | SQ_VTX_WORD0__SRC_SEL_X(SQ_SEL_X) | SQ_VTX_WORD0__MEGA_FETCH_COUNT(16); shader[i++] = SQ_VTX_WORD1_GPR__DST_GPR(0) | SQ_VTX_WORD1_GPR__DST_REL(0) | SQ_VTX_WORD1__DST_SEL_X(SQ_SEL_X) | SQ_VTX_WORD1__DST_SEL_Y(SQ_SEL_Y) | SQ_VTX_WORD1__DST_SEL_Z(SQ_SEL_Z) | SQ_VTX_WORD1__DST_SEL_W(SQ_SEL_W) | SQ_VTX_WORD1__USE_CONST_FIELDS(1) | SQ_VTX_WORD1__DATA_FORMAT(FMT_32_32_32_32_FLOAT) | SQ_VTX_WORD1__NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED) | SQ_VTX_WORD1__FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED) | SQ_VTX_WORD1__SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE); shader[i++] = SQ_VTX_WORD2__OFFSET(0) | SQ_VTX_WORD2__ENDIAN_SWAP(SQ_ENDIAN_NONE) | SQ_VTX_WORD2__CONST_BUF_NO_STRIDE(0) | SQ_VTX_WORD2__MEGA_FETCH(1); shader[i++] = 0x0; return i; } unsigned r6xx_copy_vs(uint32_t *shader) { unsigned i = 0; /* 0 */ shader[i++] = SQ_CF_WORD0__ADDR(4); shader[i++] = SQ_CF_WORD1__CF_INST(SQ_CF_INST_VTX) | SQ_CF_WORD1__POP_COUNT(0) | SQ_CF_WORD1__CF_CONST(0) | SQ_CF_WORD1__COND(SQ_CF_COND_ACTIVE) | SQ_CF_WORD1__COUNT(0) | SQ_CF_WORD1__VALID_PIXEL_MODE(0) | SQ_CF_WORD1__END_OF_PROGRAM (0) | SQ_CF_WORD1__WHOLE_QUAD_MODE(0) | SQ_CF_WORD1__BARRIER(0); /* 1 */ shader[i++] = SQ_CF_ALLOC_EXPORT_WORD0__ARRAY_BASE(SQ_EXPORT_POS0) | SQ_CF_ALLOC_EXPORT_WORD0__TYPE(SQ_EXPORT_POS) | SQ_CF_ALLOC_EXPORT_WORD0__RW_GPR(0) | SQ_CF_ALLOC_EXPORT_WORD0__RW_REL(0) | SQ_CF_ALLOC_EXPORT_WORD0__INDEX_GPR(0) | SQ_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE(3); shader[i++] = SQ_CF_ALLOC_EXPORT_WORD1__CF_INST(SQ_CF_INST_EXPORT_DONE) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_X(SQ_SEL_X) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Y(SQ_SEL_Y) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Z(SQ_SEL_0) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_W(SQ_SEL_1) | SQ_CF_ALLOC_EXPORT_WORD1__BURST_COUNT(0) | SQ_CF_ALLOC_EXPORT_WORD1__END_OF_PROGRAM(0) | SQ_CF_ALLOC_EXPORT_WORD1__WHOLE_QUAD_MODE(0) | SQ_CF_ALLOC_EXPORT_WORD1__BARRIER(1); /* 2 */ shader[i++] = SQ_CF_ALLOC_EXPORT_WORD0__ARRAY_BASE(SQ_EXPORT_PARAM0) | SQ_CF_ALLOC_EXPORT_WORD0__TYPE(SQ_EXPORT_PARAM) | SQ_CF_ALLOC_EXPORT_WORD0__RW_GPR(0) | SQ_CF_ALLOC_EXPORT_WORD0__RW_REL(0) | SQ_CF_ALLOC_EXPORT_WORD0__INDEX_GPR(0) | SQ_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE(0); shader[i++] = SQ_CF_ALLOC_EXPORT_WORD1__CF_INST(SQ_CF_INST_EXPORT_DONE) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_X(SQ_SEL_Z) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Y(SQ_SEL_W) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Z(SQ_SEL_0) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_W(SQ_SEL_0) | SQ_CF_ALLOC_EXPORT_WORD1__BURST_COUNT(0) | SQ_CF_ALLOC_EXPORT_WORD1__END_OF_PROGRAM(1) | SQ_CF_ALLOC_EXPORT_WORD1__WHOLE_QUAD_MODE(0) | SQ_CF_ALLOC_EXPORT_WORD1__BARRIER(0); /* 3 */ shader[i++] = 0x00000000; shader[i++] = 0x00000000; /* 4/5 */ shader[i++] = SQ_VTX_WORD0__VTX_INST(SQ_VTX_INST_FETCH) | SQ_VTX_WORD0__FETCH_TYPE(SQ_VTX_FETCH_VERTEX_DATA) | SQ_VTX_WORD0__FETCH_WHOLE_QUAD(0) | SQ_VTX_WORD0__BUFFER_ID(0) | SQ_VTX_WORD0__SRC_GPR(0) | SQ_VTX_WORD0__SRC_REL(0) | SQ_VTX_WORD0__SRC_SEL_X(SQ_SEL_X) | SQ_VTX_WORD0__MEGA_FETCH_COUNT(16); shader[i++] = SQ_VTX_WORD1_GPR__DST_GPR(0) | SQ_VTX_WORD1_GPR__DST_REL(0) | SQ_VTX_WORD1__DST_SEL_X(SQ_SEL_X) | SQ_VTX_WORD1__DST_SEL_Y(SQ_SEL_Y) | SQ_VTX_WORD1__DST_SEL_Z(SQ_SEL_Z) | SQ_VTX_WORD1__DST_SEL_W(SQ_SEL_W) | SQ_VTX_WORD1__USE_CONST_FIELDS(1) | SQ_VTX_WORD1__DATA_FORMAT(FMT_32_32_32_32_FLOAT) | SQ_VTX_WORD1__NUM_FORMAT_ALL(SQ_NUM_FORMAT_SCALED) | SQ_VTX_WORD1__FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED) | SQ_VTX_WORD1__SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE); shader[i++] = SQ_VTX_WORD2__OFFSET(0) | SQ_VTX_WORD2__ENDIAN_SWAP(SQ_ENDIAN_NONE) | SQ_VTX_WORD2__CONST_BUF_NO_STRIDE(0) | SQ_VTX_WORD2__MEGA_FETCH(1); shader[i++] = 0x0; return i; } /* solid ps */ unsigned r6xx_solid_ps(uint32_t* shader) { unsigned i = 0; /* 0 */ shader[i++] = SQ_CF_ALU_WORD0__ADDR(2) | SQ_CF_ALU_WORD0__KCACHE_BANK0(0) | SQ_CF_ALU_WORD0__KCACHE_BANK1(0) | SQ_CF_ALU_WORD0__KCACHE_MODE0(SQ_CF_KCACHE_NOP); shader[i++] = SQ_CF_ALU_WORD1__CF_INST(SQ_CF_INST_ALU) | SQ_CF_ALU_WORD1__COUNT(3) | SQ_CF_ALU_WORD1__KCACHE_MODE1(SQ_CF_KCACHE_NOP) | SQ_CF_ALU_WORD1__KCACHE_ADDR0(0) | SQ_CF_ALU_WORD1__KCACHE_ADDR1(0) | SQ_CF_ALU_WORD1__WHOLE_QUAD_MODE(0) | SQ_CF_ALU_WORD1__BARRIER(0); /* 1 */ shader[i++] = SQ_CF_ALLOC_EXPORT_WORD0__ARRAY_BASE(SQ_EXPORT_CB0) | SQ_CF_ALLOC_EXPORT_WORD0__TYPE(SQ_EXPORT_PIXEL) | SQ_CF_ALLOC_EXPORT_WORD0__RW_GPR(0) | SQ_CF_ALLOC_EXPORT_WORD0__RW_REL(0) | SQ_CF_ALLOC_EXPORT_WORD0__INDEX_GPR(0) | SQ_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE(0); shader[i++] = SQ_CF_ALLOC_EXPORT_WORD1__CF_INST(SQ_CF_INST_EXPORT_DONE) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_X(SQ_SEL_X) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Y(SQ_SEL_Y) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Z(SQ_SEL_Z) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_W(SQ_SEL_W) | SQ_CF_ALLOC_EXPORT_WORD1__BURST_COUNT(0) | SQ_CF_ALLOC_EXPORT_WORD1__END_OF_PROGRAM(1) | SQ_CF_ALLOC_EXPORT_WORD1__WHOLE_QUAD_MODE(0) | SQ_CF_ALLOC_EXPORT_WORD1__BARRIER(1); /* 2 */ shader[i++] = SQ_ALU_WORD0__SRC0_SEL(SQ_ALU_CFILE_0) | SQ_ALU_WORD0__SRC0_REL(0) | SQ_ALU_WORD0__SRC0_CHAN(SQ_CHAN_X) | SQ_ALU_WORD0__SRC0_NEG(0) | SQ_ALU_WORD0__SRC1_SEL(0) | SQ_ALU_WORD0__SRC1_REL(0) | SQ_ALU_WORD0__SRC1_CHAN(SQ_CHAN_X) | SQ_ALU_WORD0__SRC1_NEG(0) | SQ_ALU_WORD0__INDEX_MODE(0) | SQ_ALU_WORD0__PRED_SEL(SQ_PRED_SEL_OFF) | SQ_ALU_WORD0__LAST(0); shader[i++] = SQ_ALU_WORD1_OP2__ALU_INST(SQ_OP2_INST_MOV) | SQ_ALU_WORD1_OP2__SRC0_ABS(0) | SQ_ALU_WORD1_OP2__SRC1_ABS(0) | SQ_ALU_WORD1_OP2__UPDATE_EXECUTE_MASK(0) | SQ_ALU_WORD1_OP2__UPDATE_PRED(0) | SQ_ALU_WORD1_OP2__WRITE_MASK(1) | SQ_ALU_WORD1_OP2__OMOD(SQ_ALU_OMOD_OFF) | SQ_ALU_WORD1__BANK_SWIZZLE(SQ_ALU_VEC_012) | SQ_ALU_WORD1__DST_GPR(0) | SQ_ALU_WORD1__DST_REL(0) | SQ_ALU_WORD1__DST_CHAN(SQ_CHAN_X) | SQ_ALU_WORD1__CLAMP(1); /* 3 */ shader[i++] = SQ_ALU_WORD0__SRC0_SEL(SQ_ALU_CFILE_0) | SQ_ALU_WORD0__SRC0_REL(0) | SQ_ALU_WORD0__SRC0_CHAN(SQ_CHAN_Y) | SQ_ALU_WORD0__SRC0_NEG(0) | SQ_ALU_WORD0__SRC1_SEL(0) | SQ_ALU_WORD0__SRC1_REL(0) | SQ_ALU_WORD0__SRC1_CHAN(SQ_CHAN_Y) | SQ_ALU_WORD0__SRC1_NEG(0) | SQ_ALU_WORD0__INDEX_MODE(0) | SQ_ALU_WORD0__PRED_SEL(SQ_PRED_SEL_OFF) | SQ_ALU_WORD0__LAST(0); shader[i++] = SQ_ALU_WORD1_OP2__ALU_INST(SQ_OP2_INST_MOV) | SQ_ALU_WORD1_OP2__SRC0_ABS(0) | SQ_ALU_WORD1_OP2__SRC1_ABS(0) | SQ_ALU_WORD1_OP2__UPDATE_EXECUTE_MASK(0) | SQ_ALU_WORD1_OP2__UPDATE_PRED(0) | SQ_ALU_WORD1_OP2__WRITE_MASK(1) | SQ_ALU_WORD1_OP2__OMOD(SQ_ALU_OMOD_OFF) | SQ_ALU_WORD1__BANK_SWIZZLE(SQ_ALU_VEC_012) | SQ_ALU_WORD1__DST_GPR(0) | SQ_ALU_WORD1__DST_REL(0) | SQ_ALU_WORD1__DST_CHAN(SQ_CHAN_Y) | SQ_ALU_WORD1__CLAMP(1); /* 4 */ shader[i++] = SQ_ALU_WORD0__SRC0_SEL(SQ_ALU_CFILE_0) | SQ_ALU_WORD0__SRC0_REL(0) | SQ_ALU_WORD0__SRC0_CHAN(SQ_CHAN_Z) | SQ_ALU_WORD0__SRC0_NEG(0) | SQ_ALU_WORD0__SRC1_SEL(0) | SQ_ALU_WORD0__SRC1_REL(0) | SQ_ALU_WORD0__SRC1_CHAN(SQ_CHAN_Z) | SQ_ALU_WORD0__SRC1_NEG(0) | SQ_ALU_WORD0__INDEX_MODE(0) | SQ_ALU_WORD0__PRED_SEL(SQ_PRED_SEL_OFF) | SQ_ALU_WORD0__LAST(0); shader[i++] = SQ_ALU_WORD1_OP2__ALU_INST(SQ_OP2_INST_MOV) | SQ_ALU_WORD1_OP2__SRC0_ABS(0) | SQ_ALU_WORD1_OP2__SRC1_ABS(0) | SQ_ALU_WORD1_OP2__UPDATE_EXECUTE_MASK(0) | SQ_ALU_WORD1_OP2__UPDATE_PRED(0) | SQ_ALU_WORD1_OP2__WRITE_MASK(1) | SQ_ALU_WORD1_OP2__OMOD(SQ_ALU_OMOD_OFF) | SQ_ALU_WORD1__BANK_SWIZZLE(SQ_ALU_VEC_012) | SQ_ALU_WORD1__DST_GPR(0) | SQ_ALU_WORD1__DST_REL(0) | SQ_ALU_WORD1__DST_CHAN(SQ_CHAN_Z) | SQ_ALU_WORD1__CLAMP(1); /* 5 */ shader[i++] = SQ_ALU_WORD0__SRC0_SEL(SQ_ALU_CFILE_0) | SQ_ALU_WORD0__SRC0_REL(0) | SQ_ALU_WORD0__SRC0_CHAN(SQ_CHAN_W) | SQ_ALU_WORD0__SRC0_NEG(0) | SQ_ALU_WORD0__SRC1_SEL(0) | SQ_ALU_WORD0__SRC1_REL(0) | SQ_ALU_WORD0__SRC1_CHAN(SQ_CHAN_W) | SQ_ALU_WORD0__SRC1_NEG(0) | SQ_ALU_WORD0__INDEX_MODE(0) | SQ_ALU_WORD0__PRED_SEL(SQ_PRED_SEL_OFF) | SQ_ALU_WORD0__LAST(1); shader[i++] = SQ_ALU_WORD1_OP2__ALU_INST(SQ_OP2_INST_MOV) | SQ_ALU_WORD1_OP2__SRC0_ABS(0) | SQ_ALU_WORD1_OP2__SRC1_ABS(0) | SQ_ALU_WORD1_OP2__UPDATE_EXECUTE_MASK(0) | SQ_ALU_WORD1_OP2__UPDATE_PRED(0) | SQ_ALU_WORD1_OP2__WRITE_MASK(1) | SQ_ALU_WORD1_OP2__OMOD(SQ_ALU_OMOD_OFF) | SQ_ALU_WORD1__BANK_SWIZZLE(SQ_ALU_VEC_012) | SQ_ALU_WORD1__DST_GPR(0) | SQ_ALU_WORD1__DST_REL(0) | SQ_ALU_WORD1__DST_CHAN(SQ_CHAN_W) | SQ_ALU_WORD1__CLAMP(1); return i; } unsigned r6xx_copy_ps(uint32_t *shader) { unsigned i = 0; /* 0 */ shader[i++] = SQ_CF_WORD0__ADDR(2); shader[i++] = SQ_CF_WORD1__CF_INST(SQ_CF_INST_TEX) | SQ_CF_WORD1__COUNT(0) | SQ_CF_WORD1__WHOLE_QUAD_MODE(0) | SQ_CF_WORD1__BARRIER(1); /* 1 */ shader[i++] = SQ_CF_ALLOC_EXPORT_WORD0__ARRAY_BASE(SQ_EXPORT_CB0) | SQ_CF_ALLOC_EXPORT_WORD0__TYPE(SQ_EXPORT_PIXEL) | SQ_CF_ALLOC_EXPORT_WORD0__RW_GPR(0) | SQ_CF_ALLOC_EXPORT_WORD0__RW_REL(0) | SQ_CF_ALLOC_EXPORT_WORD0__INDEX_GPR(0) | SQ_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE(0); shader[i++] = SQ_CF_ALLOC_EXPORT_WORD1__CF_INST(SQ_CF_INST_EXPORT_DONE) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_X(SQ_SEL_X) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Y(SQ_SEL_Y) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Z(SQ_SEL_Z) | SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_W(SQ_SEL_W) | SQ_CF_ALLOC_EXPORT_WORD1__BURST_COUNT(0) | SQ_CF_ALLOC_EXPORT_WORD1__END_OF_PROGRAM(1) | SQ_CF_ALLOC_EXPORT_WORD1__WHOLE_QUAD_MODE(0) | SQ_CF_ALLOC_EXPORT_WORD1__BARRIER(1); /* TEX INST 0 */ shader[i++] = SQ_TEX_WORD0__TEX_INST(SQ_TEX_INST_SAMPLE) | SQ_TEX_WORD0__BC_FRAC_MODE(0) | SQ_TEX_WORD0__FETCH_WHOLE_QUAD(0) | SQ_TEX_WORD0__RESOURCE_ID(0) | SQ_TEX_WORD0__SRC_GPR(0) | SQ_TEX_WORD0__SRC_REL(0); shader[i++] = SQ_TEX_WORD1__DST_GPR(0) | SQ_TEX_WORD1__DST_REL(0) | SQ_TEX_WORD1__DST_SEL_X(SQ_SEL_X) | SQ_TEX_WORD1__DST_SEL_Y(SQ_SEL_Y) | SQ_TEX_WORD1__DST_SEL_Z(SQ_SEL_Z) | SQ_TEX_WORD1__DST_SEL_W(SQ_SEL_W) | SQ_TEX_WORD1__LOD_BIAS(0) | SQ_TEX_WORD1__COORD_TYPE_X(0) | SQ_TEX_WORD1__COORD_TYPE_Y(0) | SQ_TEX_WORD1__COORD_TYPE_Z(0) | SQ_TEX_WORD1__COORD_TYPE_W(0); shader[i++] = SQ_TEX_WORD2__OFFSET_X(0) | SQ_TEX_WORD2__OFFSET_Y(0) | SQ_TEX_WORD2__OFFSET_Z(0) | SQ_TEX_WORD2__SAMPLER_ID(0) | SQ_TEX_WORD2__SRC_SEL_X(SQ_SEL_X) | SQ_TEX_WORD2__SRC_SEL_Y(SQ_SEL_Y) | SQ_TEX_WORD2__SRC_SEL_Z(SQ_SEL_0) | SQ_TEX_WORD2__SRC_SEL_W(SQ_SEL_1); shader[i++] = 0; return i; }