diff options
author | Eric Anholt <eric@anholt.net> | 2017-06-21 10:23:23 -0700 |
---|---|---|
committer | Daniel Stone <daniels@collabora.com> | 2017-06-22 10:49:00 +0100 |
commit | b9549c954e190010a79e6691983b6ae16eac83d5 (patch) | |
tree | cd914eac8412cb9741c37844d26bb5fe12cccec8 | |
parent | 7e6bf88cac315a9fa41818cf72a7b5d18a2cb1fc (diff) |
headers: Update drm_fourcc and vc4_drm.h with new VC4 tiling UAPI.
Taken from make headers_install of drm-misc-next
(34c8ea400ff6383b028f63df2453914163afc07c)
Reviewed-by: Daniel Stone <daniels@collabora.com>
-rw-r--r-- | include/drm/drm_fourcc.h | 23 | ||||
-rw-r--r-- | include/drm/vc4_drm.h | 22 |
2 files changed, 41 insertions, 4 deletions
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h index 55e30104..7586c46f 100644 --- a/include/drm/drm_fourcc.h +++ b/include/drm/drm_fourcc.h @@ -182,6 +182,7 @@ extern "C" { #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 +#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 /* add more to the end as needed */ #define fourcc_mod_code(vendor, val) \ @@ -306,7 +307,6 @@ extern "C" { */ #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) - /* NVIDIA Tegra frame buffer modifiers */ /* @@ -351,6 +351,27 @@ extern "C" { */ #define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v) +/* + * Broadcom VC4 "T" format + * + * This is the primary layout that the V3D GPU can texture from (it + * can't do linear). The T format has: + * + * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 + * pixels at 32 bit depth. + * + * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually + * 16x16 pixels). + * + * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On + * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows + * they're (TR, BR, BL, TL), where bottom left is start of memory. + * + * - an image made of 4k tiles in rows either left-to-right (even rows of 4k + * tiles) or right-to-left (odd rows of 4k tiles). + */ +#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) + #if defined(__cplusplus) } #endif diff --git a/include/drm/vc4_drm.h b/include/drm/vc4_drm.h index 319881d8..6ac4c5c0 100644 --- a/include/drm/vc4_drm.h +++ b/include/drm/vc4_drm.h @@ -21,8 +21,8 @@ * IN THE SOFTWARE. */ -#ifndef _VC4_DRM_H_ -#define _VC4_DRM_H_ +#ifndef _UAPI_VC4_DRM_H_ +#define _UAPI_VC4_DRM_H_ #include "drm.h" @@ -38,6 +38,8 @@ extern "C" { #define DRM_VC4_CREATE_SHADER_BO 0x05 #define DRM_VC4_GET_HANG_STATE 0x06 #define DRM_VC4_GET_PARAM 0x07 +#define DRM_VC4_SET_TILING 0x08 +#define DRM_VC4_GET_TILING 0x09 #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) @@ -47,6 +49,8 @@ extern "C" { #define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) #define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) #define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) +#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling) +#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) struct drm_vc4_submit_rcl_surface { __u32 hindex; /* Handle index, or ~0 if not present. */ @@ -295,8 +299,20 @@ struct drm_vc4_get_param { __u64 value; }; +struct drm_vc4_get_tiling { + __u32 handle; + __u32 flags; + __u64 modifier; +}; + +struct drm_vc4_set_tiling { + __u32 handle; + __u32 flags; + __u64 modifier; +}; + #if defined(__cplusplus) } #endif -#endif /* _VC4_DRM_H_ */ +#endif /* _UAPI_VC4_DRM_H_ */ |