diff options
| author | Anusha Srivatsa <anusha.srivatsa@intel.com> | 2017-06-21 11:17:35 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-06-29 10:50:54 -0700 |
| commit | 0733f376ae93f7580be1641d8ebc644561d438f4 (patch) | |
| tree | 5c731b3d3da633628db74cfefa9830eb90ebfe8e | |
| parent | fc4922793f1871577bb44b1d69ec3801acb23eb6 (diff) | |
intel: PCI Ids for S SKU in CFL
Add the PCI IDs for S SKU IN CFL by following the spec.
v2: Update IDs.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
| -rw-r--r-- | intel/intel_chipset.h | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 41fc0da0..aeb72ba5 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -221,6 +221,12 @@ #define PCI_CHIP_GLK 0x3184 #define PCI_CHIP_GLK_2X6 0x3185 +#define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90 +#define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93 +#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91 +#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92 +#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 + #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ (devid) == PCI_CHIP_I945_GM || \ @@ -452,10 +458,19 @@ #define IS_GEMINILAKE(devid) ((devid) == PCI_CHIP_GLK || \ (devid) == PCI_CHIP_GLK_2X6) +#define IS_CFL_S(devid) ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \ + (devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \ + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \ + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \ + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3) + +#define IS_COFFEELAKE(devid) (IS_CFL_S(devid)) + #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ IS_BROXTON(devid) || \ IS_KABYLAKE(devid) || \ - IS_GEMINILAKE(devid)) + IS_GEMINILAKE(devid) || \ + IS_COFFEELAKE(devid)) #define IS_9XX(dev) (IS_GEN3(dev) || \ IS_GEN4(dev) || \ |