diff options
| author | Xiang, Haihao <haihao.xiang@intel.com> | 2014-05-26 10:36:49 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2014-05-28 16:35:08 +0800 |
| commit | 0523c58148e9496927f2c3fa9a641885a0350d0f (patch) | |
| tree | c4771051b314b0895246fefaccb7574d8badb88f | |
| parent | a9004e6c5c7f33cd1e33e4dab92a5a0017714bbd (diff) | |
VPP: i965_vpp_clear_surface() is still used for CSC on BDW
https://bugs.freedesktop.org/show_bug.cgi?id=79065
The regression is caused by commit 42258e1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
| -rwxr-xr-x | src/i965_post_processing.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c index 8999266..5fe7289 100755 --- a/src/i965_post_processing.c +++ b/src/i965_post_processing.c @@ -4817,13 +4817,13 @@ i965_vpp_clear_surface(VADriverContextP ctx, br13 |= BR13_8; br13 |= pitch; - if (IS_GEN6(i965->intel.device_info) || - IS_GEN7(i965->intel.device_info)) { - intel_batchbuffer_start_atomic_blt(batch, 48); - BEGIN_BLT_BATCH(batch, 12); - } else { + if (IS_IRONLAKE(i965->intel.device_info)) { intel_batchbuffer_start_atomic(batch, 48); BEGIN_BATCH(batch, 12); + } else { + /* Will double-check the command if the new chipset is added */ + intel_batchbuffer_start_atomic_blt(batch, 48); + BEGIN_BLT_BATCH(batch, 12); } region_width = obj_surface->width; |