diff options
174 files changed, 6960 insertions, 3026 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 19792cfb2d..87f90721b9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -515,6 +515,7 @@ F: hw/intc/arm* F: hw/intc/gic_internal.h F: hw/misc/a9scu.c F: hw/misc/arm11scu.c +F: hw/misc/arm_l2x0.c F: hw/timer/a9gtimer* F: hw/timer/arm* F: include/hw/arm/arm*.h @@ -587,6 +588,7 @@ L: qemu-arm@nongnu.org S: Maintained F: hw/arm/integratorcp.c F: hw/misc/arm_integrator_debug.c +F: include/hw/misc/arm_integrator_debug.h MCIMX6UL EVK / i.MX6ul M: Peter Maydell <peter.maydell@linaro.org> @@ -606,7 +608,9 @@ L: qemu-arm@nongnu.org S: Odd Fixes F: hw/arm/mcimx7d-sabre.c F: hw/arm/fsl-imx7.c +F: hw/misc/imx7_*.c F: include/hw/arm/fsl-imx7.h +F: include/hw/misc/imx7_*.h F: hw/pci-host/designware.c F: include/hw/pci-host/designware.h @@ -640,6 +644,10 @@ M: Peter Maydell <peter.maydell@linaro.org> L: qemu-arm@nongnu.org S: Odd Fixes F: hw/arm/nseries.c +F: hw/input/lm832x.c +F: hw/input/tsc2005.c +F: hw/misc/cbus.c +F: hw/timer/twl92230.c Palm M: Andrzej Zaborowski <balrogg@gmail.com> @@ -647,6 +655,7 @@ M: Peter Maydell <peter.maydell@linaro.org> L: qemu-arm@nongnu.org S: Odd Fixes F: hw/arm/palm.c +F: hw/input/tsc210x.c Raspberry Pi M: Peter Maydell <peter.maydell@linaro.org> @@ -683,6 +692,7 @@ F: hw/display/tc6393xb.c F: hw/gpio/max7310.c F: hw/gpio/zaurus.c F: hw/misc/mst_fpga.c +F: hw/misc/max111x.c F: include/hw/arm/pxa.h F: include/hw/arm/sharpsl.h @@ -693,10 +703,10 @@ L: qemu-arm@nongnu.org S: Odd Fixes F: hw/arm/sabrelite.c F: hw/arm/fsl-imx6.c -F: hw/misc/imx6_src.c +F: hw/misc/imx6_*.c F: hw/ssi/imx_spi.c F: include/hw/arm/fsl-imx6.h -F: include/hw/misc/imx6_src.h +F: include/hw/misc/imx6_*.h F: include/hw/ssi/imx_spi.h Sharp SL-5500 (Collie) PDA @@ -807,7 +817,9 @@ R: Joel Stanley <joel@jms.id.au> L: qemu-arm@nongnu.org S: Maintained F: hw/*/*aspeed* +F: hw/misc/pca9552.c F: include/hw/*/*aspeed* +F: include/hw/misc/pca9552*.h F: hw/net/ftgmac100.c F: include/hw/net/ftgmac100.h @@ -950,6 +962,7 @@ L: qemu-ppc@nongnu.org S: Odd Fixes F: hw/ppc/e500.[hc] F: hw/ppc/e500plat.c +F: hw/gpio/mpc8xxx.c F: include/hw/ppc/ppc_e500.h F: include/hw/pci-host/ppce500.h F: pc-bios/u-boot.e500 @@ -961,7 +974,7 @@ S: Odd Fixes F: hw/ppc/mpc8544ds.c F: hw/ppc/mpc8544_guts.c -New World +New World (mac99) M: David Gibson <david@gibson.dropbear.id.au> L: qemu-ppc@nongnu.org S: Odd Fixes @@ -971,12 +984,15 @@ F: hw/pci-bridge/dec.[hc] F: hw/misc/macio/ F: hw/misc/mos6522.c F: hw/nvram/mac_nvram.c +F: hw/input/adb* F: include/hw/misc/macio/ F: include/hw/misc/mos6522.h F: include/hw/ppc/mac_dbdma.h F: include/hw/pci-host/uninorth.h +F: include/hw/input/adb* +F: pc-bios/qemu_vga.ndrv -Old World +Old World (g3beige) M: David Gibson <david@gibson.dropbear.id.au> L: qemu-ppc@nongnu.org S: Odd Fixes @@ -984,7 +1000,10 @@ F: hw/ppc/mac_oldworld.c F: hw/pci-host/grackle.c F: hw/misc/macio/ F: hw/intc/heathrow_pic.c +F: hw/input/adb* F: include/hw/intc/heathrow_pic.h +F: include/hw/input/adb* +F: pc-bios/qemu_vga.ndrv PReP M: Hervé Poussineau <hpoussin@reactos.org> @@ -1040,8 +1059,14 @@ sam460ex M: BALATON Zoltan <balaton@eik.bme.hu> L: qemu-ppc@nongnu.org S: Maintained +F: hw/ppc/sam460ex.c +F: hw/ppc/ppc440_pcix.c +F: hw/display/sm501* F: hw/ide/sii3112.c F: hw/timer/m41t80.c +F: pc-bios/canyonlands.dt[sb] +F: pc-bios/u-boot-sam460ex-20100605.bin +F: roms/u-boot-sam460ex SH4 Machines ------------ @@ -1195,7 +1220,9 @@ M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> S: Supported F: hw/core/machine.c F: hw/core/null-machine.c +F: hw/cpu/cluster.c F: include/hw/boards.h +F: include/hw/cpu/cluster.h T: git https://github.com/ehabkost/qemu.git machine-next Xtensa Machines @@ -651,9 +651,9 @@ distclean: clean rm -Rf .sdk if test -f dtc/version_gen.h; then $(MAKE) $(DTC_MAKE_ARGS) clean; fi -KEYMAPS=da en-gb et fr fr-ch is lt modifiers no pt-br sv \ +KEYMAPS=da en-gb et fr fr-ch is lt no pt-br sv \ ar de en-us fi fr-be hr it lv nl pl ru th \ -common de-ch es fo fr-ca hu ja mk nl-be pt sl tr \ +de-ch es fo fr-ca hu ja mk pt sl tr \ bepo cz ifdef INSTALL_BLOBS diff --git a/Makefile.objs b/Makefile.objs index bc5b8a8442..456115992a 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -184,6 +184,7 @@ trace-events-subdirs += hw/vfio trace-events-subdirs += hw/virtio trace-events-subdirs += hw/watchdog trace-events-subdirs += hw/xen +trace-events-subdirs += hw/gpio trace-events-subdirs += io trace-events-subdirs += linux-user trace-events-subdirs += migration diff --git a/accel/accel.c b/accel/accel.c index 3da26eb90f..6db5d8f4df 100644 --- a/accel/accel.c +++ b/accel/accel.c @@ -119,18 +119,6 @@ void configure_accelerator(MachineState *ms) } } -void accel_register_compat_props(AccelState *accel) -{ - AccelClass *class = ACCEL_GET_CLASS(accel); - GlobalProperty *prop = class->global_props; - - for (; prop && prop->driver; prop++) { - /* Any compat_props must never cause error */ - prop->errp = &error_abort; - qdev_prop_register_global(prop); - } -} - void accel_setup_post(MachineState *ms) { AccelState *accel = ms->accelerator; diff --git a/backends/hostmem-file.c b/backends/hostmem-file.c index 78f058dee2..7a34e25c43 100644 --- a/backends/hostmem-file.c +++ b/backends/hostmem-file.c @@ -43,7 +43,7 @@ file_backend_memory_alloc(HostMemoryBackend *backend, Error **errp) { HostMemoryBackendFile *fb = MEMORY_BACKEND_FILE(backend); #ifdef CONFIG_POSIX - gchar *path; + gchar *name; #endif if (!backend->size) { @@ -58,14 +58,14 @@ file_backend_memory_alloc(HostMemoryBackend *backend, Error **errp) error_setg(errp, "-mem-path not supported on this host"); #else backend->force_prealloc = mem_prealloc; - path = object_get_canonical_path(OBJECT(backend)); + name = host_memory_backend_get_name(backend); memory_region_init_ram_from_file(&backend->mr, OBJECT(backend), - path, + name, backend->size, fb->align, (backend->share ? RAM_SHARED : 0) | (fb->is_pmem ? RAM_PMEM : 0), fb->mem_path, errp); - g_free(path); + g_free(name); #endif } diff --git a/backends/hostmem-memfd.c b/backends/hostmem-memfd.c index 2eb9c827a5..98c9bf3240 100644 --- a/backends/hostmem-memfd.c +++ b/backends/hostmem-memfd.c @@ -53,7 +53,7 @@ memfd_backend_memory_alloc(HostMemoryBackend *backend, Error **errp) return; } - name = object_get_canonical_path(OBJECT(backend)); + name = host_memory_backend_get_name(backend); memory_region_init_ram_from_fd(&backend->mr, OBJECT(backend), name, backend->size, backend->share, fd, errp); diff --git a/backends/hostmem-ram.c b/backends/hostmem-ram.c index 7ddd08d370..24b65d9ae3 100644 --- a/backends/hostmem-ram.c +++ b/backends/hostmem-ram.c @@ -16,21 +16,20 @@ #define TYPE_MEMORY_BACKEND_RAM "memory-backend-ram" - static void ram_backend_memory_alloc(HostMemoryBackend *backend, Error **errp) { - char *path; + char *name; if (!backend->size) { error_setg(errp, "can't create backend with size 0"); return; } - path = object_get_canonical_path_component(OBJECT(backend)); - memory_region_init_ram_shared_nomigrate(&backend->mr, OBJECT(backend), path, + name = host_memory_backend_get_name(backend); + memory_region_init_ram_shared_nomigrate(&backend->mr, OBJECT(backend), name, backend->size, backend->share, errp); - g_free(path); + g_free(name); } static void diff --git a/backends/hostmem.c b/backends/hostmem.c index af800284e0..0c8ef17653 100644 --- a/backends/hostmem.c +++ b/backends/hostmem.c @@ -28,6 +28,16 @@ QEMU_BUILD_BUG_ON(HOST_MEM_POLICY_BIND != MPOL_BIND); QEMU_BUILD_BUG_ON(HOST_MEM_POLICY_INTERLEAVE != MPOL_INTERLEAVE); #endif +char * +host_memory_backend_get_name(HostMemoryBackend *backend) +{ + if (!backend->use_canonical_path) { + return object_get_canonical_path_component(OBJECT(backend)); + } + + return object_get_canonical_path(OBJECT(backend)); +} + static void host_memory_backend_get_size(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) @@ -247,6 +257,11 @@ static void host_memory_backend_init(Object *obj) backend->prealloc = mem_prealloc; } +static void host_memory_backend_post_init(Object *obj) +{ + object_apply_compat_props(obj); +} + bool host_memory_backend_mr_inited(HostMemoryBackend *backend) { /* @@ -395,6 +410,23 @@ static void host_memory_backend_set_share(Object *o, bool value, Error **errp) backend->share = value; } +static bool +host_memory_backend_get_use_canonical_path(Object *obj, Error **errp) +{ + HostMemoryBackend *backend = MEMORY_BACKEND(obj); + + return backend->use_canonical_path; +} + +static void +host_memory_backend_set_use_canonical_path(Object *obj, bool value, + Error **errp) +{ + HostMemoryBackend *backend = MEMORY_BACKEND(obj); + + backend->use_canonical_path = value; +} + static void host_memory_backend_class_init(ObjectClass *oc, void *data) { @@ -441,6 +473,9 @@ host_memory_backend_class_init(ObjectClass *oc, void *data) &error_abort); object_class_property_set_description(oc, "share", "Mark the memory as private to QEMU or shared", &error_abort); + object_class_property_add_bool(oc, "x-use-canonical-path-for-ramblock-id", + host_memory_backend_get_use_canonical_path, + host_memory_backend_set_use_canonical_path, &error_abort); } static const TypeInfo host_memory_backend_info = { @@ -451,6 +486,7 @@ static const TypeInfo host_memory_backend_info = { .class_init = host_memory_backend_class_init, .instance_size = sizeof(HostMemoryBackend), .instance_init = host_memory_backend_init, + .instance_post_init = host_memory_backend_post_init, .interfaces = (InterfaceInfo[]) { { TYPE_USER_CREATABLE }, { } diff --git a/block/nbd-client.c b/block/nbd-client.c index fc5b7eda8e..ef32075971 100644 --- a/block/nbd-client.c +++ b/block/nbd-client.c @@ -28,6 +28,8 @@ */ #include "qemu/osdep.h" + +#include "trace.h" #include "qapi/error.h" #include "nbd-client.h" @@ -79,7 +81,8 @@ static coroutine_fn void nbd_read_reply_entry(void *opaque) assert(s->reply.handle == 0); ret = nbd_receive_reply(s->ioc, &s->reply, &local_err); if (local_err) { - error_report_err(local_err); + trace_nbd_read_reply_entry_fail(ret, error_get_pretty(local_err)); + error_free(local_err); } if (ret <= 0) { break; @@ -771,7 +774,11 @@ static int nbd_co_request(BlockDriverState *bs, NBDRequest *request, ret = nbd_co_receive_return_code(client, request->handle, &local_err); if (local_err) { - error_report_err(local_err); + trace_nbd_co_request_fail(request->from, request->len, request->handle, + request->flags, request->type, + nbd_cmd_lookup(request->type), + ret, error_get_pretty(local_err)); + error_free(local_err); } return ret; } @@ -802,7 +809,11 @@ int nbd_client_co_preadv(BlockDriverState *bs, uint64_t offset, ret = nbd_co_receive_cmdread_reply(client, request.handle, offset, qiov, &local_err); if (local_err) { - error_report_err(local_err); + trace_nbd_co_request_fail(request.from, request.len, request.handle, + request.flags, request.type, + nbd_cmd_lookup(request.type), + ret, error_get_pretty(local_err)); + error_free(local_err); } return ret; } @@ -925,7 +936,11 @@ int coroutine_fn nbd_client_co_block_status(BlockDriverState *bs, ret = nbd_co_receive_blockstatus_reply(client, request.handle, bytes, &extent, &local_err); if (local_err) { - error_report_err(local_err); + trace_nbd_co_request_fail(request.from, request.len, request.handle, + request.flags, request.type, + nbd_cmd_lookup(request.type), + ret, error_get_pretty(local_err)); + error_free(local_err); } if (ret < 0) { return ret; diff --git a/block/nvme.c b/block/nvme.c index 29294038fc..982097b5b1 100644 --- a/block/nvme.c +++ b/block/nvme.c @@ -837,7 +837,7 @@ try_map: } for (j = 0; j < qiov->iov[i].iov_len / s->page_size; j++) { - pagelist[entries++] = iova + j * s->page_size; + pagelist[entries++] = cpu_to_le64(iova + j * s->page_size); } trace_nvme_cmd_map_qiov_iov(s, i, qiov->iov[i].iov_base, qiov->iov[i].iov_len / s->page_size); @@ -850,20 +850,16 @@ try_map: case 0: abort(); case 1: - cmd->prp1 = cpu_to_le64(pagelist[0]); + cmd->prp1 = pagelist[0]; cmd->prp2 = 0; break; case 2: - cmd->prp1 = cpu_to_le64(pagelist[0]); - cmd->prp2 = cpu_to_le64(pagelist[1]);; + cmd->prp1 = pagelist[0]; + cmd->prp2 = pagelist[1]; break; default: - cmd->prp1 = cpu_to_le64(pagelist[0]); - cmd->prp2 = cpu_to_le64(req->prp_list_iova); - for (i = 0; i < entries - 1; ++i) { - pagelist[i] = cpu_to_le64(pagelist[i + 1]); - } - pagelist[entries - 1] = 0; + cmd->prp1 = pagelist[0]; + cmd->prp2 = cpu_to_le64(req->prp_list_iova + sizeof(uint64_t)); break; } trace_nvme_cmd_map_qiov(s, cmd, req, qiov, entries); diff --git a/block/trace-events b/block/trace-events index 3e8c47bb24..693c14c443 100644 --- a/block/trace-events +++ b/block/trace-events @@ -156,3 +156,7 @@ nvme_cmd_map_qiov_iov(void *s, int i, void *page, int pages) "s %p iov[%d] %p pa # block/iscsi.c iscsi_xcopy(void *src_lun, uint64_t src_off, void *dst_lun, uint64_t dst_off, uint64_t bytes, int ret) "src_lun %p offset %"PRIu64" dst_lun %p offset %"PRIu64" bytes %"PRIu64" ret %d" + +# block/nbd-client.c +nbd_read_reply_entry_fail(int ret, const char *err) "ret = %d, err: %s" +nbd_co_request_fail(uint64_t from, uint32_t len, uint64_t handle, uint16_t flags, uint16_t type, const char *name, int ret, const char *err) "Request failed { .from = %" PRIu64", .len = %" PRIu32 ", .handle = %" PRIu64 ", .flags = 0x%" PRIx16 ", .type = %" PRIu16 " (%s) } ret = %d, err: %s" diff --git a/chardev/spice.c b/chardev/spice.c index e66e3ad568..173c257949 100644 --- a/chardev/spice.c +++ b/chardev/spice.c @@ -77,7 +77,6 @@ static int vmc_read(SpiceCharDeviceInstance *sin, uint8_t *buf, int len) return bytes; } -#if SPICE_SERVER_VERSION >= 0x000c02 static void vmc_event(SpiceCharDeviceInstance *sin, uint8_t event) { SpiceChardev *scd = container_of(sin, SpiceChardev, sin); @@ -95,7 +94,6 @@ static void vmc_event(SpiceCharDeviceInstance *sin, uint8_t event) trace_spice_vmc_event(chr_event); qemu_chr_be_event(chr, chr_event); } -#endif static void vmc_state(SpiceCharDeviceInstance *sin, int connected) { @@ -119,9 +117,7 @@ static SpiceCharDeviceInterface vmc_interface = { .state = vmc_state, .write = vmc_write, .read = vmc_read, -#if SPICE_SERVER_VERSION >= 0x000c02 .event = vmc_event, -#endif #if SPICE_SERVER_VERSION >= 0x000c06 .flags = SPICE_CHAR_DEVICE_NOTIFY_WRITABLE, #endif @@ -223,9 +219,7 @@ static void char_spice_finalize(Object *obj) } g_free((char *)s->sin.subtype); -#if SPICE_SERVER_VERSION >= 0x000c02 g_free((char *)s->sin.portname); -#endif } static void spice_vmc_set_fe_open(struct Chardev *chr, int fe_open) @@ -240,7 +234,6 @@ static void spice_vmc_set_fe_open(struct Chardev *chr, int fe_open) static void spice_port_set_fe_open(struct Chardev *chr, int fe_open) { -#if SPICE_SERVER_VERSION >= 0x000c02 SpiceChardev *s = SPICE_CHARDEV(chr); if (fe_open) { @@ -248,7 +241,6 @@ static void spice_port_set_fe_open(struct Chardev *chr, int fe_open) } else { spice_server_port_event(&s->sin, SPICE_PORT_EVENT_CLOSED); } -#endif } static void spice_chr_accept_input(struct Chardev *chr) @@ -298,7 +290,6 @@ static void qemu_chr_open_spice_vmc(Chardev *chr, chr_open(chr, type); } -#if SPICE_SERVER_VERSION >= 0x000c02 static void qemu_chr_open_spice_port(Chardev *chr, ChardevBackend *backend, bool *be_opened, @@ -331,7 +322,6 @@ void qemu_spice_register_ports(void) vmc_register_interface(s); } } -#endif static void qemu_chr_parse_spice_vmc(QemuOpts *opts, ChardevBackend *backend, Error **errp) @@ -3721,8 +3721,8 @@ if test "$mingw32" != yes -a "$pthread" = no; then "Make sure to have the pthread libs and headers installed." fi -# check for pthread_setname_np -pthread_setname_np=no +# check for pthread_setname_np with thread id +pthread_setname_np_w_tid=no cat > $TMPC << EOF #include <pthread.h> @@ -3736,7 +3736,24 @@ int main(void) } EOF if compile_prog "" "$pthread_lib" ; then - pthread_setname_np=yes + pthread_setname_np_w_tid=yes +fi + +# check for pthread_setname_np without thread id +pthread_setname_np_wo_tid=no +cat > $TMPC << EOF +#include <pthread.h> + +static void *f(void *p) { pthread_setname_np("QEMU"); } +int main(void) +{ + pthread_t thread; + pthread_create(&thread, 0, f, 0); + return 0; +} +EOF +if compile_prog "" "$pthread_lib" ; then + pthread_setname_np_wo_tid=yes fi ########################################## @@ -3922,7 +3939,7 @@ if test "$fdt" != "no" ; then cat > $TMPC << EOF #include <libfdt.h> #include <libfdt_env.h> -int main(void) { fdt_first_subnode(0, 0); return 0; } +int main(void) { fdt_check_full(NULL, 0); return 0; } EOF if compile_prog "" "$fdt_libs" ; then # system DTC is good - use it @@ -4605,7 +4622,7 @@ int main(void) { spice_server_new(); return 0; } EOF spice_cflags=$($pkg_config --cflags spice-protocol spice-server 2>/dev/null) spice_libs=$($pkg_config --libs spice-protocol spice-server 2>/dev/null) - if $pkg_config --atleast-version=0.12.0 spice-server && \ + if $pkg_config --atleast-version=0.12.5 spice-server && \ $pkg_config --atleast-version=0.12.3 spice-protocol && \ compile_prog "$spice_cflags" "$spice_libs" ; then spice="yes" @@ -4616,7 +4633,7 @@ EOF else if test "$spice" = "yes" ; then feature_not_found "spice" \ - "Install spice-server(>=0.12.0) and spice-protocol(>=0.12.3) devel" + "Install spice-server(>=0.12.5) and spice-protocol(>=0.12.3) devel" fi spice="no" fi @@ -6889,11 +6906,14 @@ fi # Hold two types of flag: # CONFIG_THREAD_SETNAME_BYTHREAD - we've got a way of setting the name on # a thread we have a handle to -# CONFIG_PTHREAD_SETNAME_NP - A way of doing it on a particular +# CONFIG_PTHREAD_SETNAME_NP_W_TID - A way of doing it on a particular # platform -if test "$pthread_setname_np" = "yes" ; then +if test "$pthread_setname_np_w_tid" = "yes" ; then + echo "CONFIG_THREAD_SETNAME_BYTHREAD=y" >> $config_host_mak + echo "CONFIG_PTHREAD_SETNAME_NP_W_TID=y" >> $config_host_mak +elif test "$pthread_setname_np_wo_tid" = "yes" ; then echo "CONFIG_THREAD_SETNAME_BYTHREAD=y" >> $config_host_mak - echo "CONFIG_PTHREAD_SETNAME_NP=y" >> $config_host_mak + echo "CONFIG_PTHREAD_SETNAME_NP_WO_TID=y" >> $config_host_mak fi if test "$vxhs" = "yes" ; then @@ -2100,7 +2100,8 @@ void qemu_init_vcpu(CPUState *cpu) void cpu_stop_current(void) { if (current_cpu) { - qemu_cpu_stop(current_cpu, true); + current_cpu->stop = true; + cpu_exit(current_cpu); } } diff --git a/docs/interop/nbd.txt b/docs/interop/nbd.txt index 77b5f45911..fc64473e02 100644 --- a/docs/interop/nbd.txt +++ b/docs/interop/nbd.txt @@ -15,7 +15,6 @@ Qemu supports the "base:allocation" metadata context as defined in the NBD protocol specification, and also defines an additional metadata namespace "qemu". - == "qemu" namespace == The "qemu" namespace currently contains only one type of context, @@ -36,3 +35,21 @@ in addition to "qemu:dirty-bitmap:<dirty-bitmap-export-name>": namespace. * "qemu:dirty-bitmap:" - returns list of all available dirty-bitmap metadata contexts. + += Features by version = + +The following list documents which qemu version first implemented +various features (both as a server exposing the feature, and as a +client taking advantage of the feature when present), to make it +easier to plan for cross-version interoperability. Note that in +several cases, the initial release containing a feature may require +additional patches from the corresponding stable branch to fix bugs in +the operation of that feature. + +* 2.6: NBD_OPT_STARTTLS with TLS X.509 Certificates +* 2.8: NBD_CMD_WRITE_ZEROES +* 2.10: NBD_OPT_GO, NBD_INFO_BLOCK +* 2.11: NBD_OPT_STRUCTURED_REPLY +* 2.12: NBD_CMD_BLOCK_STATUS for "base:allocation" +* 3.0: NBD_OPT_STARTTLS with TLS Pre-Shared Keys (PSK), +NBD_CMD_BLOCK_STATUS for "qemu:dirty-bitmap:", NBD_CMD_CACHE @@ -29,6 +29,7 @@ #include "chardev/char-fe.h" #include "sysemu/sysemu.h" #include "exec/gdbstub.h" +#include "hw/cpu/cluster.h" #endif #define MAX_PACKET_LENGTH 4096 @@ -296,6 +297,13 @@ typedef struct GDBRegisterState { struct GDBRegisterState *next; } GDBRegisterState; +typedef struct GDBProcess { + uint32_t pid; + bool attached; + + char target_xml[1024]; +} GDBProcess; + enum RSState { RS_INACTIVE, RS_IDLE, @@ -324,6 +332,9 @@ typedef struct GDBState { CharBackend chr; Chardev *mon_chr; #endif + bool multiprocess; + GDBProcess *processes; + int process_num; char syscall_buf[256]; gdb_syscall_complete_cb current_syscall_cb; } GDBState; @@ -631,13 +642,186 @@ static int memtox(char *buf, const char *mem, int len) return p - buf; } -static const char *get_feature_xml(const char *p, const char **newp, - CPUClass *cc) +static uint32_t gdb_get_cpu_pid(const GDBState *s, CPUState *cpu) +{ +#ifndef CONFIG_USER_ONLY + gchar *path, *name = NULL; + Object *obj; + CPUClusterState *cluster; + uint32_t ret; + + path = object_get_canonical_path(OBJECT(cpu)); + + if (path == NULL) { + /* Return the default process' PID */ + ret = s->processes[s->process_num - 1].pid; + goto out; + } + + name = object_get_canonical_path_component(OBJECT(cpu)); + assert(name != NULL); + + /* + * Retrieve the CPU parent path by removing the last '/' and the CPU name + * from the CPU canonical path. + */ + path[strlen(path) - strlen(name) - 1] = '\0'; + + obj = object_resolve_path_type(path, TYPE_CPU_CLUSTER, NULL); + + if (obj == NULL) { + /* Return the default process' PID */ + ret = s->processes[s->process_num - 1].pid; + goto out; + } + + cluster = CPU_CLUSTER(obj); + ret = cluster->cluster_id + 1; + +out: + g_free(name); + g_free(path); + + return ret; + +#else + /* TODO: In user mode, we should use the task state PID */ + return s->processes[s->process_num - 1].pid; +#endif +} + +static GDBProcess *gdb_get_process(const GDBState *s, uint32_t pid) +{ + int i; + + if (!pid) { + /* 0 means any process, we take the first one */ + return &s->processes[0]; + } + + for (i = 0; i < s->process_num; i++) { + if (s->processes[i].pid == pid) { + return &s->processes[i]; + } + } + + return NULL; +} + +static GDBProcess *gdb_get_cpu_process(const GDBState *s, CPUState *cpu) +{ + return gdb_get_process(s, gdb_get_cpu_pid(s, cpu)); +} + +static CPUState *find_cpu(uint32_t thread_id) +{ + CPUState *cpu; + + CPU_FOREACH(cpu) { + if (cpu_gdb_index(cpu) == thread_id) { + return cpu; + } + } + + return NULL; +} + +static CPUState *get_first_cpu_in_process(const GDBState *s, + GDBProcess *process) +{ + CPUState *cpu; + + CPU_FOREACH(cpu) { + if (gdb_get_cpu_pid(s, cpu) == process->pid) { + return cpu; + } + } + + return NULL; +} + +static CPUState *gdb_next_cpu_in_process(const GDBState *s, CPUState *cpu) +{ + uint32_t pid = gdb_get_cpu_pid(s, cpu); + cpu = CPU_NEXT(cpu); + + while (cpu) { + if (gdb_get_cpu_pid(s, cpu) == pid) { + break; + } + + cpu = CPU_NEXT(cpu); + } + + return cpu; +} + +static CPUState *gdb_get_cpu(const GDBState *s, uint32_t pid, uint32_t tid) +{ + GDBProcess *process; + CPUState *cpu; + + if (!tid) { + /* 0 means any thread, we take the first one */ + tid = 1; + } + + cpu = find_cpu(tid); + + if (cpu == NULL) { + return NULL; + } + + process = gdb_get_cpu_process(s, cpu); + + if (process->pid != pid) { + return NULL; + } + + if (!process->attached) { + return NULL; + } + + return cpu; +} + +/* Return the cpu following @cpu, while ignoring unattached processes. */ +static CPUState *gdb_next_attached_cpu(const GDBState *s, CPUState *cpu) +{ + cpu = CPU_NEXT(cpu); + + while (cpu) { + if (gdb_get_cpu_process(s, cpu)->attached) { + break; + } + + cpu = CPU_NEXT(cpu); + } + + return cpu; +} + +/* Return the first attached cpu */ +static CPUState *gdb_first_attached_cpu(const GDBState *s) +{ + CPUState *cpu = first_cpu; + GDBProcess *process = gdb_get_cpu_process(s, cpu); + + if (!process->attached) { + return gdb_next_attached_cpu(s, cpu); + } + + return cpu; +} + +static const char *get_feature_xml(const GDBState *s, const char *p, + const char **newp, GDBProcess *process) { size_t len; int i; const char *name; - static char target_xml[1024]; + CPUState *cpu = get_first_cpu_in_process(s, process); + CPUClass *cc = CPU_GET_CLASS(cpu); len = 0; while (p[len] && p[len] != ':') @@ -646,36 +830,37 @@ static const char *get_feature_xml(const char *p, const char **newp, name = NULL; if (strncmp(p, "target.xml", len) == 0) { + char *buf = process->target_xml; + const size_t buf_sz = sizeof(process->target_xml); + /* Generate the XML description for this CPU. */ - if (!target_xml[0]) { + if (!buf[0]) { GDBRegisterState *r; - CPUState *cpu = first_cpu; - pstrcat(target_xml, sizeof(target_xml), + pstrcat(buf, buf_sz, "<?xml version=\"1.0\"?>" "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">" "<target>"); if (cc->gdb_arch_name) { gchar *arch = cc->gdb_arch_name(cpu); - pstrcat(target_xml, sizeof(target_xml), "<architecture>"); - pstrcat(target_xml, sizeof(target_xml), arch); - pstrcat(target_xml, sizeof(target_xml), "</architecture>"); + pstrcat(buf, buf_sz, "<architecture>"); + pstrcat(buf, buf_sz, arch); + pstrcat(buf, buf_sz, "</architecture>"); g_free(arch); } - pstrcat(target_xml, sizeof(target_xml), "<xi:include href=\""); - pstrcat(target_xml, sizeof(target_xml), cc->gdb_core_xml_file); - pstrcat(target_xml, sizeof(target_xml), "\"/>"); + pstrcat(buf, buf_sz, "<xi:include href=\""); + pstrcat(buf, buf_sz, cc->gdb_core_xml_file); + pstrcat(buf, buf_sz, "\"/>"); for (r = cpu->gdb_regs; r; r = r->next) { - pstrcat(target_xml, sizeof(target_xml), "<xi:include href=\""); - pstrcat(target_xml, sizeof(target_xml), r->xml); - pstrcat(target_xml, sizeof(target_xml), "\"/>"); + pstrcat(buf, buf_sz, "<xi:include href=\""); + pstrcat(buf, buf_sz, r->xml); + pstrcat(buf, buf_sz, "\"/>"); } - pstrcat(target_xml, sizeof(target_xml), "</target>"); + pstrcat(buf, buf_sz, "</target>"); } - return target_xml; + return buf; } if (cc->gdb_get_dynamic_xml) { - CPUState *cpu = first_cpu; char *xmlname = g_strndup(p, len); const char *xml = cc->gdb_get_dynamic_xml(cpu, xmlname); @@ -862,6 +1047,24 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type) } } +static inline void gdb_cpu_breakpoint_remove_all(CPUState *cpu) +{ + cpu_breakpoint_remove_all(cpu, BP_GDB); +#ifndef CONFIG_USER_ONLY + cpu_watchpoint_remove_all(cpu, BP_GDB); +#endif +} + +static void gdb_process_breakpoint_remove_all(const GDBState *s, GDBProcess *p) +{ + CPUState *cpu = get_first_cpu_in_process(s, p); + + while (cpu) { + gdb_cpu_breakpoint_remove_all(cpu); + cpu = gdb_next_cpu_in_process(s, cpu); + } +} + static void gdb_breakpoint_remove_all(void) { CPUState *cpu; @@ -872,10 +1075,7 @@ static void gdb_breakpoint_remove_all(void) } CPU_FOREACH(cpu) { - cpu_breakpoint_remove_all(cpu, BP_GDB); -#ifndef CONFIG_USER_ONLY - cpu_watchpoint_remove_all(cpu, BP_GDB); -#endif + gdb_cpu_breakpoint_remove_all(cpu); } } @@ -887,17 +1087,71 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong pc) cpu_set_pc(cpu, pc); } -static CPUState *find_cpu(uint32_t thread_id) +static char *gdb_fmt_thread_id(const GDBState *s, CPUState *cpu, + char *buf, size_t buf_size) { - CPUState *cpu; + if (s->multiprocess) { + snprintf(buf, buf_size, "p%02x.%02x", + gdb_get_cpu_pid(s, cpu), cpu_gdb_index(cpu)); + } else { + snprintf(buf, buf_size, "%02x", cpu_gdb_index(cpu)); + } - CPU_FOREACH(cpu) { - if (cpu_gdb_index(cpu) == thread_id) { - return cpu; + return buf; +} + +typedef enum GDBThreadIdKind { + GDB_ONE_THREAD = 0, + GDB_ALL_THREADS, /* One process, all threads */ + GDB_ALL_PROCESSES, + GDB_READ_THREAD_ERR +} GDBThreadIdKind; + +static GDBThreadIdKind read_thread_id(const char *buf, const char **end_buf, + uint32_t *pid, uint32_t *tid) +{ + unsigned long p, t; + int ret; + + if (*buf == 'p') { + buf++; + ret = qemu_strtoul(buf, &buf, 16, &p); + + if (ret) { + return GDB_READ_THREAD_ERR; } + + /* Skip '.' */ + buf++; + } else { + p = 1; } - return NULL; + ret = qemu_strtoul(buf, &buf, 16, &t); + + if (ret) { + return GDB_READ_THREAD_ERR; + } + + *end_buf = buf; + + if (p == -1) { + return GDB_ALL_PROCESSES; + } + + if (pid) { + *pid = p; + } + + if (t == -1) { + return GDB_ALL_THREADS; + } + + if (tid) { + *tid = t; + } + + return GDB_ONE_THREAD; } static int is_query_packet(const char *p, const char *query, char separator) @@ -915,10 +1169,12 @@ static int is_query_packet(const char *p, const char *query, char separator) */ static int gdb_handle_vcont(GDBState *s, const char *p) { - int res, idx, signal = 0; + int res, signal = 0; char cur_action; char *newstates; unsigned long tmp; + uint32_t pid, tid; + GDBProcess *process; CPUState *cpu; #ifdef CONFIG_USER_ONLY int max_cpus = 1; /* global variable max_cpus exists only in system mode */ @@ -961,25 +1217,48 @@ static int gdb_handle_vcont(GDBState *s, const char *p) res = -ENOTSUP; goto out; } - /* thread specification. special values: (none), -1 = all; 0 = any */ - if ((p[0] == ':' && p[1] == '-' && p[2] == '1') || (p[0] != ':')) { - if (*p == ':') { - p += 3; - } - for (idx = 0; idx < max_cpus; idx++) { - if (newstates[idx] == 1) { - newstates[idx] = cur_action; + + if (*p++ != ':') { + res = -ENOTSUP; + goto out; + } + + switch (read_thread_id(p, &p, &pid, &tid)) { + case GDB_READ_THREAD_ERR: + res = -EINVAL; + goto out; + + case GDB_ALL_PROCESSES: + cpu = gdb_first_attached_cpu(s); + while (cpu) { + if (newstates[cpu->cpu_index] == 1) { + newstates[cpu->cpu_index] = cur_action; } + + cpu = gdb_next_attached_cpu(s, cpu); } - } else if (*p == ':') { - p++; - res = qemu_strtoul(p, &p, 16, &tmp); - if (res) { + break; + + case GDB_ALL_THREADS: + process = gdb_get_process(s, pid); + + if (!process->attached) { + res = -EINVAL; goto out; } - /* 0 means any thread, so we pick the first valid CPU */ - cpu = tmp ? find_cpu(tmp) : first_cpu; + cpu = get_first_cpu_in_process(s, process); + while (cpu) { + if (newstates[cpu->cpu_index] == 1) { + newstates[cpu->cpu_index] = cur_action; + } + + cpu = gdb_next_cpu_in_process(s, cpu); + } + break; + + case GDB_ONE_THREAD: + cpu = gdb_get_cpu(s, pid, tid); /* invalid CPU/thread specified */ if (!cpu) { @@ -991,6 +1270,7 @@ static int gdb_handle_vcont(GDBState *s, const char *p) if (newstates[cpu->cpu_index] == 1) { newstates[cpu->cpu_index] = cur_action; } + break; } } s->signal = signal; @@ -1005,24 +1285,30 @@ out: static int gdb_handle_packet(GDBState *s, const char *line_buf) { CPUState *cpu; + GDBProcess *process; CPUClass *cc; const char *p; - uint32_t thread; + uint32_t pid, tid; int ch, reg_size, type, res; uint8_t mem_buf[MAX_PACKET_LENGTH]; char buf[sizeof(mem_buf) + 1 /* trailing NUL */]; + char thread_id[16]; uint8_t *registers; target_ulong addr, len; + GDBThreadIdKind thread_kind; trace_gdbstub_io_command(line_buf); p = line_buf; ch = *p++; switch(ch) { + case '!': + put_packet(s, "OK"); + break; case '?': /* TODO: Make this return the correct value for user-mode. */ - snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP, - cpu_gdb_index(s->c_cpu)); + snprintf(buf, sizeof(buf), "T%02xthread:%s;", GDB_SIGNAL_TRAP, + gdb_fmt_thread_id(s, s->c_cpu, thread_id, sizeof(thread_id))); put_packet(s, buf); /* Remove all the breakpoints when this query is issued, * because gdb is doing and initial connect and the state @@ -1062,6 +1348,41 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) goto unknown_command; } break; + } else if (strncmp(p, "Attach;", 7) == 0) { + unsigned long pid; + + p += 7; + + if (qemu_strtoul(p, &p, 16, &pid)) { + put_packet(s, "E22"); + break; + } + + process = gdb_get_process(s, pid); + + if (process == NULL) { + put_packet(s, "E22"); + break; + } + + cpu = get_first_cpu_in_process(s, process); + + if (cpu == NULL) { + /* Refuse to attach an empty process */ + put_packet(s, "E22"); + break; + } + + process->attached = true; + + s->g_cpu = cpu; + s->c_cpu = cpu; + + snprintf(buf, sizeof(buf), "T%02xthread:%s;", GDB_SIGNAL_TRAP, + gdb_fmt_thread_id(s, cpu, thread_id, sizeof(thread_id))); + + put_packet(s, buf); + break; } else { goto unknown_command; } @@ -1071,9 +1392,40 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) exit(0); case 'D': /* Detach packet */ - gdb_breakpoint_remove_all(); - gdb_syscall_mode = GDB_SYS_DISABLED; - gdb_continue(s); + pid = 1; + + if (s->multiprocess) { + unsigned long lpid; + if (*p != ';') { + put_packet(s, "E22"); + break; + } + + if (qemu_strtoul(p + 1, &p, 16, &lpid)) { + put_packet(s, "E22"); + break; + } + + pid = lpid; + } + + process = gdb_get_process(s, pid); + gdb_process_breakpoint_remove_all(s, process); + process->attached = false; + + if (pid == gdb_get_cpu_pid(s, s->c_cpu)) { + s->c_cpu = gdb_first_attached_cpu(s); + } + + if (pid == gdb_get_cpu_pid(s, s->g_cpu)) { + s->g_cpu = gdb_first_attached_cpu(s); + } + + if (s->c_cpu == NULL) { + /* No more process attached */ + gdb_syscall_mode = GDB_SYS_DISABLED; + gdb_continue(s); + } put_packet(s, "OK"); break; case 's': @@ -1220,12 +1572,18 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) break; case 'H': type = *p++; - thread = strtoull(p, (char **)&p, 16); - if (thread == -1 || thread == 0) { + + thread_kind = read_thread_id(p, &p, &pid, &tid); + if (thread_kind == GDB_READ_THREAD_ERR) { + put_packet(s, "E22"); + break; + } + + if (thread_kind != GDB_ONE_THREAD) { put_packet(s, "OK"); break; } - cpu = find_cpu(thread); + cpu = gdb_get_cpu(s, pid, tid); if (cpu == NULL) { put_packet(s, "E22"); break; @@ -1245,8 +1603,12 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) } break; case 'T': - thread = strtoull(p, (char **)&p, 16); - cpu = find_cpu(thread); + thread_kind = read_thread_id(p, &p, &pid, &tid); + if (thread_kind == GDB_READ_THREAD_ERR) { + put_packet(s, "E22"); + break; + } + cpu = gdb_get_cpu(s, pid, tid); if (cpu != NULL) { put_packet(s, "OK"); @@ -1280,31 +1642,55 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) put_packet(s, "OK"); break; } else if (strcmp(p,"C") == 0) { - /* "Current thread" remains vague in the spec, so always return - * the first CPU (gdb returns the first thread). */ - put_packet(s, "QC1"); + /* + * "Current thread" remains vague in the spec, so always return + * the first thread of the current process (gdb returns the + * first thread). + */ + cpu = get_first_cpu_in_process(s, gdb_get_cpu_process(s, s->g_cpu)); + snprintf(buf, sizeof(buf), "QC%s", + gdb_fmt_thread_id(s, cpu, thread_id, sizeof(thread_id))); + put_packet(s, buf); break; } else if (strcmp(p,"fThreadInfo") == 0) { - s->query_cpu = first_cpu; + s->query_cpu = gdb_first_attached_cpu(s); goto report_cpuinfo; } else if (strcmp(p,"sThreadInfo") == 0) { report_cpuinfo: if (s->query_cpu) { - snprintf(buf, sizeof(buf), "m%x", cpu_gdb_index(s->query_cpu)); + snprintf(buf, sizeof(buf), "m%s", + gdb_fmt_thread_id(s, s->query_cpu, + thread_id, sizeof(thread_id))); put_packet(s, buf); - s->query_cpu = CPU_NEXT(s->query_cpu); + s->query_cpu = gdb_next_attached_cpu(s, s->query_cpu); } else put_packet(s, "l"); break; } else if (strncmp(p,"ThreadExtraInfo,", 16) == 0) { - thread = strtoull(p+16, (char **)&p, 16); - cpu = find_cpu(thread); + if (read_thread_id(p + 16, &p, &pid, &tid) == GDB_READ_THREAD_ERR) { + put_packet(s, "E22"); + break; + } + cpu = gdb_get_cpu(s, pid, tid); if (cpu != NULL) { cpu_synchronize_state(cpu); - /* memtohex() doubles the required space */ - len = snprintf((char *)mem_buf, sizeof(buf) / 2, - "CPU#%d [%s]", cpu->cpu_index, - cpu->halted ? "halted " : "running"); + + if (s->multiprocess && (s->process_num > 1)) { + /* Print the CPU model and name in multiprocess mode */ + ObjectClass *oc = object_get_class(OBJECT(cpu)); + const char *cpu_model = object_class_get_name(oc); + char *cpu_name = + object_get_canonical_path_component(OBJECT(cpu)); + len = snprintf((char *)mem_buf, sizeof(buf) / 2, + "%s %s [%s]", cpu_model, cpu_name, + cpu->halted ? "halted " : "running"); + g_free(cpu_name); + } else { + /* memtohex() doubles the required space */ + len = snprintf((char *)mem_buf, sizeof(buf) / 2, + "CPU#%d [%s]", cpu->cpu_index, + cpu->halted ? "halted " : "running"); + } trace_gdbstub_op_extra_info((char *)mem_buf); memtohex(buf, mem_buf, len); put_packet(s, buf); @@ -1346,6 +1732,12 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) if (cc->gdb_core_xml_file != NULL) { pstrcat(buf, sizeof(buf), ";qXfer:features:read+"); } + + if (strstr(p, "multiprocess+")) { + s->multiprocess = true; + } + pstrcat(buf, sizeof(buf), ";multiprocess+"); + put_packet(s, buf); break; } @@ -1353,14 +1745,15 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) const char *xml; target_ulong total_len; - cc = CPU_GET_CLASS(first_cpu); + process = gdb_get_cpu_process(s, s->g_cpu); + cc = CPU_GET_CLASS(s->g_cpu); if (cc->gdb_core_xml_file == NULL) { goto unknown_command; } gdb_has_xml = true; p += 19; - xml = get_feature_xml(p, &p, cc); + xml = get_feature_xml(s, p, &p, process); if (!xml) { snprintf(buf, sizeof(buf), "E00"); put_packet(s, buf); @@ -1411,6 +1804,16 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) void gdb_set_stop_cpu(CPUState *cpu) { + GDBProcess *p = gdb_get_cpu_process(gdbserver_state, cpu); + + if (!p->attached) { + /* + * Having a stop CPU corresponding to a process that is not attached + * confuses GDB. So we ignore the request. + */ + return; + } + gdbserver_state->c_cpu = cpu; gdbserver_state->g_cpu = cpu; } @@ -1421,6 +1824,7 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state) GDBState *s = gdbserver_state; CPUState *cpu = s->c_cpu; char buf[256]; + char thread_id[16]; const char *type; int ret; @@ -1432,6 +1836,14 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state) put_packet(s, s->syscall_buf); return; } + + if (cpu == NULL) { + /* No process attached */ + return; + } + + gdb_fmt_thread_id(s, cpu, thread_id, sizeof(thread_id)); + switch (state) { case RUN_STATE_DEBUG: if (cpu->watchpoint_hit) { @@ -1449,8 +1861,8 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state) trace_gdbstub_hit_watchpoint(type, cpu_gdb_index(cpu), (target_ulong)cpu->watchpoint_hit->vaddr); snprintf(buf, sizeof(buf), - "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";", - GDB_SIGNAL_TRAP, cpu_gdb_index(cpu), type, + "T%02xthread:%s;%swatch:" TARGET_FMT_lx ";", + GDB_SIGNAL_TRAP, thread_id, type, (target_ulong)cpu->watchpoint_hit->vaddr); cpu->watchpoint_hit = NULL; goto send_packet; @@ -1492,7 +1904,7 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state) break; } gdb_set_stop_cpu(cpu); - snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, cpu_gdb_index(cpu)); + snprintf(buf, sizeof(buf), "T%02xthread:%s;", ret, thread_id); send_packet: put_packet(s, buf); @@ -1751,6 +2163,31 @@ void gdb_exit(CPUArchState *env, int code) #endif } +/* + * Create the process that will contain all the "orphan" CPUs (that are not + * part of a CPU cluster). Note that if this process contains no CPUs, it won't + * be attachable and thus will be invisible to the user. + */ +static void create_default_process(GDBState *s) +{ + GDBProcess *process; + int max_pid = 0; + + if (s->process_num) { + max_pid = s->processes[s->process_num - 1].pid; + } + + s->processes = g_renew(GDBProcess, s->processes, ++s->process_num); + process = &s->processes[s->process_num - 1]; + + /* We need an available PID slot for this process */ + assert(max_pid < UINT32_MAX); + + process->pid = max_pid + 1; + process->attached = false; + process->target_xml[0] = '\0'; +} + #ifdef CONFIG_USER_ONLY int gdb_handlesig(CPUState *cpu, int sig) @@ -1846,8 +2283,10 @@ static bool gdb_accept(void) } s = g_malloc0(sizeof(GDBState)); - s->c_cpu = first_cpu; - s->g_cpu = first_cpu; + create_default_process(s); + s->processes[0].attached = true; + s->c_cpu = gdb_first_attached_cpu(s); + s->g_cpu = s->c_cpu; s->fd = fd; gdb_has_xml = false; @@ -1933,8 +2372,19 @@ static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size) static void gdb_chr_event(void *opaque, int event) { + int i; + GDBState *s = (GDBState *) opaque; + switch (event) { case CHR_EVENT_OPENED: + /* Start with first process attached, others detached */ + for (i = 0; i < s->process_num; i++) { + s->processes[i].attached = !i; + } + + s->c_cpu = gdb_first_attached_cpu(s); + s->g_cpu = s->c_cpu; + vm_stop(RUN_STATE_PAUSED); gdb_has_xml = false; break; @@ -2004,6 +2454,66 @@ static const TypeInfo char_gdb_type_info = { .class_init = char_gdb_class_init, }; +static int find_cpu_clusters(Object *child, void *opaque) +{ + if (object_dynamic_cast(child, TYPE_CPU_CLUSTER)) { + GDBState *s = (GDBState *) opaque; + CPUClusterState *cluster = CPU_CLUSTER(child); + GDBProcess *process; + + s->processes = g_renew(GDBProcess, s->processes, ++s->process_num); + + process = &s->processes[s->process_num - 1]; + + /* + * GDB process IDs -1 and 0 are reserved. To avoid subtle errors at + * runtime, we enforce here that the machine does not use a cluster ID + * that would lead to PID 0. + */ + assert(cluster->cluster_id != UINT32_MAX); + process->pid = cluster->cluster_id + 1; + process->attached = false; + process->target_xml[0] = '\0'; + + return 0; + } + + return object_child_foreach(child, find_cpu_clusters, opaque); +} + +static int pid_order(const void *a, const void *b) +{ + GDBProcess *pa = (GDBProcess *) a; + GDBProcess *pb = (GDBProcess *) b; + + if (pa->pid < pb->pid) { + return -1; + } else if (pa->pid > pb->pid) { + return 1; + } else { + return 0; + } +} + +static void create_processes(GDBState *s) +{ + object_child_foreach(object_get_root(), find_cpu_clusters, s); + + if (s->processes) { + /* Sort by PID */ + qsort(s->processes, s->process_num, sizeof(s->processes[0]), pid_order); + } + + create_default_process(s); +} + +static void cleanup_processes(GDBState *s) +{ + g_free(s->processes); + s->process_num = 0; + s->processes = NULL; +} + int gdbserver_start(const char *device) { trace_gdbstub_op_start(device); @@ -2060,15 +2570,17 @@ int gdbserver_start(const char *device) } else { qemu_chr_fe_deinit(&s->chr, true); mon_chr = s->mon_chr; + cleanup_processes(s); memset(s, 0, sizeof(GDBState)); s->mon_chr = mon_chr; } - s->c_cpu = first_cpu; - s->g_cpu = first_cpu; + + create_processes(s); + if (chr) { qemu_chr_fe_init(&s->chr, chr, &error_abort); qemu_chr_fe_set_handlers(&s->chr, gdb_chr_can_receive, gdb_chr_receive, - gdb_chr_event, NULL, NULL, NULL, true); + gdb_chr_event, NULL, s, NULL, true); } s->state = chr ? RS_IDLE : RS_INACTIVE; s->mon_chr = mon_chr; diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index 8004afe45b..cbacea5fbd 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -75,7 +75,9 @@ static void cpu_irq_change(AlphaCPU *cpu, uint64_t req) } } -static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) +static MemTxResult cchip_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) { CPUState *cpu = current_cpu; TyphoonState *s = opaque; @@ -196,11 +198,11 @@ static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) break; default: - cpu_unassigned_access(cpu, addr, false, false, 0, size); - return -1; + return MEMTX_ERROR; } - return ret; + *data = ret; + return MEMTX_OK; } static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size) @@ -209,7 +211,8 @@ static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size) return 0; } -static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size) +static MemTxResult pchip_read(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) { TyphoonState *s = opaque; uint64_t ret = 0; @@ -294,15 +297,16 @@ static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size) break; default: - cpu_unassigned_access(current_cpu, addr, false, false, 0, size); - return -1; + return MEMTX_ERROR; } - return ret; + *data = ret; + return MEMTX_OK; } -static void cchip_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static MemTxResult cchip_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { TyphoonState *s = opaque; uint64_t oldval, newval; @@ -446,9 +450,10 @@ static void cchip_write(void *opaque, hwaddr addr, break; default: - cpu_unassigned_access(current_cpu, addr, true, false, 0, size); - return; + return MEMTX_ERROR; } + + return MEMTX_OK; } static void dchip_write(void *opaque, hwaddr addr, @@ -457,8 +462,9 @@ static void dchip_write(void *opaque, hwaddr addr, /* Skip this. It's all related to DRAM timing and setup. */ } -static void pchip_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static MemTxResult pchip_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { TyphoonState *s = opaque; uint64_t oldval; @@ -553,14 +559,15 @@ static void pchip_write(void *opaque, hwaddr addr, break; default: - cpu_unassigned_access(current_cpu, addr, true, false, 0, size); - return; + return MEMTX_ERROR; } + + return MEMTX_OK; } static const MemoryRegionOps cchip_ops = { - .read = cchip_read, - .write = cchip_write, + .read_with_attrs = cchip_read, + .write_with_attrs = cchip_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = { .min_access_size = 8, @@ -587,8 +594,8 @@ static const MemoryRegionOps dchip_ops = { }; static const MemoryRegionOps pchip_ops = { - .read = pchip_read, - .write = pchip_write, + .read_with_attrs = pchip_read, + .write_with_attrs = pchip_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = { .min_access_size = 8, diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 9fe875cdb5..df0d079ad0 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -22,6 +22,7 @@ #include "hw/sysbus.h" #include "hw/devices.h" #include "hw/arm/allwinner-a10.h" +#include "hw/misc/unimp.h" static void aw_a10_init(Object *obj) { @@ -85,6 +86,11 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(sysbusdev, 4, s->irq[67]); sysbus_connect_irq(sysbusdev, 5, s->irq[68]); + memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB, + &error_fatal); + memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a); + create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB); + /* FIXME use qdev NIC properties instead of nd_table[] */ if (nd_table[0].used) { qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC); diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 4bf9131b81..f444652830 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -285,11 +285,6 @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) big_endian = 0; #endif - if (!kernel_filename && !qtest_enabled()) { - error_report("Guest image must be specified (using -kernel)"); - exit(1); - } - if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { asidx = ARMASIdx_S; } else { diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 94fce12802..c7a67af7a9 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -30,8 +30,9 @@ * Documentation/arm/Booting and Documentation/arm64/booting.txt * They have different preferred image load offsets from system RAM base. */ -#define KERNEL_ARGS_ADDR 0x100 -#define KERNEL_LOAD_ADDR 0x00010000 +#define KERNEL_ARGS_ADDR 0x100 +#define KERNEL_NOLOAD_ADDR 0x02000000 +#define KERNEL_LOAD_ADDR 0x00010000 #define KERNEL64_LOAD_ADDR 0x00080000 #define ARM64_TEXT_OFFSET_OFFSET 8 @@ -1082,7 +1083,8 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) } entry = elf_entry; if (kernel_size < 0) { - kernel_size = load_uimage_as(info->kernel_filename, &entry, NULL, + uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR; + kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr, &is_linux, NULL, NULL, as); } if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) { diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index b89c1bdea0..1630c27594 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -21,35 +21,46 @@ #include "qemu/log.h" #include "cpu.h" +#include "hw/arm/nrf51.h" #include "hw/arm/nrf51_soc.h" -#define IOMEM_BASE 0x40000000 -#define IOMEM_SIZE 0x20000000 - -#define FICR_BASE 0x10000000 -#define FICR_SIZE 0x000000fc - -#define FLASH_BASE 0x00000000 -#define SRAM_BASE 0x20000000 - -#define PRIVATE_BASE 0xF0000000 -#define PRIVATE_SIZE 0x10000000 - /* * The size and base is for the NRF51822 part. If other parts * are supported in the future, add a sub-class of NRF51SoC for * the specific variants */ -#define NRF51822_FLASH_SIZE (256 * 1024) -#define NRF51822_SRAM_SIZE (16 * 1024) +#define NRF51822_FLASH_SIZE (256 * NRF51_PAGE_SIZE) +#define NRF51822_SRAM_SIZE (16 * NRF51_PAGE_SIZE) #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) +static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", + __func__, addr, size); + return 1; +} + +static void clock_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", + __func__, addr, data, size); +} + +static const MemoryRegionOps clock_ops = { + .read = clock_read, + .write = clock_write +}; + + static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) { NRF51State *s = NRF51_SOC(dev_soc); MemoryRegion *mr; Error *err = NULL; + uint8_t i = 0; + hwaddr base_addr = 0; if (!s->board_memory) { error_setg(errp, "memory property was not set"); @@ -76,14 +87,14 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) error_propagate(errp, err); return; } - memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash); + memory_region_add_subregion(&s->container, NRF51_FLASH_BASE, &s->flash); memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &err); if (err) { error_propagate(errp, err); return; } - memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram); + memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram); /* UART */ object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); @@ -92,19 +103,71 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) return; } mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); - memory_region_add_subregion_overlap(&s->container, UART_BASE, mr, 0); + memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, qdev_get_gpio_in(DEVICE(&s->cpu), - BASE_TO_IRQ(UART_BASE))); + BASE_TO_IRQ(NRF51_UART_BASE))); + + /* RNG */ + object_property_set_bool(OBJECT(&s->rng), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); + memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, + qdev_get_gpio_in(DEVICE(&s->cpu), + BASE_TO_IRQ(NRF51_RNG_BASE))); + + /* GPIO */ + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0); + memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0); + + /* Pass all GPIOs to the SOC layer so they are available to the board */ + qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); + + /* TIMER */ + for (i = 0; i < NRF51_NUM_TIMERS; i++) { + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE; - create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE); - create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, + qdev_get_gpio_in(DEVICE(&s->cpu), + BASE_TO_IRQ(base_addr))); + } + + /* STUB Peripherals */ + memory_region_init_io(&s->clock, NULL, &clock_ops, NULL, + "nrf51_soc.clock", 0x1000); + memory_region_add_subregion_overlap(&s->container, + NRF51_IOMEM_BASE, &s->clock, -1); + + create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, + NRF51_IOMEM_SIZE); + create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, + NRF51_FICR_SIZE); create_unimplemented_device("nrf51_soc.private", - PRIVATE_BASE, PRIVATE_SIZE); + NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); } static void nrf51_soc_init(Object *obj) { + uint8_t i = 0; + NRF51State *s = NRF51_SOC(obj); memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); @@ -119,6 +182,18 @@ static void nrf51_soc_init(Object *obj) TYPE_NRF51_UART); object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev", &error_abort); + + sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng), + TYPE_NRF51_RNG); + + sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), + TYPE_NRF51_GPIO); + + for (i = 0; i < NRF51_NUM_TIMERS; i++) { + sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], + sizeof(s->timer[i]), TYPE_NRF51_TIMER); + + } } static Property nrf51_soc_properties[] = { diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c2641e56ea..99c2b6e60d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -43,7 +43,6 @@ #include "sysemu/numa.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" -#include "hw/compat.h" #include "hw/loader.h" #include "exec/address-spaces.h" #include "qemu/bitops.h" @@ -1872,84 +1871,63 @@ static void virt_machine_4_0_options(MachineClass *mc) } DEFINE_VIRT_MACHINE_AS_LATEST(4, 0) -#define VIRT_COMPAT_3_1 \ - HW_COMPAT_3_1 - static void virt_machine_3_1_options(MachineClass *mc) { virt_machine_4_0_options(mc); - SET_MACHINE_COMPAT(mc, VIRT_COMPAT_3_1); + compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); } DEFINE_VIRT_MACHINE(3, 1) -#define VIRT_COMPAT_3_0 \ - HW_COMPAT_3_0 - static void virt_machine_3_0_options(MachineClass *mc) { virt_machine_3_1_options(mc); - SET_MACHINE_COMPAT(mc, VIRT_COMPAT_3_0); + compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); } DEFINE_VIRT_MACHINE(3, 0) -#define VIRT_COMPAT_2_12 \ - HW_COMPAT_2_12 - static void virt_machine_2_12_options(MachineClass *mc) { VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); virt_machine_3_0_options(mc); - SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_12); + compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); vmc->no_highmem_ecam = true; mc->max_cpus = 255; } DEFINE_VIRT_MACHINE(2, 12) -#define VIRT_COMPAT_2_11 \ - HW_COMPAT_2_11 - static void virt_machine_2_11_options(MachineClass *mc) { VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); virt_machine_2_12_options(mc); - SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_11); + compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); vmc->smbios_old_sys_ver = true; } DEFINE_VIRT_MACHINE(2, 11) -#define VIRT_COMPAT_2_10 \ - HW_COMPAT_2_10 - static void virt_machine_2_10_options(MachineClass *mc) { virt_machine_2_11_options(mc); - SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_10); + compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); /* before 2.11 we never faulted accesses to bad addresses */ mc->ignore_memory_transaction_failures = true; } DEFINE_VIRT_MACHINE(2, 10) -#define VIRT_COMPAT_2_9 \ - HW_COMPAT_2_9 - static void virt_machine_2_9_options(MachineClass *mc) { virt_machine_2_10_options(mc); - SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9); + compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); } DEFINE_VIRT_MACHINE(2, 9) -#define VIRT_COMPAT_2_8 \ - HW_COMPAT_2_8 - static void virt_machine_2_8_options(MachineClass *mc) { VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); virt_machine_2_9_options(mc); - SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8); + compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); /* For 2.8 and earlier we falsely claimed in the DT that * our timers were edge-triggered, not level-triggered. */ @@ -1957,15 +1935,12 @@ static void virt_machine_2_8_options(MachineClass *mc) } DEFINE_VIRT_MACHINE(2, 8) -#define VIRT_COMPAT_2_7 \ - HW_COMPAT_2_7 - static void virt_machine_2_7_options(MachineClass *mc) { VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); virt_machine_2_8_options(mc); - SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7); + compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); /* ITS was introduced with 2.8 */ vmc->no_its = true; /* Stick with 1K pages for migration compatibility */ @@ -1973,15 +1948,12 @@ static void virt_machine_2_7_options(MachineClass *mc) } DEFINE_VIRT_MACHINE(2, 7) -#define VIRT_COMPAT_2_6 \ - HW_COMPAT_2_6 - static void virt_machine_2_6_options(MachineClass *mc) { VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); virt_machine_2_7_options(mc); - SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); + compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); vmc->disallow_affinity_adjustment = true; /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ vmc->no_pmu = true; diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index c6feeac532..f95fde2309 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -130,6 +130,7 @@ static void fdt_add_gic_nodes(VersalVirt *s) 2, MM_GIC_APU_REDIST_0_SIZE); qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3); qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3"); + g_free(nodename); } static void fdt_add_timer_nodes(VersalVirt *s) @@ -364,6 +365,7 @@ static void create_virtio_regions(VersalVirt *s) sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq); mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); memory_region_add_subregion(&s->soc.mr_ps, base, mr); + g_free(name); } for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index c195040350..c67ac2e64a 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -178,12 +178,19 @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu, int i; int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS); + object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, + sizeof(s->rpu_cluster), TYPE_CPU_CLUSTER, + &error_abort, NULL); + qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); + + qdev_init_nofail(DEVICE(&s->rpu_cluster)); + for (i = 0; i < num_rpus; i++) { char *name; object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), "cortex-r5f-" TYPE_ARM_CPU); - object_property_add_child(OBJECT(s), "rpu-cpu[*]", + object_property_add_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]), &error_abort); name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); @@ -213,10 +220,16 @@ static void xlnx_zynqmp_init(Object *obj) int i; int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS); + object_initialize_child(obj, "apu-cluster", &s->apu_cluster, + sizeof(s->apu_cluster), TYPE_CPU_CLUSTER, + &error_abort, NULL); + qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); + for (i = 0; i < num_apus; i++) { - object_initialize_child(obj, "apu-cpu[*]", &s->apu_cpu[i], - sizeof(s->apu_cpu[i]), - "cortex-a53-" TYPE_ARM_CPU, &error_abort, NULL); + object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", + &s->apu_cpu[i], sizeof(s->apu_cpu[i]), + "cortex-a53-" TYPE_ARM_CPU, &error_abort, + NULL); } sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), @@ -333,6 +346,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", s->virt); + qdev_init_nofail(DEVICE(&s->apu_cluster)); + /* Realize APUs before realizing the GIC. KVM requires this. */ for (i = 0; i < num_apus; i++) { char *name; diff --git a/hw/core/loader.c b/hw/core/loader.c index fa41842280..c7182dfa64 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -613,13 +613,26 @@ static int load_uboot_image(const char *filename, hwaddr *ep, hwaddr *loadaddr, goto out; if (hdr->ih_type != image_type) { - fprintf(stderr, "Wrong image type %d, expected %d\n", hdr->ih_type, - image_type); - goto out; + if (!(image_type == IH_TYPE_KERNEL && + hdr->ih_type == IH_TYPE_KERNEL_NOLOAD)) { + fprintf(stderr, "Wrong image type %d, expected %d\n", hdr->ih_type, + image_type); + goto out; + } } /* TODO: Implement other image types. */ switch (hdr->ih_type) { + case IH_TYPE_KERNEL_NOLOAD: + if (!loadaddr || *loadaddr == LOAD_UIMAGE_LOADADDR_INVALID) { + fprintf(stderr, "this image format (kernel_noload) cannot be " + "loaded on this machine type"); + goto out; + } + + hdr->ih_load = *loadaddr + sizeof(*hdr); + hdr->ih_ep += hdr->ih_load; + /* fall through */ case IH_TYPE_KERNEL: address = hdr->ih_load; if (translate_fn) { diff --git a/hw/core/machine.c b/hw/core/machine.c index 4439ea663f..1a0a9ab111 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -21,6 +21,334 @@ #include "sysemu/numa.h" #include "qemu/error-report.h" #include "sysemu/qtest.h" +#include "hw/pci/pci.h" + +GlobalProperty hw_compat_3_1[] = { + { + .driver = "pcie-root-port", + .property = "x-speed", + .value = "2_5", + },{ + .driver = "pcie-root-port", + .property = "x-width", + .value = "1", + },{ + .driver = "memory-backend-file", + .property = "x-use-canonical-path-for-ramblock-id", + .value = "true", + },{ + .driver = "memory-backend-memfd", + .property = "x-use-canonical-path-for-ramblock-id", + .value = "true", + }, +}; +const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1); + +GlobalProperty hw_compat_3_0[] = {}; +const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0); + +GlobalProperty hw_compat_2_12[] = { + { + .driver = "migration", + .property = "decompress-error-check", + .value = "off", + },{ + .driver = "hda-audio", + .property = "use-timer", + .value = "false", + },{ + .driver = "cirrus-vga", + .property = "global-vmstate", + .value = "true", + },{ + .driver = "VGA", + .property = "global-vmstate", + .value = "true", + },{ + .driver = "vmware-svga", + .property = "global-vmstate", + .value = "true", + },{ + .driver = "qxl-vga", + .property = "global-vmstate", + .value = "true", + }, +}; +const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12); + +GlobalProperty hw_compat_2_11[] = { + { + .driver = "hpet", + .property = "hpet-offset-saved", + .value = "false", + },{ + .driver = "virtio-blk-pci", + .property = "vectors", + .value = "2", + },{ + .driver = "vhost-user-blk-pci", + .property = "vectors", + .value = "2", + },{ + .driver = "e1000", + .property = "migrate_tso_props", + .value = "off", + }, +}; +const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11); + +GlobalProperty hw_compat_2_10[] = { + { + .driver = "virtio-mouse-device", + .property = "wheel-axis", + .value = "false", + },{ + .driver = "virtio-tablet-device", + .property = "wheel-axis", + .value = "false", + }, +}; +const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10); + +GlobalProperty hw_compat_2_9[] = { + { + .driver = "pci-bridge", + .property = "shpc", + .value = "off", + },{ + .driver = "intel-iommu", + .property = "pt", + .value = "off", + },{ + .driver = "virtio-net-device", + .property = "x-mtu-bypass-backend", + .value = "off", + },{ + .driver = "pcie-root-port", + .property = "x-migrate-msix", + .value = "false", + }, +}; +const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9); + +GlobalProperty hw_compat_2_8[] = { + { + .driver = "fw_cfg_mem", + .property = "x-file-slots", + .value = stringify(0x10), + },{ + .driver = "fw_cfg_io", + .property = "x-file-slots", + .value = stringify(0x10), + },{ + .driver = "pflash_cfi01", + .property = "old-multiple-chip-handling", + .value = "on", + },{ + .driver = "pci-bridge", + .property = "shpc", + .value = "on", + },{ + .driver = TYPE_PCI_DEVICE, + .property = "x-pcie-extcap-init", + .value = "off", + },{ + .driver = "virtio-pci", + .property = "x-pcie-deverr-init", + .value = "off", + },{ + .driver = "virtio-pci", + .property = "x-pcie-lnkctl-init", + .value = "off", + },{ + .driver = "virtio-pci", + .property = "x-pcie-pm-init", + .value = "off", + },{ + .driver = "cirrus-vga", + .property = "vgamem_mb", + .value = "8", + },{ + .driver = "isa-cirrus-vga", + .property = "vgamem_mb", + .value = "8", + }, +}; +const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8); + +GlobalProperty hw_compat_2_7[] = { + { + .driver = "virtio-pci", + .property = "page-per-vq", + .value = "on", + },{ + .driver = "virtio-serial-device", + .property = "emergency-write", + .value = "off", + },{ + .driver = "ioapic", + .property = "version", + .value = "0x11", + },{ + .driver = "intel-iommu", + .property = "x-buggy-eim", + .value = "true", + },{ + .driver = "virtio-pci", + .property = "x-ignore-backend-features", + .value = "on", + }, +}; +const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7); + +GlobalProperty hw_compat_2_6[] = { + { + .driver = "virtio-mmio", + .property = "format_transport_address", + .value = "off", + },{ + .driver = "virtio-pci", + .property = "disable-modern", + .value = "on", + },{ + .driver = "virtio-pci", + .property = "disable-legacy", + .value = "off", + }, +}; +const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6); + +GlobalProperty hw_compat_2_5[] = { + { + .driver = "isa-fdc", + .property = "fallback", + .value = "144", + },{ + .driver = "pvscsi", + .property = "x-old-pci-configuration", + .value = "on", + },{ + .driver = "pvscsi", + .property = "x-disable-pcie", + .value = "on", + }, + { + .driver = "vmxnet3", + .property = "x-old-msi-offsets", + .value = "on", + },{ + .driver = "vmxnet3", + .property = "x-disable-pcie", + .value = "on", + }, +}; +const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5); + +GlobalProperty hw_compat_2_4[] = { + { + .driver = "virtio-blk-device", + .property = "scsi", + .value = "true", + },{ + .driver = "e1000", + .property = "extra_mac_registers", + .value = "off", + },{ + .driver = "virtio-pci", + .property = "x-disable-pcie", + .value = "on", + },{ + .driver = "virtio-pci", + .property = "migrate-extra", + .value = "off", + },{ + .driver = "fw_cfg_mem", + .property = "dma_enabled", + .value = "off", + },{ + .driver = "fw_cfg_io", + .property = "dma_enabled", + .value = "off", + } +}; +const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4); + +GlobalProperty hw_compat_2_3[] = { + { + .driver = "virtio-blk-pci", + .property = "any_layout", + .value = "off", + },{ + .driver = "virtio-balloon-pci", + .property = "any_layout", + .value = "off", + },{ + .driver = "virtio-serial-pci", + .property = "any_layout", + .value = "off", + },{ + .driver = "virtio-9p-pci", + .property = "any_layout", + .value = "off", + },{ + .driver = "virtio-rng-pci", + .property = "any_layout", + .value = "off", + },{ + .driver = TYPE_PCI_DEVICE, + .property = "x-pcie-lnksta-dllla", + .value = "off", + },{ + .driver = "migration", + .property = "send-configuration", + .value = "off", + },{ + .driver = "migration", + .property = "send-section-footer", + .value = "off", + },{ + .driver = "migration", + .property = "store-global-state", + .value = "off", + }, +}; +const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3); + +GlobalProperty hw_compat_2_2[] = {}; +const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2); + +GlobalProperty hw_compat_2_1[] = { + { + .driver = "intel-hda", + .property = "old_msi_addr", + .value = "on", + },{ + .driver = "VGA", + .property = "qemu-extended-regs", + .value = "off", + },{ + .driver = "secondary-vga", + .property = "qemu-extended-regs", + .value = "off", + },{ + .driver = "virtio-scsi-pci", + .property = "any_layout", + .value = "off", + },{ + .driver = "usb-mouse", + .property = "usb_version", + .value = stringify(1), + },{ + .driver = "usb-kbd", + .property = "usb_version", + .value = stringify(1), + },{ + .driver = "virtio-pci", + .property = "virtio-pci-bus-master-bug-migration", + .value = "on", + }, +}; +const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1); static char *machine_get_accel(Object *obj, Error **errp) { @@ -591,7 +919,7 @@ static void machine_class_init(ObjectClass *oc, void *data) object_class_property_add_bool(oc, "dump-guest-core", machine_get_dump_guest_core, machine_set_dump_guest_core, &error_abort); object_class_property_set_description(oc, "dump-guest-core", - "Include guest memory in a core dump", &error_abort); + "Include guest memory in a core dump", &error_abort); object_class_property_add_bool(oc, "mem-merge", machine_get_mem_merge, machine_set_mem_merge, &error_abort); @@ -647,6 +975,7 @@ static void machine_class_base_init(ObjectClass *oc, void *data) assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX)); mc->name = g_strndup(cname, strlen(cname) - strlen(TYPE_MACHINE_SUFFIX)); + mc->compat_props = g_ptr_array_new(); } } @@ -836,24 +1165,6 @@ void machine_run_board_init(MachineState *machine) machine_class->init(machine); } -void machine_register_compat_props(MachineState *machine) -{ - MachineClass *mc = MACHINE_GET_CLASS(machine); - int i; - GlobalProperty *p; - - if (!mc->compat_props) { - return; - } - - for (i = 0; i < mc->compat_props->len; i++) { - p = g_array_index(mc->compat_props, GlobalProperty *, i); - /* Machine compat_props must never cause errors: */ - p->errp = &error_abort; - qdev_prop_register_global(p); - } -} - static const TypeInfo machine_info = { .name = TYPE_MACHINE, .parent = TYPE_OBJECT, diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c index 943dc2654b..5da1439a8b 100644 --- a/hw/core/qdev-properties.c +++ b/hw/core/qdev-properties.c @@ -1173,28 +1173,35 @@ void qdev_prop_set_ptr(DeviceState *dev, const char *name, void *value) *ptr = value; } -static GList *global_props; +static GPtrArray *global_props(void) +{ + static GPtrArray *gp; + + if (!gp) { + gp = g_ptr_array_new(); + } + + return gp; +} void qdev_prop_register_global(GlobalProperty *prop) { - global_props = g_list_append(global_props, prop); + g_ptr_array_add(global_props(), prop); } int qdev_prop_check_globals(void) { - GList *l; - int ret = 0; + int i, ret = 0; - for (l = global_props; l; l = l->next) { - GlobalProperty *prop = l->data; + for (i = 0; i < global_props()->len; i++) { + GlobalProperty *prop; ObjectClass *oc; DeviceClass *dc; + + prop = g_ptr_array_index(global_props(), i); if (prop->used) { continue; } - if (!prop->user_provided) { - continue; - } oc = object_class_by_name(prop->driver); oc = object_class_dynamic_cast(oc, TYPE_DEVICE); if (!oc) { @@ -1216,28 +1223,8 @@ int qdev_prop_check_globals(void) void qdev_prop_set_globals(DeviceState *dev) { - GList *l; - - for (l = global_props; l; l = l->next) { - GlobalProperty *prop = l->data; - Error *err = NULL; - - if (object_dynamic_cast(OBJECT(dev), prop->driver) == NULL) { - continue; - } - prop->used = true; - object_property_parse(OBJECT(dev), prop->value, prop->property, &err); - if (err != NULL) { - error_prepend(&err, "can't apply global %s.%s=%s: ", - prop->driver, prop->property, prop->value); - if (!dev->hotplugged && prop->errp) { - error_propagate(prop->errp, err); - } else { - assert(prop->user_provided); - warn_report_err(err); - } - } - } + object_apply_global_props(OBJECT(dev), global_props(), + dev->hotplugged ? NULL : &error_fatal); } /* --- 64bit unsigned int 'size' type --- */ diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 6b3cc55b27..3769a2bccb 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -970,8 +970,23 @@ static void device_initfn(Object *obj) QLIST_INIT(&dev->gpios); } +void object_apply_compat_props(Object *obj) +{ + if (object_dynamic_cast(qdev_get_machine(), TYPE_MACHINE)) { + MachineState *m = MACHINE(qdev_get_machine()); + MachineClass *mc = MACHINE_GET_CLASS(m); + AccelClass *ac = ACCEL_GET_CLASS(m->accelerator); + + if (ac->compat_props) { + object_apply_global_props(obj, ac->compat_props, &error_abort); + } + object_apply_global_props(obj, mc->compat_props, &error_abort); + } +} + static void device_post_init(Object *obj) { + object_apply_compat_props(obj); qdev_prop_set_globals(DEVICE(obj)); } diff --git a/hw/core/uboot_image.h b/hw/core/uboot_image.h index 34c11a70a6..608022de6e 100644 --- a/hw/core/uboot_image.h +++ b/hw/core/uboot_image.h @@ -124,6 +124,7 @@ #define IH_TYPE_SCRIPT 6 /* Script file */ #define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ #define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ +#define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image (noload) */ /* * Compression Types diff --git a/hw/cpu/Makefile.objs b/hw/cpu/Makefile.objs index cd52d20b65..8db9e8a7b3 100644 --- a/hw/cpu/Makefile.objs +++ b/hw/cpu/Makefile.objs @@ -2,4 +2,4 @@ obj-$(CONFIG_ARM11MPCORE) += arm11mpcore.o obj-$(CONFIG_REALVIEW) += realview_mpcore.o obj-$(CONFIG_A9MPCORE) += a9mpcore.o obj-$(CONFIG_A15MPCORE) += a15mpcore.o -common-obj-y += core.o +common-obj-y += core.o cluster.o diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c new file mode 100644 index 0000000000..9d50a235d5 --- /dev/null +++ b/hw/cpu/cluster.c @@ -0,0 +1,50 @@ +/* + * QEMU CPU cluster + * + * Copyright (c) 2018 GreenSocs SAS + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * <http://www.gnu.org/licenses/gpl-2.0.html> + */ + +#include "qemu/osdep.h" +#include "hw/cpu/cluster.h" +#include "qapi/error.h" +#include "qemu/module.h" + +static Property cpu_cluster_properties[] = { + DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void cpu_cluster_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->props = cpu_cluster_properties; +} + +static const TypeInfo cpu_cluster_type_info = { + .name = TYPE_CPU_CLUSTER, + .parent = TYPE_DEVICE, + .instance_size = sizeof(CPUClusterState), + .class_init = cpu_cluster_class_init, +}; + +static void cpu_cluster_register_types(void) +{ + type_register_static(&cpu_cluster_type_info); +} + +type_init(cpu_cluster_register_types) diff --git a/hw/display/qxl.c b/hw/display/qxl.c index 9087db5dee..8e9a65e75b 100644 --- a/hw/display/qxl.c +++ b/hw/display/qxl.c @@ -1189,9 +1189,7 @@ static void qxl_enter_vga_mode(PCIQXLDevice *d) return; } trace_qxl_enter_vga_mode(d->id); -#if SPICE_SERVER_VERSION >= 0x000c03 /* release 0.12.3 */ spice_qxl_driver_unload(&d->ssd.qxl); -#endif graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga); update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT); qemu_spice_create_host_primary(&d->ssd); diff --git a/hw/display/ramfb-standalone.c b/hw/display/ramfb-standalone.c index c0d241ba01..da3229a1f6 100644 --- a/hw/display/ramfb-standalone.c +++ b/hw/display/ramfb-standalone.c @@ -1,7 +1,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/loader.h" -#include "hw/isa/isa.h" #include "hw/display/ramfb.h" #include "ui/console.h" #include "sysemu/sysemu.h" diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs index fa0a72e6d0..e5da0cb54f 100644 --- a/hw/gpio/Makefile.objs +++ b/hw/gpio/Makefile.objs @@ -8,3 +8,4 @@ common-obj-$(CONFIG_GPIO_KEY) += gpio_key.o obj-$(CONFIG_OMAP) += omap_gpio.o obj-$(CONFIG_IMX) += imx_gpio.o obj-$(CONFIG_RASPI) += bcm2835_gpio.o +obj-$(CONFIG_NRF51_SOC) += nrf51_gpio.o diff --git a/hw/gpio/nrf51_gpio.c b/hw/gpio/nrf51_gpio.c new file mode 100644 index 0000000000..86e047d649 --- /dev/null +++ b/hw/gpio/nrf51_gpio.c @@ -0,0 +1,300 @@ +/* + * nRF51 System-on-Chip general purpose input/output register definition + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf + * + * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de> + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/gpio/nrf51_gpio.h" +#include "trace.h" + +/* + * Check if the output driver is connected to the direction switch + * given the current configuration and logic level. + * It is not differentiated between standard and "high"(-power) drive modes. + */ +static bool is_connected(uint32_t config, uint32_t level) +{ + bool state; + uint32_t drive_config = extract32(config, 8, 3); + + switch (drive_config) { + case 0 ... 3: + state = true; + break; + case 4 ... 5: + state = level != 0; + break; + case 6 ... 7: + state = level == 0; + break; + default: + g_assert_not_reached(); + break; + } + + return state; +} + +static void update_output_irq(NRF51GPIOState *s, size_t i, + bool connected, bool level) +{ + int64_t irq_level = connected ? level : -1; + bool old_connected = extract32(s->old_out_connected, i, 1); + bool old_level = extract32(s->old_out, i, 1); + + if ((old_connected != connected) || (old_level != level)) { + qemu_set_irq(s->output[i], irq_level); + trace_nrf51_gpio_update_output_irq(i, irq_level); + } + + s->old_out = deposit32(s->old_out, i, 1, level); + s->old_out_connected = deposit32(s->old_out_connected, i, 1, connected); +} + +static void update_state(NRF51GPIOState *s) +{ + uint32_t pull; + size_t i; + bool connected_out, dir, connected_in, out, input; + + for (i = 0; i < NRF51_GPIO_PINS; i++) { + pull = extract32(s->cnf[i], 2, 2); + dir = extract32(s->cnf[i], 0, 1); + connected_in = extract32(s->in_mask, i, 1); + out = extract32(s->out, i, 1); + input = !extract32(s->cnf[i], 1, 1); + connected_out = is_connected(s->cnf[i], out) && dir; + + update_output_irq(s, i, connected_out, out); + + /* Pin both driven externally and internally */ + if (connected_out && connected_in) { + qemu_log_mask(LOG_GUEST_ERROR, "GPIO pin %zu short circuited\n", i); + } + + /* + * Input buffer disconnected from internal/external drives, so + * pull-up/pull-down becomes relevant + */ + if (!input || (input && !connected_in && !connected_out)) { + if (pull == NRF51_GPIO_PULLDOWN) { + s->in = deposit32(s->in, i, 1, 0); + } else if (pull == NRF51_GPIO_PULLUP) { + s->in = deposit32(s->in, i, 1, 1); + } + } + + /* Self stimulation through internal output driver */ + if (connected_out && !connected_in && input) { + s->in = deposit32(s->in, i, 1, out); + } + } + +} + +/* + * Direction is exposed in both the DIR register and the DIR bit + * of each PINs CNF configuration register. Reflect bits for pins in DIR + * to individual pin configuration registers. + */ +static void reflect_dir_bit_in_cnf(NRF51GPIOState *s) +{ + size_t i; + + uint32_t value = s->dir; + + for (i = 0; i < NRF51_GPIO_PINS; i++) { + s->cnf[i] = (s->cnf[i] & ~(1UL)) | ((value >> i) & 0x01); + } +} + +static uint64_t nrf51_gpio_read(void *opaque, hwaddr offset, unsigned int size) +{ + NRF51GPIOState *s = NRF51_GPIO(opaque); + uint64_t r = 0; + size_t idx; + + switch (offset) { + case NRF51_GPIO_REG_OUT ... NRF51_GPIO_REG_OUTCLR: + r = s->out; + break; + + case NRF51_GPIO_REG_IN: + r = s->in; + break; + + case NRF51_GPIO_REG_DIR ... NRF51_GPIO_REG_DIRCLR: + r = s->dir; + break; + + case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END: + idx = (offset - NRF51_GPIO_REG_CNF_START) / 4; + r = s->cnf[idx]; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad read offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + trace_nrf51_gpio_read(offset, r); + + return r; +} + +static void nrf51_gpio_write(void *opaque, hwaddr offset, + uint64_t value, unsigned int size) +{ + NRF51GPIOState *s = NRF51_GPIO(opaque); + size_t idx; + + trace_nrf51_gpio_write(offset, value); + + switch (offset) { + case NRF51_GPIO_REG_OUT: + s->out = value; + break; + + case NRF51_GPIO_REG_OUTSET: + s->out |= value; + break; + + case NRF51_GPIO_REG_OUTCLR: + s->out &= ~value; + break; + + case NRF51_GPIO_REG_DIR: + s->dir = value; + reflect_dir_bit_in_cnf(s); + break; + + case NRF51_GPIO_REG_DIRSET: + s->dir |= value; + reflect_dir_bit_in_cnf(s); + break; + + case NRF51_GPIO_REG_DIRCLR: + s->dir &= ~value; + reflect_dir_bit_in_cnf(s); + break; + + case NRF51_GPIO_REG_CNF_START ... NRF51_GPIO_REG_CNF_END: + idx = (offset - NRF51_GPIO_REG_CNF_START) / 4; + s->cnf[idx] = value; + /* + * direction is exposed in both the DIR register and the DIR bit + * of each PINs CNF configuration register. + */ + s->dir = (s->dir & ~(1UL << idx)) | ((value & 0x01) << idx); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad write offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + update_state(s); +} + +static const MemoryRegionOps gpio_ops = { + .read = nrf51_gpio_read, + .write = nrf51_gpio_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4, +}; + +static void nrf51_gpio_set(void *opaque, int line, int value) +{ + NRF51GPIOState *s = NRF51_GPIO(opaque); + + trace_nrf51_gpio_set(line, value); + + assert(line >= 0 && line < NRF51_GPIO_PINS); + + s->in_mask = deposit32(s->in_mask, line, 1, value >= 0); + if (value >= 0) { + s->in = deposit32(s->in, line, 1, value != 0); + } + + update_state(s); +} + +static void nrf51_gpio_reset(DeviceState *dev) +{ + NRF51GPIOState *s = NRF51_GPIO(dev); + size_t i; + + s->out = 0; + s->old_out = 0; + s->old_out_connected = 0; + s->in = 0; + s->in_mask = 0; + s->dir = 0; + + for (i = 0; i < NRF51_GPIO_PINS; i++) { + s->cnf[i] = 0x00000002; + } +} + +static const VMStateDescription vmstate_nrf51_gpio = { + .name = TYPE_NRF51_GPIO, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(out, NRF51GPIOState), + VMSTATE_UINT32(in, NRF51GPIOState), + VMSTATE_UINT32(in_mask, NRF51GPIOState), + VMSTATE_UINT32(dir, NRF51GPIOState), + VMSTATE_UINT32_ARRAY(cnf, NRF51GPIOState, NRF51_GPIO_PINS), + VMSTATE_UINT32(old_out, NRF51GPIOState), + VMSTATE_UINT32(old_out_connected, NRF51GPIOState), + VMSTATE_END_OF_LIST() + } +}; + +static void nrf51_gpio_init(Object *obj) +{ + NRF51GPIOState *s = NRF51_GPIO(obj); + + memory_region_init_io(&s->mmio, obj, &gpio_ops, s, + TYPE_NRF51_GPIO, NRF51_GPIO_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + qdev_init_gpio_in(DEVICE(s), nrf51_gpio_set, NRF51_GPIO_PINS); + qdev_init_gpio_out(DEVICE(s), s->output, NRF51_GPIO_PINS); +} + +static void nrf51_gpio_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->vmsd = &vmstate_nrf51_gpio; + dc->reset = nrf51_gpio_reset; + dc->desc = "nRF51 GPIO"; +} + +static const TypeInfo nrf51_gpio_info = { + .name = TYPE_NRF51_GPIO, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NRF51GPIOState), + .instance_init = nrf51_gpio_init, + .class_init = nrf51_gpio_class_init +}; + +static void nrf51_gpio_register_types(void) +{ + type_register_static(&nrf51_gpio_info); +} + +type_init(nrf51_gpio_register_types) diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events new file mode 100644 index 0000000000..cb41a89756 --- /dev/null +++ b/hw/gpio/trace-events @@ -0,0 +1,7 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# hw/gpio/nrf51_gpio.c +nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64 +nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64 +nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 +nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
\ No newline at end of file diff --git a/hw/i386/kvm/ioapic.c b/hw/i386/kvm/ioapic.c index 5b40d75439..e453692199 100644 --- a/hw/i386/kvm/ioapic.c +++ b/hw/i386/kvm/ioapic.c @@ -163,7 +163,7 @@ static void kvm_ioapic_class_init(ObjectClass *klass, void *data) } static const TypeInfo kvm_ioapic_info = { - .name = "kvm-ioapic", + .name = TYPE_KVM_IOAPIC, .parent = TYPE_IOAPIC_COMMON, .instance_size = sizeof(KVMIOAPICState), .class_init = kvm_ioapic_class_init, diff --git a/hw/i386/pc.c b/hw/i386/pc.c index f248662e97..3c9e20ad9c 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -72,6 +72,7 @@ #include "qapi/visitor.h" #include "qom/cpu.h" #include "hw/nmi.h" +#include "hw/usb.h" #include "hw/i386/intel_iommu.h" #include "hw/net/ne2000-isa.h" @@ -109,6 +110,679 @@ static struct e820_entry *e820_table; static unsigned e820_entries; struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; +GlobalProperty pc_compat_3_1[] = { + { + .driver = "intel-iommu", + .property = "dma-drain", + .value = "off", + }, +}; +const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); + +GlobalProperty pc_compat_3_0[] = { + { + .driver = TYPE_X86_CPU, + .property = "x-hv-synic-kvm-only", + .value = "on", + },{ + .driver = "Skylake-Server" "-" TYPE_X86_CPU, + .property = "pku", + .value = "off", + },{ + .driver = "Skylake-Server-IBRS" "-" TYPE_X86_CPU, + .property = "pku", + .value = "off", + }, +}; +const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); + +GlobalProperty pc_compat_2_12[] = { + { + .driver = TYPE_X86_CPU, + .property = "legacy-cache", + .value = "on", + },{ + .driver = TYPE_X86_CPU, + .property = "topoext", + .value = "off", + },{ + .driver = "EPYC-" TYPE_X86_CPU, + .property = "xlevel", + .value = stringify(0x8000000a), + },{ + .driver = "EPYC-IBPB-" TYPE_X86_CPU, + .property = "xlevel", + .value = stringify(0x8000000a), + }, +}; +const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); + +GlobalProperty pc_compat_2_11[] = { + { + .driver = TYPE_X86_CPU, + .property = "x-migrate-smi-count", + .value = "off", + },{ + .driver = "Skylake-Server" "-" TYPE_X86_CPU, + .property = "clflushopt", + .value = "off", + }, +}; +const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); + +GlobalProperty pc_compat_2_10[] = { + { + .driver = TYPE_X86_CPU, + .property = "x-hv-max-vps", + .value = "0x40", + },{ + .driver = "i440FX-pcihost", + .property = "x-pci-hole64-fix", + .value = "off", + },{ + .driver = "q35-pcihost", + .property = "x-pci-hole64-fix", + .value = "off", + }, +}; +const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); + +GlobalProperty pc_compat_2_9[] = { + { + .driver = "mch", + .property = "extended-tseg-mbytes", + .value = stringify(0), + }, +}; +const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); + +GlobalProperty pc_compat_2_8[] = { + { + .driver = TYPE_X86_CPU, + .property = "tcg-cpuid", + .value = "off", + }, + { + .driver = "kvmclock", + .property = "x-mach-use-reliable-get-clock", + .value = "off", + }, + { + .driver = "ICH9-LPC", + .property = "x-smi-broadcast", + .value = "off", + }, + { + .driver = TYPE_X86_CPU, + .property = "vmware-cpuid-freq", + .value = "off", + }, + { + .driver = "Haswell-" TYPE_X86_CPU, + .property = "stepping", + .value = "1", + }, +}; +const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); + +GlobalProperty pc_compat_2_7[] = { + { + .driver = TYPE_X86_CPU, + .property = "l3-cache", + .value = "off", + }, + { + .driver = TYPE_X86_CPU, + .property = "full-cpuid-auto-level", + .value = "off", + }, + { + .driver = "Opteron_G3" "-" TYPE_X86_CPU, + .property = "family", + .value = "15", + }, + { + .driver = "Opteron_G3" "-" TYPE_X86_CPU, + .property = "model", + .value = "6", + }, + { + .driver = "Opteron_G3" "-" TYPE_X86_CPU, + .property = "stepping", + .value = "1", + }, + { + .driver = "isa-pcspk", + .property = "migrate", + .value = "off", + }, +}; +const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); + +GlobalProperty pc_compat_2_6[] = { + { + .driver = TYPE_X86_CPU, + .property = "cpuid-0xb", + .value = "off", + },{ + .driver = "vmxnet3", + .property = "romfile", + .value = "", + }, + { + .driver = TYPE_X86_CPU, + .property = "fill-mtrr-mask", + .value = "off", + }, + { + .driver = "apic-common", + .property = "legacy-instance-id", + .value = "on", + } +}; +const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); + +GlobalProperty pc_compat_2_5[] = {}; +const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); + +GlobalProperty pc_compat_2_4[] = { + PC_CPU_MODEL_IDS("2.4.0") + { + .driver = "Haswell-" TYPE_X86_CPU, + .property = "abm", + .value = "off", + }, + { + .driver = "Haswell-noTSX-" TYPE_X86_CPU, + .property = "abm", + .value = "off", + }, + { + .driver = "Broadwell-" TYPE_X86_CPU, + .property = "abm", + .value = "off", + }, + { + .driver = "Broadwell-noTSX-" TYPE_X86_CPU, + .property = "abm", + .value = "off", + }, + { + .driver = "host" "-" TYPE_X86_CPU, + .property = "host-cache-info", + .value = "on", + }, + { + .driver = TYPE_X86_CPU, + .property = "check", + .value = "off", + }, + { + .driver = "qemu64" "-" TYPE_X86_CPU, + .property = "sse4a", + .value = "on", + }, + { + .driver = "qemu64" "-" TYPE_X86_CPU, + .property = "abm", + .value = "on", + }, + { + .driver = "qemu64" "-" TYPE_X86_CPU, + .property = "popcnt", + .value = "on", + }, + { + .driver = "qemu32" "-" TYPE_X86_CPU, + .property = "popcnt", + .value = "on", + },{ + .driver = "Opteron_G2" "-" TYPE_X86_CPU, + .property = "rdtscp", + .value = "on", + },{ + .driver = "Opteron_G3" "-" TYPE_X86_CPU, + .property = "rdtscp", + .value = "on", + },{ + .driver = "Opteron_G4" "-" TYPE_X86_CPU, + .property = "rdtscp", + .value = "on", + },{ + .driver = "Opteron_G5" "-" TYPE_X86_CPU, + .property = "rdtscp", + .value = "on", + } +}; +const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); + +GlobalProperty pc_compat_2_3[] = { + PC_CPU_MODEL_IDS("2.3.0") + { + .driver = TYPE_X86_CPU, + .property = "arat", + .value = "off", + },{ + .driver = "qemu64" "-" TYPE_X86_CPU, + .property = "min-level", + .value = stringify(4), + },{ + .driver = "kvm64" "-" TYPE_X86_CPU, + .property = "min-level", + .value = stringify(5), + },{ + .driver = "pentium3" "-" TYPE_X86_CPU, + .property = "min-level", + .value = stringify(2), + },{ + .driver = "n270" "-" TYPE_X86_CPU, + .property = "min-level", + .value = stringify(5), + },{ + .driver = "Conroe" "-" TYPE_X86_CPU, + .property = "min-level", + .value = stringify(4), + },{ + .driver = "Penryn" "-" TYPE_X86_CPU, + .property = "min-level", + .value = stringify(4), + },{ + .driver = "Nehalem" "-" TYPE_X86_CPU, + .property = "min-level", + .value = stringify(4), + },{ + .driver = "n270" "-" TYPE_X86_CPU, + .property = "min-xlevel", + .value = stringify(0x8000000a), + },{ + .driver = "Penryn" "-" TYPE_X86_CPU, + .property = "min-xlevel", + .value = stringify(0x8000000a), + },{ + .driver = "Conroe" "-" TYPE_X86_CPU, + .property = "min-xlevel", + .value = stringify(0x8000000a), + },{ + .driver = "Nehalem" "-" TYPE_X86_CPU, + .property = "min-xlevel", + .value = stringify(0x8000000a), + },{ + .driver = "Westmere" "-" TYPE_X86_CPU, + .property = "min-xlevel", + .value = stringify(0x8000000a), + },{ + .driver = "SandyBridge" "-" TYPE_X86_CPU, + .property = "min-xlevel", + .value = stringify(0x8000000a), + },{ + .driver = "IvyBridge" "-" TYPE_X86_CPU, + .property = "min-xlevel", + .value = stringify(0x8000000a), + },{ + .driver = "Haswell" "-" TYPE_X86_CPU, + .property = "min-xlevel", + .value = stringify(0x8000000a), + },{ + .driver = "Haswell-noTSX" "-" TYPE_X86_CPU, + .property = "min-xlevel", + .value = stringify(0x8000000a), + },{ + .driver = "Broadwell" "-" TYPE_X86_CPU, + .property = "min-xlevel", + .value = stringify(0x8000000a), + },{ + .driver = "Broadwell-noTSX" "-" TYPE_X86_CPU, + .property = "min-xlevel", + .value = stringify(0x8000000a), + },{ + .driver = TYPE_X86_CPU, + .property = "kvm-no-smi-migration", + .value = "on", + }, +}; +const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); + +GlobalProperty pc_compat_2_2[] = { + PC_CPU_MODEL_IDS("2.2.0") + { + .driver = "kvm64" "-" TYPE_X86_CPU, + .property = "vme", + .value = "off", + }, + { + .driver = "kvm32" "-" TYPE_X86_CPU, + .property = "vme", + .value = "off", + }, + { + .driver = "Conroe" "-" TYPE_X86_CPU, + .property = "vme", + .value = "off", + }, + { + .driver = "Penryn" "-" TYPE_X86_CPU, + .property = "vme", + .value = "off", + }, + { + .driver = "Nehalem" "-" TYPE_X86_CPU, + .property = "vme", + .value = "off", + }, + { + .driver = "Westmere" "-" TYPE_X86_CPU, + .property = "vme", + .value = "off", + }, + { + .driver = "SandyBridge" "-" TYPE_X86_CPU, + .property = "vme", + .value = "off", + }, + { + .driver = "Haswell" "-" TYPE_X86_CPU, + .property = "vme", + .value = "off", + }, + { + .driver = "Broadwell" "-" TYPE_X86_CPU, + .property = "vme", + .value = "off", + }, + { + .driver = "Opteron_G1" "-" TYPE_X86_CPU, + .property = "vme", + .value = "off", + }, + { + .driver = "Opteron_G2" "-" TYPE_X86_CPU, + .property = "vme", + .value = "off", + }, + { + .driver = "Opteron_G3" "-" TYPE_X86_CPU, + .property = "vme", + .value = "off", + }, + { + .driver = "Opteron_G4" "-" TYPE_X86_CPU, + .property = "vme", + .value = "off", + }, + { + .driver = "Opteron_G5" "-" TYPE_X86_CPU, + .property = "vme", + .value = "off", + }, + { + .driver = "Haswell" "-" TYPE_X86_CPU, + .property = "f16c", + .value = "off", + }, + { + .driver = "Haswell" "-" TYPE_X86_CPU, + .property = "rdrand", + .value = "off", + }, + { + .driver = "Broadwell" "-" TYPE_X86_CPU, + .property = "f16c", + .value = "off", + }, + { + .driver = "Broadwell" "-" TYPE_X86_CPU, + .property = "rdrand", + .value = "off", + }, +}; +const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); + +GlobalProperty pc_compat_2_1[] = { + PC_CPU_MODEL_IDS("2.1.0") + { + .driver = "coreduo" "-" TYPE_X86_CPU, + .property = "vmx", + .value = "on", + }, + { + .driver = "core2duo" "-" TYPE_X86_CPU, + .property = "vmx", + .value = "on", + }, +}; +const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); + +GlobalProperty pc_compat_2_0[] = { + PC_CPU_MODEL_IDS("2.0.0") + { + .driver = "virtio-scsi-pci", + .property = "any_layout", + .value = "off", + },{ + .driver = "PIIX4_PM", + .property = "memory-hotplug-support", + .value = "off", + }, + { + .driver = "apic", + .property = "version", + .value = stringify(0x11), + }, + { + .driver = "nec-usb-xhci", + .property = "superspeed-ports-first", + .value = "off", + }, + { + .driver = "nec-usb-xhci", + .property = "force-pcie-endcap", + .value = "on", + }, + { + .driver = "pci-serial", + .property = "prog_if", + .value = stringify(0), + }, + { + .driver = "pci-serial-2x", + .property = "prog_if", + .value = stringify(0), + }, + { + .driver = "pci-serial-4x", + .property = "prog_if", + .value = stringify(0), + }, + { + .driver = "virtio-net-pci", + .property = "guest_announce", + .value = "off", + }, + { + .driver = "ICH9-LPC", + .property = "memory-hotplug-support", + .value = "off", + },{ + .driver = "xio3130-downstream", + .property = COMPAT_PROP_PCP, + .value = "off", + },{ + .driver = "ioh3420", + .property = COMPAT_PROP_PCP, + .value = "off", + }, +}; +const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); + +GlobalProperty pc_compat_1_7[] = { + PC_CPU_MODEL_IDS("1.7.0") + { + .driver = TYPE_USB_DEVICE, + .property = "msos-desc", + .value = "no", + }, + { + .driver = "PIIX4_PM", + .property = "acpi-pci-hotplug-with-bridge-support", + .value = "off", + }, + { + .driver = "hpet", + .property = HPET_INTCAP, + .value = stringify(4), + }, +}; +const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); + +GlobalProperty pc_compat_1_6[] = { + PC_CPU_MODEL_IDS("1.6.0") + { + .driver = "e1000", + .property = "mitigation", + .value = "off", + },{ + .driver = "qemu64-" TYPE_X86_CPU, + .property = "model", + .value = stringify(2), + },{ + .driver = "qemu32-" TYPE_X86_CPU, + .property = "model", + .value = stringify(3), + },{ + .driver = "i440FX-pcihost", + .property = "short_root_bus", + .value = stringify(1), + },{ + .driver = "q35-pcihost", + .property = "short_root_bus", + .value = stringify(1), + }, +}; +const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); + +GlobalProperty pc_compat_1_5[] = { + PC_CPU_MODEL_IDS("1.5.0") + { + .driver = "Conroe-" TYPE_X86_CPU, + .property = "model", + .value = stringify(2), + },{ + .driver = "Conroe-" TYPE_X86_CPU, + .property = "min-level", + .value = stringify(2), + },{ + .driver = "Penryn-" TYPE_X86_CPU, + .property = "model", + .value = stringify(2), + },{ + .driver = "Penryn-" TYPE_X86_CPU, + .property = "min-level", + .value = stringify(2), + },{ + .driver = "Nehalem-" TYPE_X86_CPU, + .property = "model", + .value = stringify(2), + },{ + .driver = "Nehalem-" TYPE_X86_CPU, + .property = "min-level", + .value = stringify(2), + },{ + .driver = "virtio-net-pci", + .property = "any_layout", + .value = "off", + },{ + .driver = TYPE_X86_CPU, + .property = "pmu", + .value = "on", + },{ + .driver = "i440FX-pcihost", + .property = "short_root_bus", + .value = stringify(0), + },{ + .driver = "q35-pcihost", + .property = "short_root_bus", + .value = stringify(0), + }, +}; +const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); + +GlobalProperty pc_compat_1_4[] = { + PC_CPU_MODEL_IDS("1.4.0") + { + .driver = "scsi-hd", + .property = "discard_granularity", + .value = stringify(0), + },{ + .driver = "scsi-cd", + .property = "discard_granularity", + .value = stringify(0), + },{ + .driver = "scsi-disk", + .property = "discard_granularity", + .value = stringify(0), + },{ + .driver = "ide-hd", + .property = "discard_granularity", + .value = stringify(0), + },{ + .driver = "ide-cd", + .property = "discard_granularity", + .value = stringify(0), + },{ + .driver = "ide-drive", + .property = "discard_granularity", + .value = stringify(0), + },{ + .driver = "virtio-blk-pci", + .property = "discard_granularity", + .value = stringify(0), + },{ + .driver = "virtio-serial-pci", + .property = "vectors", + /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */ + .value = stringify(0xFFFFFFFF), + },{ + .driver = "virtio-net-pci", + .property = "ctrl_guest_offloads", + .value = "off", + },{ + .driver = "e1000", + .property = "romfile", + .value = "pxe-e1000.rom", + },{ + .driver = "ne2k_pci", + .property = "romfile", + .value = "pxe-ne2k_pci.rom", + },{ + .driver = "pcnet", + .property = "romfile", + .value = "pxe-pcnet.rom", + },{ + .driver = "rtl8139", + .property = "romfile", + .value = "pxe-rtl8139.rom", + },{ + .driver = "virtio-net-pci", + .property = "romfile", + .value = "pxe-virtio.rom", + },{ + .driver = "486-" TYPE_X86_CPU, + .property = "model", + .value = stringify(0), + }, + { + .driver = "n270" "-" TYPE_X86_CPU, + .property = "movbe", + .value = "off", + }, + { + .driver = "Westmere" "-" TYPE_X86_CPU, + .property = "pclmulqdq", + .value = "off", + }, +}; +const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); + void gsi_handler(void *opaque, int n, int level) { GSIState *s = opaque; @@ -1665,9 +2339,9 @@ void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) unsigned int i; if (kvm_ioapic_in_kernel()) { - dev = qdev_create(NULL, "kvm-ioapic"); + dev = qdev_create(NULL, TYPE_KVM_IOAPIC); } else { - dev = qdev_create(NULL, "ioapic"); + dev = qdev_create(NULL, TYPE_IOAPIC); } if (parent_name) { object_property_add_child(object_resolve_path(parent_name, NULL), diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 7f1cb527b5..ed6984638e 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -310,7 +310,7 @@ static void pc_init1(MachineState *machine, * HW_COMPAT_*, PC_COMPAT_*, or * pc_*_machine_options(). */ -static void pc_compat_2_3(MachineState *machine) +static void pc_compat_2_3_fn(MachineState *machine) { PCMachineState *pcms = PC_MACHINE(machine); if (kvm_enabled()) { @@ -318,46 +318,46 @@ static void pc_compat_2_3(MachineState *machine) } } -static void pc_compat_2_2(MachineState *machine) +static void pc_compat_2_2_fn(MachineState *machine) { - pc_compat_2_3(machine); + pc_compat_2_3_fn(machine); } -static void pc_compat_2_1(MachineState *machine) +static void pc_compat_2_1_fn(MachineState *machine) { - pc_compat_2_2(machine); + pc_compat_2_2_fn(machine); x86_cpu_change_kvm_default("svm", NULL); } -static void pc_compat_2_0(MachineState *machine) +static void pc_compat_2_0_fn(MachineState *machine) { - pc_compat_2_1(machine); + pc_compat_2_1_fn(machine); } -static void pc_compat_1_7(MachineState *machine) +static void pc_compat_1_7_fn(MachineState *machine) { - pc_compat_2_0(machine); + pc_compat_2_0_fn(machine); x86_cpu_change_kvm_default("x2apic", NULL); } -static void pc_compat_1_6(MachineState *machine) +static void pc_compat_1_6_fn(MachineState *machine) { - pc_compat_1_7(machine); + pc_compat_1_7_fn(machine); } -static void pc_compat_1_5(MachineState *machine) +static void pc_compat_1_5_fn(MachineState *machine) { - pc_compat_1_6(machine); + pc_compat_1_6_fn(machine); } -static void pc_compat_1_4(MachineState *machine) +static void pc_compat_1_4_fn(MachineState *machine) { - pc_compat_1_5(machine); + pc_compat_1_5_fn(machine); } static void pc_compat_1_3(MachineState *machine) { - pc_compat_1_4(machine); + pc_compat_1_4_fn(machine); enable_compat_apic_id_mode(); } @@ -443,7 +443,8 @@ static void pc_i440fx_3_1_machine_options(MachineClass *m) pc_i440fx_4_0_machine_options(m); m->is_default = 0; m->alias = NULL; - SET_MACHINE_COMPAT(m, PC_COMPAT_3_1); + compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); + compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); } DEFINE_I440FX_MACHINE(v3_1, "pc-i440fx-3.1", NULL, @@ -452,7 +453,8 @@ DEFINE_I440FX_MACHINE(v3_1, "pc-i440fx-3.1", NULL, static void pc_i440fx_3_0_machine_options(MachineClass *m) { pc_i440fx_3_1_machine_options(m); - SET_MACHINE_COMPAT(m, PC_COMPAT_3_0); + compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); + compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); } DEFINE_I440FX_MACHINE(v3_0, "pc-i440fx-3.0", NULL, @@ -461,7 +463,8 @@ DEFINE_I440FX_MACHINE(v3_0, "pc-i440fx-3.0", NULL, static void pc_i440fx_2_12_machine_options(MachineClass *m) { pc_i440fx_3_0_machine_options(m); - SET_MACHINE_COMPAT(m, PC_COMPAT_2_12); + compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); + compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); } DEFINE_I440FX_MACHINE(v2_12, "pc-i440fx-2.12", NULL, @@ -470,7 +473,8 @@ DEFINE_I440FX_MACHINE(v2_12, "pc-i440fx-2.12", NULL, static void pc_i440fx_2_11_machine_options(MachineClass *m) { pc_i440fx_2_12_machine_options(m); - SET_MACHINE_COMPAT(m, PC_COMPAT_2_11); + compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); + compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); } DEFINE_I440FX_MACHINE(v2_11, "pc-i440fx-2.11", NULL, @@ -479,7 +483,8 @@ DEFINE_I440FX_MACHINE(v2_11, "pc-i440fx-2.11", NULL, static void pc_i440fx_2_10_machine_options(MachineClass *m) { pc_i440fx_2_11_machine_options(m); - SET_MACHINE_COMPAT(m, PC_COMPAT_2_10); + compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); + compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); m->auto_enable_numa_with_memhp = false; } @@ -489,7 +494,8 @@ DEFINE_I440FX_MACHINE(v2_10, "pc-i440fx-2.10", NULL, static void pc_i440fx_2_9_machine_options(MachineClass *m) { pc_i440fx_2_10_machine_options(m); - SET_MACHINE_COMPAT(m, PC_COMPAT_2_9); + compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); + compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); m->numa_auto_assign_ram = numa_legacy_auto_assign_ram; } @@ -499,109 +505,114 @@ DEFINE_I440FX_MACHINE(v2_9, "pc-i440fx-2.9", NULL, static void pc_i440fx_2_8_machine_options(MachineClass *m) { pc_i440fx_2_9_machine_options(m); - SET_MACHINE_COMPAT(m, PC_COMPAT_2_8); + compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); + compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); } DEFINE_I440FX_MACHINE(v2_8, "pc-i440fx-2.8", NULL, pc_i440fx_2_8_machine_options); - static void pc_i440fx_2_7_machine_options(MachineClass *m) { pc_i440fx_2_8_machine_options(m); - SET_MACHINE_COMPAT(m, PC_COMPAT_2_7); + compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); + compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); } DEFINE_I440FX_MACHINE(v2_7, "pc-i440fx-2.7", NULL, pc_i440fx_2_7_machine_options); - static void pc_i440fx_2_6_machine_options(MachineClass *m) { PCMachineClass *pcmc = PC_MACHINE_CLASS(m); + pc_i440fx_2_7_machine_options(m); pcmc->legacy_cpu_hotplug = true; pcmc->linuxboot_dma_enabled = false; - SET_MACHINE_COMPAT(m, PC_COMPAT_2_6); + compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); + compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); } DEFINE_I440FX_MACHINE(v2_6, "pc-i440fx-2.6", NULL, pc_i440fx_2_6_machine_options); - static void pc_i440fx_2_5_machine_options(MachineClass *m) { PCMachineClass *pcmc = PC_MACHINE_CLASS(m); + pc_i440fx_2_6_machine_options(m); pcmc->save_tsc_khz = false; m->legacy_fw_cfg_order = 1; - SET_MACHINE_COMPAT(m, PC_COMPAT_2_5); + compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); + compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); } DEFINE_I440FX_MACHINE(v2_5, "pc-i440fx-2.5", NULL, pc_i440fx_2_5_machine_options); - static void pc_i440fx_2_4_machine_options(MachineClass *m) { PCMachineClass *pcmc = PC_MACHINE_CLASS(m); + pc_i440fx_2_5_machine_options(m); m->hw_version = "2.4.0"; pcmc->broken_reserved_end = true; - SET_MACHINE_COMPAT(m, PC_COMPAT_2_4); + compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); + compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); } DEFINE_I440FX_MACHINE(v2_4, "pc-i440fx-2.4", NULL, pc_i440fx_2_4_machine_options) - static void pc_i440fx_2_3_machine_options(MachineClass *m) { pc_i440fx_2_4_machine_options(m); m->hw_version = "2.3.0"; - SET_MACHINE_COMPAT(m, PC_COMPAT_2_3); + compat_props_add(m->compat_props, hw_compat_2_3, hw_compat_2_3_len); + compat_props_add(m->compat_props, pc_compat_2_3, pc_compat_2_3_len); } -DEFINE_I440FX_MACHINE(v2_3, "pc-i440fx-2.3", pc_compat_2_3, +DEFINE_I440FX_MACHINE(v2_3, "pc-i440fx-2.3", pc_compat_2_3_fn, pc_i440fx_2_3_machine_options); - static void pc_i440fx_2_2_machine_options(MachineClass *m) { PCMachineClass *pcmc = PC_MACHINE_CLASS(m); + pc_i440fx_2_3_machine_options(m); m->hw_version = "2.2.0"; m->default_machine_opts = "firmware=bios-256k.bin,suppress-vmdesc=on"; - SET_MACHINE_COMPAT(m, PC_COMPAT_2_2); + compat_props_add(m->compat_props, hw_compat_2_2, hw_compat_2_2_len); + compat_props_add(m->compat_props, pc_compat_2_2, pc_compat_2_2_len); pcmc->rsdp_in_ram = false; } -DEFINE_I440FX_MACHINE(v2_2, "pc-i440fx-2.2", pc_compat_2_2, +DEFINE_I440FX_MACHINE(v2_2, "pc-i440fx-2.2", pc_compat_2_2_fn, pc_i440fx_2_2_machine_options); - static void pc_i440fx_2_1_machine_options(MachineClass *m) { PCMachineClass *pcmc = PC_MACHINE_CLASS(m); + pc_i440fx_2_2_machine_options(m); m->hw_version = "2.1.0"; m->default_display = NULL; - SET_MACHINE_COMPAT(m, PC_COMPAT_2_1); + compat_props_add(m->compat_props, hw_compat_2_1, hw_compat_2_1_len); + compat_props_add(m->compat_props, pc_compat_2_1, pc_compat_2_1_len); pcmc->smbios_uuid_encoded = false; pcmc->enforce_aligned_dimm = false; } -DEFINE_I440FX_MACHINE(v2_1, "pc-i440fx-2.1", pc_compat_2_1, +DEFINE_I440FX_MACHINE(v2_1, "pc-i440fx-2.1", pc_compat_2_1_fn, pc_i440fx_2_1_machine_options); - - static void pc_i440fx_2_0_machine_options(MachineClass *m) { PCMachineClass *pcmc = PC_MACHINE_CLASS(m); + pc_i440fx_2_1_machine_options(m); m->hw_version = "2.0.0"; - SET_MACHINE_COMPAT(m, PC_COMPAT_2_0); + compat_props_add(m->compat_props, pc_compat_2_0, pc_compat_2_0_len); pcmc->smbios_legacy_mode = true; pcmc->has_reserved_memory = false; /* This value depends on the actual DSDT and SSDT compiled into @@ -624,329 +635,330 @@ static void pc_i440fx_2_0_machine_options(MachineClass *m) pcmc->acpi_data_size = 0x10000; } -DEFINE_I440FX_MACHINE(v2_0, "pc-i440fx-2.0", pc_compat_2_0, +DEFINE_I440FX_MACHINE(v2_0, "pc-i440fx-2.0", pc_compat_2_0_fn, pc_i440fx_2_0_machine_options); - static void pc_i440fx_1_7_machine_options(MachineClass *m) { PCMachineClass *pcmc = PC_MACHINE_CLASS(m); + pc_i440fx_2_0_machine_options(m); m->hw_version = "1.7.0"; m->default_machine_opts = NULL; m->option_rom_has_mr = true; - SET_MACHINE_COMPAT(m, PC_COMPAT_1_7); + compat_props_add(m->compat_props, pc_compat_1_7, pc_compat_1_7_len); pcmc->smbios_defaults = false; pcmc->gigabyte_align = false; pcmc->legacy_acpi_table_size = 6414; } -DEFINE_I440FX_MACHINE(v1_7, "pc-i440fx-1.7", pc_compat_1_7, +DEFINE_I440FX_MACHINE(v1_7, "pc-i440fx-1.7", pc_compat_1_7_fn, pc_i440fx_1_7_machine_options); - static void pc_i440fx_1_6_machine_options(MachineClass *m) { PCMachineClass *pcmc = PC_MACHINE_CLASS(m); + pc_i440fx_1_7_machine_options(m); m->hw_version = "1.6.0"; m->rom_file_has_mr = false; - SET_MACHINE_COMPAT(m, PC_COMPAT_1_6); + compat_props_add(m->compat_props, pc_compat_1_6, pc_compat_1_6_len); pcmc->has_acpi_build = false; } -DEFINE_I440FX_MACHINE(v1_6, "pc-i440fx-1.6", pc_compat_1_6, +DEFINE_I440FX_MACHINE(v1_6, "pc-i440fx-1.6", pc_compat_1_6_fn, pc_i440fx_1_6_machine_options); - static void pc_i440fx_1_5_machine_options(MachineClass *m) { pc_i440fx_1_6_machine_options(m); m->hw_version = "1.5.0"; - SET_MACHINE_COMPAT(m, PC_COMPAT_1_5); + compat_props_add(m->compat_props, pc_compat_1_5, pc_compat_1_5_len); } -DEFINE_I440FX_MACHINE(v1_5, "pc-i440fx-1.5", pc_compat_1_5, +DEFINE_I440FX_MACHINE(v1_5, "pc-i440fx-1.5", pc_compat_1_5_fn, pc_i440fx_1_5_machine_options); - static void pc_i440fx_1_4_machine_options(MachineClass *m) { pc_i440fx_1_5_machine_options(m); m->hw_version = "1.4.0"; m->hot_add_cpu = NULL; - SET_MACHINE_COMPAT(m, PC_COMPAT_1_4); + compat_props_add(m->compat_props, pc_compat_1_4, pc_compat_1_4_len); } -DEFINE_I440FX_MACHINE(v1_4, "pc-i440fx-1.4", pc_compat_1_4, +DEFINE_I440FX_MACHINE(v1_4, "pc-i440fx-1.4", pc_compat_1_4_fn, pc_i440fx_1_4_machine_options); - -#define PC_COMPAT_1_3 \ - PC_CPU_MODEL_IDS("1.3.0") \ - {\ - .driver = "usb-tablet",\ - .property = "usb_version",\ - .value = stringify(1),\ - },{\ - .driver = "virtio-net-pci",\ - .property = "ctrl_mac_addr",\ - .value = "off", \ - },{ \ - .driver = "virtio-net-pci", \ - .property = "mq", \ - .value = "off", \ - }, {\ - .driver = "e1000",\ - .property = "autonegotiation",\ - .value = "off",\ - }, - - static void pc_i440fx_1_3_machine_options(MachineClass *m) { + static GlobalProperty compat[] = { + PC_CPU_MODEL_IDS("1.3.0") + { + .driver = "usb-tablet", + .property = "usb_version", + .value = stringify(1), + },{ + .driver = "virtio-net-pci", + .property = "ctrl_mac_addr", + .value = "off", + },{ + .driver = "virtio-net-pci", + .property = "mq", + .value = "off", + }, { + .driver = "e1000", + .property = "autonegotiation", + .value = "off", + }, + }; + pc_i440fx_1_4_machine_options(m); m->hw_version = "1.3.0"; - SET_MACHINE_COMPAT(m, PC_COMPAT_1_3); + compat_props_add(m->compat_props, compat, G_N_ELEMENTS(compat)); } DEFINE_I440FX_MACHINE(v1_3, "pc-1.3", pc_compat_1_3, pc_i440fx_1_3_machine_options); -#define PC_COMPAT_1_2 \ - PC_CPU_MODEL_IDS("1.2.0") \ - {\ - .driver = "nec-usb-xhci",\ - .property = "msi",\ - .value = "off",\ - },{\ - .driver = "nec-usb-xhci",\ - .property = "msix",\ - .value = "off",\ - },{\ - .driver = "ivshmem",\ - .property = "use64",\ - .value = "0",\ - },{\ - .driver = "qxl",\ - .property = "revision",\ - .value = stringify(3),\ - },{\ - .driver = "qxl-vga",\ - .property = "revision",\ - .value = stringify(3),\ - },{\ - .driver = "VGA",\ - .property = "mmio",\ - .value = "off",\ - }, - static void pc_i440fx_1_2_machine_options(MachineClass *m) { + static GlobalProperty compat[] = { + PC_CPU_MODEL_IDS("1.2.0") + { + .driver = "nec-usb-xhci", + .property = "msi", + .value = "off", + },{ + .driver = "nec-usb-xhci", + .property = "msix", + .value = "off", + },{ + .driver = "ivshmem", + .property = "use64", + .value = "0", + },{ + .driver = "qxl", + .property = "revision", + .value = stringify(3), + },{ + .driver = "qxl-vga", + .property = "revision", + .value = stringify(3), + },{ + .driver = "VGA", + .property = "mmio", + .value = "off", + }, + }; + pc_i440fx_1_3_machine_options(m); m->hw_version = "1.2.0"; - SET_MACHINE_COMPAT(m, PC_COMPAT_1_2); + compat_props_add(m->compat_props, compat, G_N_ELEMENTS(compat)); } DEFINE_I440FX_MACHINE(v1_2, "pc-1.2", pc_compat_1_2, pc_i440fx_1_2_machine_options); -#define PC_COMPAT_1_1 \ - PC_CPU_MODEL_IDS("1.1.0") \ - {\ - .driver = "virtio-scsi-pci",\ - .property = "hotplug",\ - .value = "off",\ - },{\ - .driver = "virtio-scsi-pci",\ - .property = "param_change",\ - .value = "off",\ - },{\ - .driver = "VGA",\ - .property = "vgamem_mb",\ - .value = stringify(8),\ - },{\ - .driver = "vmware-svga",\ - .property = "vgamem_mb",\ - .value = stringify(8),\ - },{\ - .driver = "qxl-vga",\ - .property = "vgamem_mb",\ - .value = stringify(8),\ - },{\ - .driver = "qxl",\ - .property = "vgamem_mb",\ - .value = stringify(8),\ - },{\ - .driver = "virtio-blk-pci",\ - .property = "config-wce",\ - .value = "off",\ - }, - static void pc_i440fx_1_1_machine_options(MachineClass *m) { + static GlobalProperty compat[] = { + PC_CPU_MODEL_IDS("1.1.0") + { + .driver = "virtio-scsi-pci", + .property = "hotplug", + .value = "off", + },{ + .driver = "virtio-scsi-pci", + .property = "param_change", + .value = "off", + },{ + .driver = "VGA", + .property = "vgamem_mb", + .value = stringify(8), + },{ + .driver = "vmware-svga", + .property = "vgamem_mb", + .value = stringify(8), + },{ + .driver = "qxl-vga", + .property = "vgamem_mb", + .value = stringify(8), + },{ + .driver = "qxl", + .property = "vgamem_mb", + .value = stringify(8), + },{ + .driver = "virtio-blk-pci", + .property = "config-wce", + .value = "off", + }, + }; + pc_i440fx_1_2_machine_options(m); m->hw_version = "1.1.0"; - SET_MACHINE_COMPAT(m, PC_COMPAT_1_1); + compat_props_add(m->compat_props, compat, G_N_ELEMENTS(compat)); } DEFINE_I440FX_MACHINE(v1_1, "pc-1.1", pc_compat_1_2, pc_i440fx_1_1_machine_options); - -#define PC_COMPAT_1_0 \ - PC_CPU_MODEL_IDS("1.0") \ - {\ - .driver = TYPE_ISA_FDC,\ - .property = "check_media_rate",\ - .value = "off",\ - }, {\ - .driver = "virtio-balloon-pci",\ - .property = "class",\ - .value = stringify(PCI_CLASS_MEMORY_RAM),\ - },{\ - .driver = "apic-common",\ - .property = "vapic",\ - .value = "off",\ - },{\ - .driver = TYPE_USB_DEVICE,\ - .property = "full-path",\ - .value = "no",\ - }, - static void pc_i440fx_1_0_machine_options(MachineClass *m) { + static GlobalProperty compat[] = { + PC_CPU_MODEL_IDS("1.0") + { + .driver = TYPE_ISA_FDC, + .property = "check_media_rate", + .value = "off", + },{ + .driver = "virtio-balloon-pci", + .property = "class", + .value = stringify(PCI_CLASS_MEMORY_RAM), + },{ + .driver = "apic-common", + .property = "vapic", + .value = "off", + },{ + .driver = TYPE_USB_DEVICE, + .property = "full-path", + .value = "no", + }, + }; + pc_i440fx_1_1_machine_options(m); m->hw_version = "1.0"; - SET_MACHINE_COMPAT(m, PC_COMPAT_1_0); + compat_props_add(m->compat_props, compat, G_N_ELEMENTS(compat)); } DEFINE_I440FX_MACHINE(v1_0, "pc-1.0", pc_compat_1_2, pc_i440fx_1_0_machine_options); -#define PC_COMPAT_0_15 \ - PC_CPU_MODEL_IDS("0.15") - static void pc_i440fx_0_15_machine_options(MachineClass *m) { + static GlobalProperty compat[] = { + PC_CPU_MODEL_IDS("0.15") + }; + pc_i440fx_1_0_machine_options(m); m->hw_version = "0.15"; m->deprecation_reason = "use a newer machine type instead"; - SET_MACHINE_COMPAT(m, PC_COMPAT_0_15); + compat_props_add(m->compat_props, compat, G_N_ELEMENTS(compat)); } DEFINE_I440FX_MACHINE(v0_15, "pc-0.15", pc_compat_1_2, pc_i440fx_0_15_machine_options); -#define PC_COMPAT_0_14 \ - PC_CPU_MODEL_IDS("0.14") \ - {\ - .driver = "virtio-blk-pci",\ - .property = "event_idx",\ - .value = "off",\ - },{\ - .driver = "virtio-serial-pci",\ - .property = "event_idx",\ - .value = "off",\ - },{\ - .driver = "virtio-net-pci",\ - .property = "event_idx",\ - .value = "off",\ - },{\ - .driver = "virtio-balloon-pci",\ - .property = "event_idx",\ - .value = "off",\ - },{\ - .driver = "qxl",\ - .property = "revision",\ - .value = stringify(2),\ - },{\ - .driver = "qxl-vga",\ - .property = "revision",\ - .value = stringify(2),\ - }, - static void pc_i440fx_0_14_machine_options(MachineClass *m) { + static GlobalProperty compat[] = { + PC_CPU_MODEL_IDS("0.14") + { + .driver = "virtio-blk-pci", + .property = "event_idx", + .value = "off", + },{ + .driver = "virtio-serial-pci", + .property = "event_idx", + .value = "off", + },{ + .driver = "virtio-net-pci", + .property = "event_idx", + .value = "off", + },{ + .driver = "virtio-balloon-pci", + .property = "event_idx", + .value = "off", + },{ + .driver = "qxl", + .property = "revision", + .value = stringify(2), + },{ + .driver = "qxl-vga", + .property = "revision", + .value = stringify(2), + }, + }; + pc_i440fx_0_15_machine_options(m); m->hw_version = "0.14"; - SET_MACHINE_COMPAT(m, PC_COMPAT_0_14); + compat_props_add(m->compat_props, compat, G_N_ELEMENTS(compat)); } DEFINE_I440FX_MACHINE(v0_14, "pc-0.14", pc_compat_1_2, pc_i440fx_0_14_machine_options); - -#define PC_COMPAT_0_13 \ - PC_CPU_MODEL_IDS("0.13") \ - {\ - .driver = TYPE_PCI_DEVICE,\ - .property = "command_serr_enable",\ - .value = "off",\ - },{\ - .driver = "AC97",\ - .property = "use_broken_id",\ - .value = stringify(1),\ - },{\ - .driver = "virtio-9p-pci",\ - .property = "vectors",\ - .value = stringify(0),\ - },{\ - .driver = "VGA",\ - .property = "rombar",\ - .value = stringify(0),\ - },{\ - .driver = "vmware-svga",\ - .property = "rombar",\ - .value = stringify(0),\ - }, - static void pc_i440fx_0_13_machine_options(MachineClass *m) { PCMachineClass *pcmc = PC_MACHINE_CLASS(m); + static GlobalProperty compat[] = { + PC_CPU_MODEL_IDS("0.13") + { + .driver = TYPE_PCI_DEVICE, + .property = "command_serr_enable", + .value = "off", + },{ + .driver = "AC97", + .property = "use_broken_id", + .value = stringify(1), + },{ + .driver = "virtio-9p-pci", + .property = "vectors", + .value = stringify(0), + },{ + .driver = "VGA", + .property = "rombar", + .value = stringify(0), + },{ + .driver = "vmware-svga", + .property = "rombar", + .value = stringify(0), + }, + }; + pc_i440fx_0_14_machine_options(m); m->hw_version = "0.13"; - SET_MACHINE_COMPAT(m, PC_COMPAT_0_13); + compat_props_add(m->compat_props, compat, G_N_ELEMENTS(compat)); pcmc->kvmclock_enabled = false; } DEFINE_I440FX_MACHINE(v0_13, "pc-0.13", pc_compat_0_13, pc_i440fx_0_13_machine_options); - -#define PC_COMPAT_0_12 \ - PC_CPU_MODEL_IDS("0.12") \ - {\ - .driver = "virtio-serial-pci",\ - .property = "max_ports",\ - .value = stringify(1),\ - },{\ - .driver = "virtio-serial-pci",\ - .property = "vectors",\ - .value = stringify(0),\ - },{\ - .driver = "usb-mouse",\ - .property = "serial",\ - .value = "1",\ - },{\ - .driver = "usb-tablet",\ - .property = "serial",\ - .value = "1",\ - },{\ - .driver = "usb-kbd",\ - .property = "serial",\ - .value = "1",\ - }, - static void pc_i440fx_0_12_machine_options(MachineClass *m) { + static GlobalProperty compat[] = { + PC_CPU_MODEL_IDS("0.12") + { + .driver = "virtio-serial-pci", + .property = "max_ports", + .value = stringify(1), + },{ + .driver = "virtio-serial-pci", + .property = "vectors", + .value = stringify(0), + },{ + .driver = "usb-mouse", + .property = "serial", + .value = "1", + },{ + .driver = "usb-tablet", + .property = "serial", + .value = "1", + },{ + .driver = "usb-kbd", + .property = "serial", + .value = "1", + }, + }; + pc_i440fx_0_13_machine_options(m); m->hw_version = "0.12"; - SET_MACHINE_COMPAT(m, PC_COMPAT_0_12); + compat_props_add(m->compat_props, compat, G_N_ELEMENTS(compat)); } DEFINE_I440FX_MACHINE(v0_12, "pc-0.12", pc_compat_0_13, diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 0a3f3f18e4..b7b7959934 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -58,6 +58,59 @@ /* ICH9 AHCI has 6 ports */ #define MAX_SATA_PORTS 6 +struct ehci_companions { + const char *name; + int func; + int port; +}; + +static const struct ehci_companions ich9_1d[] = { + { .name = "ich9-usb-uhci1", .func = 0, .port = 0 }, + { .name = "ich9-usb-uhci2", .func = 1, .port = 2 }, + { .name = "ich9-usb-uhci3", .func = 2, .port = 4 }, +}; + +static const struct ehci_companions ich9_1a[] = { + { .name = "ich9-usb-uhci4", .func = 0, .port = 0 }, + { .name = "ich9-usb-uhci5", .func = 1, .port = 2 }, + { .name = "ich9-usb-uhci6", .func = 2, .port = 4 }, +}; + +static int ehci_create_ich9_with_companions(PCIBus *bus, int slot) +{ + const struct ehci_companions *comp; + PCIDevice *ehci, *uhci; + BusState *usbbus; + const char *name; + int i; + + switch (slot) { + case 0x1d: + name = "ich9-usb-ehci1"; + comp = ich9_1d; + break; + case 0x1a: + name = "ich9-usb-ehci2"; + comp = ich9_1a; + break; + default: + return -1; + } + + ehci = pci_create_multifunction(bus, PCI_DEVFN(slot, 7), true, name); + qdev_init_nofail(&ehci->qdev); + usbbus = QLIST_FIRST(&ehci->qdev.child_bus); + + for (i = 0; i < 3; i++) { + uhci = pci_create_multifunction(bus, PCI_DEVFN(slot, comp[i].func), + true, comp[i].name); + qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); + qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); + qdev_init_nofail(&uhci->qdev); + } + return 0; +} + /* PC hardware initialisation */ static void pc_q35_init(MachineState *machine) { @@ -326,7 +379,8 @@ static void pc_q35_3_1_machine_options(MachineClass *m) pc_q35_4_0_machine_options(m); m->default_kernel_irqchip_split = false; m->alias = NULL; - SET_MACHINE_COMPAT(m, PC_COMPAT_3_1); + compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len); + compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len); } DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, @@ -335,7 +389,8 @@ DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL, static void pc_q35_3_0_machine_options(MachineClass *m) { pc_q35_3_1_machine_options(m); - SET_MACHINE_COMPAT(m, PC_COMPAT_3_0); + compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len); + compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len); } DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, @@ -344,7 +399,8 @@ DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL, static void pc_q35_2_12_machine_options(MachineClass *m) { pc_q35_3_0_machine_options(m); - SET_MACHINE_COMPAT(m, PC_COMPAT_2_12); + compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len); + compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len); } DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL, @@ -356,7 +412,8 @@ static void pc_q35_2_11_machine_options(MachineClass *m) pc_q35_2_12_machine_options(m); pcmc->default_nic_model = "e1000"; - SET_MACHINE_COMPAT(m, PC_COMPAT_2_11); + compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len); + compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len); } DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, @@ -365,7 +422,8 @@ DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL, static void pc_q35_2_10_machine_options(MachineClass *m) { pc_q35_2_11_machine_options(m); - SET_MACHINE_COMPAT(m, PC_COMPAT_2_10); + compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len); + compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len); m->numa_auto_assign_ram = numa_legacy_auto_assign_ram; m->auto_enable_numa_with_memhp = false; } @@ -376,7 +434,8 @@ DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL, static void pc_q35_2_9_machine_options(MachineClass *m) { pc_q35_2_10_machine_options(m); - SET_MACHINE_COMPAT(m, PC_COMPAT_2_9); + compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len); + compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len); } DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, @@ -385,7 +444,8 @@ DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL, static void pc_q35_2_8_machine_options(MachineClass *m) { pc_q35_2_9_machine_options(m); - SET_MACHINE_COMPAT(m, PC_COMPAT_2_8); + compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len); + compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len); } DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL, @@ -395,7 +455,8 @@ static void pc_q35_2_7_machine_options(MachineClass *m) { pc_q35_2_8_machine_options(m); m->max_cpus = 255; - SET_MACHINE_COMPAT(m, PC_COMPAT_2_7); + compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len); + compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len); } DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, @@ -404,10 +465,12 @@ DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL, static void pc_q35_2_6_machine_options(MachineClass *m) { PCMachineClass *pcmc = PC_MACHINE_CLASS(m); + pc_q35_2_7_machine_options(m); pcmc->legacy_cpu_hotplug = true; pcmc->linuxboot_dma_enabled = false; - SET_MACHINE_COMPAT(m, PC_COMPAT_2_6); + compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len); + compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len); } DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, @@ -416,10 +479,12 @@ DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL, static void pc_q35_2_5_machine_options(MachineClass *m) { PCMachineClass *pcmc = PC_MACHINE_CLASS(m); + pc_q35_2_6_machine_options(m); pcmc->save_tsc_khz = false; m->legacy_fw_cfg_order = 1; - SET_MACHINE_COMPAT(m, PC_COMPAT_2_5); + compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len); + compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len); } DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, @@ -428,10 +493,12 @@ DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL, static void pc_q35_2_4_machine_options(MachineClass *m) { PCMachineClass *pcmc = PC_MACHINE_CLASS(m); + pc_q35_2_5_machine_options(m); m->hw_version = "2.4.0"; pcmc->broken_reserved_end = true; - SET_MACHINE_COMPAT(m, PC_COMPAT_2_4); + compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len); + compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len); } DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL, diff --git a/hw/ide/pci.c b/hw/ide/pci.c index fe1ceeb0cd..b75154f99f 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -25,7 +25,6 @@ #include "qemu/osdep.h" #include "hw/hw.h" #include "hw/pci/pci.h" -#include "hw/isa/isa.h" #include "sysemu/dma.h" #include "qemu/error-report.h" #include "hw/ide/pci.h" diff --git a/hw/ide/piix.c b/hw/ide/piix.c index a3afe1fd29..885c16e938 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -26,7 +26,6 @@ #include "qemu/osdep.h" #include "hw/hw.h" #include "hw/pci/pci.h" -#include "hw/isa/isa.h" #include "sysemu/block-backend.h" #include "sysemu/sysemu.h" #include "sysemu/blockdev.h" diff --git a/hw/ide/via.c b/hw/ide/via.c index 238f038d72..987d99c5ec 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -26,7 +26,6 @@ #include "qemu/osdep.h" #include "hw/hw.h" #include "hw/pci/pci.h" -#include "hw/isa/isa.h" #include "sysemu/sysemu.h" #include "sysemu/dma.h" diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c index 4e529729b4..9d75f84d3b 100644 --- a/hw/intc/ioapic.c +++ b/hw/intc/ioapic.c @@ -429,7 +429,7 @@ static void ioapic_class_init(ObjectClass *klass, void *data) } static const TypeInfo ioapic_info = { - .name = "ioapic", + .name = TYPE_IOAPIC, .parent = TYPE_IOAPIC_COMMON, .instance_size = sizeof(IOAPICCommonState), .class_init = ioapic_class_init, diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 0e39c90cbd..d391177ab8 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -179,6 +179,15 @@ static void spapr_xive_map_mmio(sPAPRXive *xive) sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base); } +void spapr_xive_mmio_set_enabled(sPAPRXive *xive, bool enable) +{ + memory_region_set_enabled(&xive->source.esb_mmio, enable); + memory_region_set_enabled(&xive->tm_mmio, enable); + + /* Disable the END ESBs until a guest OS makes use of them */ + memory_region_set_enabled(&xive->end_source.esb_mmio, false); +} + /* * When a Virtual Processor is scheduled to run on a HW thread, the * hypervisor pushes its identifier in the OS CAM line. Emulate the @@ -488,20 +497,6 @@ bool spapr_xive_irq_free(sPAPRXive *xive, uint32_t lisn) return true; } -qemu_irq spapr_xive_qirq(sPAPRXive *xive, uint32_t lisn) -{ - XiveSource *xsrc = &xive->source; - - if (lisn >= xive->nr_irqs) { - return NULL; - } - - /* The sPAPR machine/device should have claimed the IRQ before */ - assert(xive_eas_is_valid(&xive->eat[lisn])); - - return xive_source_qirq(xsrc, lisn); -} - /* * XIVE hcalls * diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 406efee064..16e8ffa2aa 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -461,7 +461,7 @@ static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val) ics_simple_resend_lsi(ics, srcno); } -static void ics_simple_set_irq(void *opaque, int srcno, int val) +void ics_simple_set_irq(void *opaque, int srcno, int val) { ICSState *ics = (ICSState *)opaque; @@ -571,8 +571,6 @@ static void ics_simple_realize(DeviceState *dev, Error **errp) return; } - ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs); - qemu_register_reset(ics_simple_reset_handler, ics); } diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c index e8fa9a53ae..ac94594b19 100644 --- a/hw/intc/xics_kvm.c +++ b/hw/intc/xics_kvm.c @@ -298,7 +298,7 @@ static int ics_set_kvm_state(ICSState *ics, int version_id) return 0; } -static void ics_kvm_set_irq(void *opaque, int srcno, int val) +void ics_kvm_set_irq(void *opaque, int srcno, int val) { ICSState *ics = opaque; struct kvm_irq_level args; @@ -344,7 +344,6 @@ static void ics_kvm_realize(DeviceState *dev, Error **errp) error_propagate(errp, local_err); return; } - ics->qirqs = qemu_allocate_irqs(ics_kvm_set_irq, ics, ics->nr_irqs); qemu_register_reset(ics_kvm_reset_handler, ics); } diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index f67d3c80bf..9c1a90d709 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -44,7 +44,7 @@ static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr, { target_ulong cppr = args[0]; - icp_set_cppr(ICP(cpu->intc), cppr); + icp_set_cppr(cpu->icp, cppr); return H_SUCCESS; } @@ -65,7 +65,7 @@ static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr, static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, target_ulong *args) { - uint32_t xirr = icp_accept(ICP(cpu->intc)); + uint32_t xirr = icp_accept(cpu->icp); args[0] = xirr; return H_SUCCESS; @@ -74,7 +74,7 @@ static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr, static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, target_ulong *args) { - uint32_t xirr = icp_accept(ICP(cpu->intc)); + uint32_t xirr = icp_accept(cpu->icp); args[0] = xirr; args[1] = cpu_get_host_ticks(); @@ -86,7 +86,7 @@ static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr, { target_ulong xirr = args[0]; - icp_eoi(ICP(cpu->intc), xirr); + icp_eoi(cpu->icp, xirr); return H_SUCCESS; } @@ -94,7 +94,7 @@ static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, target_ulong *args) { uint32_t mfrr; - uint32_t xirr = icp_ipoll(ICP(cpu->intc), &mfrr); + uint32_t xirr = icp_ipoll(cpu->icp, &mfrr); args[0] = xirr; args[1] = mfrr; diff --git a/hw/intc/xive.c b/hw/intc/xive.c index ea33494338..a3cb0cf0e3 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -321,7 +321,7 @@ static void xive_tm_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { PowerPCCPU *cpu = POWERPC_CPU(current_cpu); - XiveTCTX *tctx = XIVE_TCTX(cpu->intc); + XiveTCTX *tctx = cpu->tctx; const XiveTmOp *xto; /* @@ -360,7 +360,7 @@ static void xive_tm_write(void *opaque, hwaddr offset, static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) { PowerPCCPU *cpu = POWERPC_CPU(current_cpu); - XiveTCTX *tctx = XIVE_TCTX(cpu->intc); + XiveTCTX *tctx = cpu->tctx; const XiveTmOp *xto; /* @@ -845,7 +845,7 @@ static const MemoryRegionOps xive_source_esb_ops = { }, }; -static void xive_source_set_irq(void *opaque, int srcno, int val) +void xive_source_set_irq(void *opaque, int srcno, int val) { XiveSource *xsrc = XIVE_SOURCE(opaque); bool notify = false; @@ -932,9 +932,6 @@ static void xive_source_realize(DeviceState *dev, Error **errp) &xive_source_esb_ops, xsrc, "xive.esb", (1ull << xsrc->esb_shift) * xsrc->nr_irqs); - xsrc->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, - xsrc->nr_irqs); - qemu_register_reset(xive_source_reset, dev); } @@ -1186,7 +1183,7 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, CPU_FOREACH(cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); - XiveTCTX *tctx = XIVE_TCTX(cpu->intc); + XiveTCTX *tctx = cpu->tctx; int ring; /* diff --git a/hw/microblaze/boot.c b/hw/microblaze/boot.c index 35bfeda7aa..489ab839b7 100644 --- a/hw/microblaze/boot.c +++ b/hw/microblaze/boot.c @@ -156,7 +156,7 @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base, /* If it wasn't an ELF image, try an u-boot image. */ if (kernel_size < 0) { - hwaddr uentry, loadaddr; + hwaddr uentry, loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; kernel_size = load_uimage(kernel_filename, &uentry, &loadaddr, 0, NULL, NULL); diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 680350b3c3..04f3bfa516 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -74,3 +74,4 @@ obj-$(CONFIG_PVPANIC) += pvpanic.o obj-$(CONFIG_AUX) += auxbus.o obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o obj-$(CONFIG_MSF2) += msf2-sysreg.o +obj-$(CONFIG_NRF51_SOC) += nrf51_rng.o diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c index 87ae246d37..e5917d8f2e 100644 --- a/hw/misc/macio/mac_dbdma.c +++ b/hw/misc/macio/mac_dbdma.c @@ -38,7 +38,6 @@ */ #include "qemu/osdep.h" #include "hw/hw.h" -#include "hw/isa/isa.h" #include "hw/ppc/mac_dbdma.h" #include "qemu/main-loop.h" #include "qemu/log.h" diff --git a/hw/misc/nrf51_rng.c b/hw/misc/nrf51_rng.c new file mode 100644 index 0000000000..d188f044f4 --- /dev/null +++ b/hw/misc/nrf51_rng.c @@ -0,0 +1,262 @@ +/* + * nRF51 Random Number Generator + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf + * + * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de> + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/arm/nrf51.h" +#include "hw/misc/nrf51_rng.h" +#include "crypto/random.h" + +static void update_irq(NRF51RNGState *s) +{ + bool irq = s->interrupt_enabled && s->event_valrdy; + qemu_set_irq(s->irq, irq); +} + +static uint64_t rng_read(void *opaque, hwaddr offset, unsigned int size) +{ + NRF51RNGState *s = NRF51_RNG(opaque); + uint64_t r = 0; + + switch (offset) { + case NRF51_RNG_EVENT_VALRDY: + r = s->event_valrdy; + break; + case NRF51_RNG_REG_SHORTS: + r = s->shortcut_stop_on_valrdy; + break; + case NRF51_RNG_REG_INTEN: + case NRF51_RNG_REG_INTENSET: + case NRF51_RNG_REG_INTENCLR: + r = s->interrupt_enabled; + break; + case NRF51_RNG_REG_CONFIG: + r = s->filter_enabled; + break; + case NRF51_RNG_REG_VALUE: + r = s->value; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad read offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + return r; +} + +static int64_t calc_next_timeout(NRF51RNGState *s) +{ + int64_t timeout = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL); + if (s->filter_enabled) { + timeout += s->period_filtered_us; + } else { + timeout += s->period_unfiltered_us; + } + + return timeout; +} + + +static void rng_update_timer(NRF51RNGState *s) +{ + if (s->active) { + timer_mod(&s->timer, calc_next_timeout(s)); + } else { + timer_del(&s->timer); + } +} + + +static void rng_write(void *opaque, hwaddr offset, + uint64_t value, unsigned int size) +{ + NRF51RNGState *s = NRF51_RNG(opaque); + + switch (offset) { + case NRF51_RNG_TASK_START: + if (value == NRF51_TRIGGER_TASK) { + s->active = 1; + rng_update_timer(s); + } + break; + case NRF51_RNG_TASK_STOP: + if (value == NRF51_TRIGGER_TASK) { + s->active = 0; + rng_update_timer(s); + } + break; + case NRF51_RNG_EVENT_VALRDY: + if (value == NRF51_EVENT_CLEAR) { + s->event_valrdy = 0; + } + break; + case NRF51_RNG_REG_SHORTS: + s->shortcut_stop_on_valrdy = + (value & BIT_MASK(NRF51_RNG_REG_SHORTS_VALRDY_STOP)) ? 1 : 0; + break; + case NRF51_RNG_REG_INTEN: + s->interrupt_enabled = + (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) ? 1 : 0; + break; + case NRF51_RNG_REG_INTENSET: + if (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) { + s->interrupt_enabled = 1; + } + break; + case NRF51_RNG_REG_INTENCLR: + if (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) { + s->interrupt_enabled = 0; + } + break; + case NRF51_RNG_REG_CONFIG: + s->filter_enabled = + (value & BIT_MASK(NRF51_RNG_REG_CONFIG_DECEN)) ? 1 : 0; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad write offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + update_irq(s); +} + +static const MemoryRegionOps rng_ops = { + .read = rng_read, + .write = rng_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4 +}; + +static void nrf51_rng_timer_expire(void *opaque) +{ + NRF51RNGState *s = NRF51_RNG(opaque); + + qcrypto_random_bytes(&s->value, 1, &error_abort); + + s->event_valrdy = 1; + qemu_set_irq(s->eep_valrdy, 1); + + if (s->shortcut_stop_on_valrdy) { + s->active = 0; + } + + rng_update_timer(s); + update_irq(s); +} + +static void nrf51_rng_tep_start(void *opaque, int n, int level) +{ + NRF51RNGState *s = NRF51_RNG(opaque); + + if (level) { + s->active = 1; + rng_update_timer(s); + } +} + +static void nrf51_rng_tep_stop(void *opaque, int n, int level) +{ + NRF51RNGState *s = NRF51_RNG(opaque); + + if (level) { + s->active = 0; + rng_update_timer(s); + } +} + + +static void nrf51_rng_init(Object *obj) +{ + NRF51RNGState *s = NRF51_RNG(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->mmio, obj, &rng_ops, s, + TYPE_NRF51_RNG, NRF51_RNG_SIZE); + sysbus_init_mmio(sbd, &s->mmio); + + timer_init_us(&s->timer, QEMU_CLOCK_VIRTUAL, nrf51_rng_timer_expire, s); + + sysbus_init_irq(sbd, &s->irq); + + /* Tasks */ + qdev_init_gpio_in_named(DEVICE(s), nrf51_rng_tep_start, "tep_start", 1); + qdev_init_gpio_in_named(DEVICE(s), nrf51_rng_tep_stop, "tep_stop", 1); + + /* Events */ + qdev_init_gpio_out_named(DEVICE(s), &s->eep_valrdy, "eep_valrdy", 1); +} + +static void nrf51_rng_reset(DeviceState *dev) +{ + NRF51RNGState *s = NRF51_RNG(dev); + + s->value = 0; + s->active = 0; + s->event_valrdy = 0; + s->shortcut_stop_on_valrdy = 0; + s->interrupt_enabled = 0; + s->filter_enabled = 0; + + rng_update_timer(s); +} + + +static Property nrf51_rng_properties[] = { + DEFINE_PROP_UINT16("period_unfiltered_us", NRF51RNGState, + period_unfiltered_us, 167), + DEFINE_PROP_UINT16("period_filtered_us", NRF51RNGState, + period_filtered_us, 660), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription vmstate_rng = { + .name = "nrf51_soc.rng", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(active, NRF51RNGState), + VMSTATE_UINT32(event_valrdy, NRF51RNGState), + VMSTATE_UINT32(shortcut_stop_on_valrdy, NRF51RNGState), + VMSTATE_UINT32(interrupt_enabled, NRF51RNGState), + VMSTATE_UINT32(filter_enabled, NRF51RNGState), + VMSTATE_END_OF_LIST() + } +}; + +static void nrf51_rng_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->props = nrf51_rng_properties; + dc->vmsd = &vmstate_rng; + dc->reset = nrf51_rng_reset; +} + +static const TypeInfo nrf51_rng_info = { + .name = TYPE_NRF51_RNG, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NRF51RNGState), + .instance_init = nrf51_rng_init, + .class_init = nrf51_rng_class_init +}; + +static void nrf51_rng_register_types(void) +{ + type_register_static(&nrf51_rng_info); +} + +type_init(nrf51_rng_register_types) diff --git a/hw/misc/tz-mpc.c b/hw/misc/tz-mpc.c index fb48a1540b..9a84be75ed 100644 --- a/hw/misc/tz-mpc.c +++ b/hw/misc/tz-mpc.c @@ -150,7 +150,7 @@ static MemTxResult tz_mpc_reg_read(void *opaque, hwaddr addr, r = s->ctrl; break; case A_BLK_MAX: - r = s->blk_max; + r = s->blk_max - 1; break; case A_BLK_CFG: /* We are never in "init in progress state", so this just indicates diff --git a/hw/moxie/moxiesim.c b/hw/moxie/moxiesim.c index 4b0ce09c5e..c6b6f7262d 100644 --- a/hw/moxie/moxiesim.c +++ b/hw/moxie/moxiesim.c @@ -31,7 +31,6 @@ #include "cpu.h" #include "hw/sysbus.h" #include "hw/hw.h" -#include "hw/isa/isa.h" #include "net/net.h" #include "sysemu/sysemu.h" #include "hw/boards.h" diff --git a/hw/nios2/boot.c b/hw/nios2/boot.c index 4bb5b601d3..ed5cb28e94 100644 --- a/hw/nios2/boot.c +++ b/hw/nios2/boot.c @@ -161,7 +161,7 @@ void nios2_load_kernel(Nios2CPU *cpu, hwaddr ddr_base, /* If it wasn't an ELF image, try an u-boot image. */ if (kernel_size < 0) { - hwaddr uentry, loadaddr; + hwaddr uentry, loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; kernel_size = load_uimage(kernel_filename, &uentry, &loadaddr, 0, NULL, NULL); diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index de58c7be46..53e8e010a8 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -27,7 +27,6 @@ #include "sysemu/sysemu.h" #include "sysemu/dma.h" #include "hw/boards.h" -#include "hw/isa/isa.h" #include "hw/nvram/fw_cfg.h" #include "hw/sysbus.h" #include "trace.h" diff --git a/hw/pci/pci.c b/hw/pci/pci.c index d831fa0a36..46d5010fac 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -333,6 +333,13 @@ static void pci_host_bus_register(DeviceState *host) QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); } +static void pci_host_bus_unregister(DeviceState *host) +{ + PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); + + QLIST_REMOVE(host_bridge, next); +} + PCIBus *pci_device_root_bus(const PCIDevice *d) { PCIBus *bus = pci_get_bus(d); @@ -379,6 +386,11 @@ static void pci_root_bus_init(PCIBus *bus, DeviceState *parent, pci_host_bus_register(parent); } +static void pci_bus_uninit(PCIBus *bus) +{ + pci_host_bus_unregister(BUS(bus)->parent); +} + bool pci_bus_is_express(PCIBus *bus) { return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); @@ -413,6 +425,12 @@ PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, return bus; } +void pci_root_bus_cleanup(PCIBus *bus) +{ + pci_bus_uninit(bus); + object_unparent(OBJECT(bus)); +} + void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, void *irq_opaque, int nirq) { @@ -423,6 +441,15 @@ void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); } +void pci_bus_irqs_cleanup(PCIBus *bus) +{ + bus->set_irq = NULL; + bus->map_irq = NULL; + bus->irq_opaque = NULL; + bus->nirq = 0; + g_free(bus->irq_count); +} + PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, void *irq_opaque, @@ -439,6 +466,12 @@ PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, return bus; } +void pci_unregister_root_bus(PCIBus *bus) +{ + pci_bus_irqs_cleanup(bus); + pci_root_bus_cleanup(bus); +} + int pci_bus_num(PCIBus *s) { return PCI_BUS_GET_CLASS(s)->bus_num(s); diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index b20fea0dfc..0581e9e3d4 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -995,6 +995,7 @@ void ppce500_init(MachineState *machine) * Hrm. No ELF image? Try a uImage, maybe someone is giving us an * ePAPR compliant kernel */ + loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, NULL, NULL); if (payload_size < 0) { diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 346f5e7aed..d84acef55b 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -668,11 +668,20 @@ static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) return (chip->chip_id << 7) | (core_id << 3); } -static Object *pnv_chip_power8_intc_create(PnvChip *chip, Object *child, - Error **errp) +static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, + Error **errp) { - return icp_create(child, TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), - errp); + Error *local_err = NULL; + Object *obj; + + obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), + &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + cpu->icp = ICP(obj); } /* @@ -690,10 +699,10 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) return (chip->chip_id << 8) | (core_id << 2); } -static Object *pnv_chip_power9_intc_create(PnvChip *chip, Object *child, - Error **errp) +static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, + Error **errp) { - return NULL; + return; } /* Allowed core identifiers on a POWER8 Processor Chip : @@ -1090,7 +1099,7 @@ static ICPState *pnv_icp_get(XICSFabric *xi, int pir) { PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); - return cpu ? ICP(cpu->intc) : NULL; + return cpu ? cpu->icp : NULL; } static void pnv_pic_print_info(InterruptStatsProvider *obj, @@ -1103,7 +1112,7 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj, CPU_FOREACH(cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); - icp_pic_print_info(ICP(cpu->intc), mon); + icp_pic_print_info(cpu->icp, mon); } for (i = 0; i < pnv->num_chips; i++) { diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index ad1bcc7990..b98f277f1e 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -114,7 +114,7 @@ static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp) return; } - cpu->intc = pcc->intc_create(chip, OBJECT(cpu), &local_err); + pcc->intc_create(chip, cpu, &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -190,7 +190,7 @@ err: static void pnv_unrealize_vcpu(PowerPCCPU *cpu) { qemu_unregister_reset(pnv_cpu_reset, cpu); - object_unparent(cpu->intc); + object_unparent(OBJECT(cpu->icp)); cpu_remove_sync(CPU(cpu)); object_unparent(OBJECT(cpu)); } diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 5b969127c3..8ced095063 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -207,7 +207,6 @@ static const uint64_t stat_bits[] = { void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state) { - ICSState *ics = &psi->ics; uint32_t xivr_reg; uint32_t stat_reg; uint32_t src; @@ -227,14 +226,14 @@ void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state) /* TODO: optimization, check mask here. That means * re-evaluating when unmasking */ - qemu_irq_raise(ics->qirqs[src]); + qemu_irq_raise(psi->qirqs[src]); } else { psi->regs[stat_reg] &= ~stat_bits[irq]; /* FSP and PSI are muxed so don't lower if either is still set */ if (stat_reg != PSIHB_XSCOM_CR || !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) { - qemu_irq_lower(ics->qirqs[src]); + qemu_irq_lower(psi->qirqs[src]); } else { state = true; } @@ -491,6 +490,8 @@ static void pnv_psi_realize(DeviceState *dev, Error **errp) ics_set_irq_type(ics, i, true); } + psi->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs); + /* XSCOM region for PSI registers */ pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops, psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE); diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index b8aa55d526..fc06191588 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -179,7 +179,7 @@ static void bamboo_init(MachineState *machine) CPUPPCState *env; uint64_t elf_entry; uint64_t elf_lowaddr; - hwaddr loadaddr = 0; + hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; target_long initrd_size = 0; DeviceState *dev; int success; diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 8c6f3c9577..9b6e4c60fa 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -32,8 +32,7 @@ #include "exec/address-spaces.h" #include "qemu/error-report.h" -#define DEBUG_UIC - +/*#define DEBUG_UIC*/ #ifdef DEBUG_UIC # define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 4b051c0950..84ea592749 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -402,7 +402,7 @@ static void sam460ex_init(MachineState *machine) CPUPPCState *env; PPC4xxI2CState *i2c[2]; hwaddr entry = UBOOT_ENTRY; - hwaddr loadaddr = 0; + hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; target_long initrd_size = 0; DeviceState *dev; SysBusDevice *sbdev; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 19a07c5c9d..83081defde 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -70,7 +70,6 @@ #include "hw/nmi.h" #include "hw/intc/intc.h" -#include "hw/compat.h" #include "qemu/cutils.h" #include "hw/ppc/spapr_cpu_core.h" #include "hw/mem/memory-device.h" @@ -1049,6 +1048,7 @@ static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) add_str(hypertas, "hcall-sprg0"); add_str(hypertas, "hcall-copy"); add_str(hypertas, "hcall-debug"); + add_str(hypertas, "hcall-vphn"); add_str(qemu_hypertas, "hcall-memop1"); if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { @@ -1669,7 +1669,10 @@ static void spapr_machine_reset(void) /* Load the fdt */ qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); - g_free(fdt); + g_free(spapr->fdt_blob); + spapr->fdt_size = fdt_totalsize(fdt); + spapr->fdt_initial_size = spapr->fdt_size; + spapr->fdt_blob = fdt; /* Set up the entry state */ spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); @@ -1744,12 +1747,17 @@ static int spapr_post_load(void *opaque, int version_id) return err; } - /* In earlier versions, there was no separate qdev for the PAPR + /* + * In earlier versions, there was no separate qdev for the PAPR * RTC, so the RTC offset was stored directly in sPAPREnvironment. * So when migrating from those versions, poke the incoming offset - * value into the RTC device */ + * value into the RTC device + */ if (version_id < 3) { err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); + if (err) { + return err; + } } if (kvm_enabled() && spapr->patb_entry) { @@ -1920,6 +1928,39 @@ static const VMStateDescription vmstate_spapr_irq_map = { }, }; +static bool spapr_dtb_needed(void *opaque) +{ + sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); + + return smc->update_dt_enabled; +} + +static int spapr_dtb_pre_load(void *opaque) +{ + sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; + + g_free(spapr->fdt_blob); + spapr->fdt_blob = NULL; + spapr->fdt_size = 0; + + return 0; +} + +static const VMStateDescription vmstate_spapr_dtb = { + .name = "spapr_dtb", + .version_id = 1, + .minimum_version_id = 1, + .needed = spapr_dtb_needed, + .pre_load = spapr_dtb_pre_load, + .fields = (VMStateField[]) { + VMSTATE_UINT32(fdt_initial_size, sPAPRMachineState), + VMSTATE_UINT32(fdt_size, sPAPRMachineState), + VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, sPAPRMachineState, 0, NULL, + fdt_size), + VMSTATE_END_OF_LIST() + }, +}; + static const VMStateDescription vmstate_spapr = { .name = "spapr", .version_id = 3, @@ -1949,6 +1990,7 @@ static const VMStateDescription vmstate_spapr = { &vmstate_spapr_cap_ibs, &vmstate_spapr_irq_map, &vmstate_spapr_cap_nested_kvm_hv, + &vmstate_spapr_dtb, NULL } }; @@ -2515,6 +2557,17 @@ static void spapr_init_cpus(sPAPRMachineState *spapr) } } +static PCIHostState *spapr_create_default_phb(void) +{ + DeviceState *dev; + + dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); + qdev_prop_set_uint32(dev, "index", 0); + qdev_init_nofail(dev); + + return PCI_HOST_BRIDGE(dev); +} + /* pSeries LPAR / sPAPR hardware init */ static void spapr_machine_init(MachineState *machine) { @@ -2633,11 +2686,11 @@ static void spapr_machine_init(MachineState *machine) spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); /* advertise XIVE on POWER9 machines */ - if (spapr->irq->ov5 & SPAPR_OV5_XIVE_EXPLOIT) { + if (spapr->irq->ov5 & (SPAPR_OV5_XIVE_EXPLOIT | SPAPR_OV5_XIVE_BOTH)) { if (ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, spapr->max_compat_pvr)) { spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); - } else { + } else if (spapr->irq->ov5 & SPAPR_OV5_XIVE_EXPLOIT) { error_report("XIVE-only machines require a POWER9 CPU"); exit(1); } @@ -2747,7 +2800,7 @@ static void spapr_machine_init(MachineState *machine) /* Set up PCI */ spapr_pci_rtas_init(); - phb = spapr_create_phb(spapr, 0); + phb = spapr_create_default_phb(); for (i = 0; i < nb_nics; i++) { NICInfo *nd = &nd_table[i]; @@ -3063,6 +3116,8 @@ static char *spapr_get_ic_mode(Object *obj, Error **errp) return g_strdup("xics"); } else if (spapr->irq == &spapr_irq_xive) { return g_strdup("xive"); + } else if (spapr->irq == &spapr_irq_dual) { + return g_strdup("dual"); } g_assert_not_reached(); } @@ -3076,6 +3131,8 @@ static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) spapr->irq = &spapr_irq_xics; } else if (strcmp(value, "xive") == 0) { spapr->irq = &spapr_irq_xive; + } else if (strcmp(value, "dual") == 0) { + spapr->irq = &spapr_irq_dual; } else { error_setg(errp, "Bad value for \"ic-mode\" property"); } @@ -3124,7 +3181,7 @@ static void spapr_instance_init(Object *obj) object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, spapr_set_ic_mode, NULL); object_property_set_description(obj, "ic-mode", - "Specifies the interrupt controller mode (xics, xive)", + "Specifies the interrupt controller mode (xics, xive, dual)", NULL); } @@ -3792,8 +3849,6 @@ static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, * 1TiB 64-bit MMIO windows for each PHB. */ const uint64_t base_buid = 0x800000020000000ULL; -#define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ - SPAPR_PCI_MEM64_WIN_SIZE - 1) int i; /* Sanity check natural alignments */ @@ -3841,7 +3896,7 @@ static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) { PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); - return cpu ? ICP(cpu->intc) : NULL; + return cpu ? cpu->icp : NULL; } static void spapr_pic_print_info(InterruptStatsProvider *obj, @@ -3931,6 +3986,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) hc->unplug = spapr_machine_device_unplug; smc->dr_lmb_enabled = true; + smc->update_dt_enabled = true; mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); mc->has_hotpluggable_cpus = true; smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; @@ -4021,14 +4077,14 @@ DEFINE_SPAPR_MACHINE(4_0, "4.0", true); /* * pseries-3.1 */ -#define SPAPR_COMPAT_3_1 \ - HW_COMPAT_3_1 - static void spapr_machine_3_1_class_options(MachineClass *mc) { + sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + spapr_machine_4_0_class_options(mc); - SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_1); + compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); + smc->update_dt_enabled = false; } DEFINE_SPAPR_MACHINE(3_1, "3.1", false); @@ -4036,15 +4092,13 @@ DEFINE_SPAPR_MACHINE(3_1, "3.1", false); /* * pseries-3.0 */ -#define SPAPR_COMPAT_3_0 \ - HW_COMPAT_3_0 static void spapr_machine_3_0_class_options(MachineClass *mc) { sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); spapr_machine_3_1_class_options(mc); - SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_0); + compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); smc->legacy_irq_allocation = true; smc->irq = &spapr_irq_xics_legacy; @@ -4055,25 +4109,25 @@ DEFINE_SPAPR_MACHINE(3_0, "3.0", false); /* * pseries-2.12 */ -#define SPAPR_COMPAT_2_12 \ - HW_COMPAT_2_12 \ - { \ - .driver = TYPE_POWERPC_CPU, \ - .property = "pre-3.0-migration", \ - .value = "on", \ - }, \ - { \ - .driver = TYPE_SPAPR_CPU_CORE, \ - .property = "pre-3.0-migration", \ - .value = "on", \ - }, - static void spapr_machine_2_12_class_options(MachineClass *mc) { sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + static GlobalProperty compat[] = { + { + .driver = TYPE_POWERPC_CPU, + .property = "pre-3.0-migration", + .value = "on", + }, + { + .driver = TYPE_SPAPR_CPU_CORE, + .property = "pre-3.0-migration", + .value = "on", + }, + }; spapr_machine_3_0_class_options(mc); - SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_12); + compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); + compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); /* We depend on kvm_enabled() to choose a default value for the * hpt-max-page-size capability. Of course we can't do it here @@ -4100,8 +4154,6 @@ DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); /* * pseries-2.11 */ -#define SPAPR_COMPAT_2_11 \ - HW_COMPAT_2_11 static void spapr_machine_2_11_class_options(MachineClass *mc) { @@ -4109,7 +4161,7 @@ static void spapr_machine_2_11_class_options(MachineClass *mc) spapr_machine_2_12_class_options(mc); smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; - SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); + compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); } DEFINE_SPAPR_MACHINE(2_11, "2.11", false); @@ -4117,13 +4169,11 @@ DEFINE_SPAPR_MACHINE(2_11, "2.11", false); /* * pseries-2.10 */ -#define SPAPR_COMPAT_2_10 \ - HW_COMPAT_2_10 static void spapr_machine_2_10_class_options(MachineClass *mc) { spapr_machine_2_11_class_options(mc); - SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); + compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); } DEFINE_SPAPR_MACHINE(2_10, "2.10", false); @@ -4131,20 +4181,21 @@ DEFINE_SPAPR_MACHINE(2_10, "2.10", false); /* * pseries-2.9 */ -#define SPAPR_COMPAT_2_9 \ - HW_COMPAT_2_9 \ - { \ - .driver = TYPE_POWERPC_CPU, \ - .property = "pre-2.10-migration", \ - .value = "on", \ - }, \ static void spapr_machine_2_9_class_options(MachineClass *mc) { sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + static GlobalProperty compat[] = { + { + .driver = TYPE_POWERPC_CPU, + .property = "pre-2.10-migration", + .value = "on", + }, + }; spapr_machine_2_10_class_options(mc); - SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); + compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); + compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; smc->pre_2_10_has_unused_icps = true; smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; @@ -4155,18 +4206,20 @@ DEFINE_SPAPR_MACHINE(2_9, "2.9", false); /* * pseries-2.8 */ -#define SPAPR_COMPAT_2_8 \ - HW_COMPAT_2_8 \ - { \ - .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ - .property = "pcie-extended-configuration-space", \ - .value = "off", \ - }, static void spapr_machine_2_8_class_options(MachineClass *mc) { + static GlobalProperty compat[] = { + { + .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, + .property = "pcie-extended-configuration-space", + .value = "off", + }, + }; + spapr_machine_2_9_class_options(mc); - SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); + compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); + compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); mc->numa_mem_align_shift = 23; } @@ -4175,28 +4228,6 @@ DEFINE_SPAPR_MACHINE(2_8, "2.8", false); /* * pseries-2.7 */ -#define SPAPR_COMPAT_2_7 \ - HW_COMPAT_2_7 \ - { \ - .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ - .property = "mem_win_size", \ - .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ - }, \ - { \ - .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ - .property = "mem64_win_size", \ - .value = "0", \ - }, \ - { \ - .driver = TYPE_POWERPC_CPU, \ - .property = "pre-2.8-migration", \ - .value = "on", \ - }, \ - { \ - .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ - .property = "pre-2.8-migration", \ - .value = "on", \ - }, static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, uint64_t *buid, hwaddr *pio, @@ -4250,11 +4281,34 @@ static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, static void spapr_machine_2_7_class_options(MachineClass *mc) { sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + static GlobalProperty compat[] = { + { + .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, + .property = "mem_win_size", + .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE), + }, + { + .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, + .property = "mem64_win_size", + .value = "0", + }, + { + .driver = TYPE_POWERPC_CPU, + .property = "pre-2.8-migration", + .value = "on", + }, + { + .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, + .property = "pre-2.8-migration", + .value = "on", + }, + }; spapr_machine_2_8_class_options(mc); mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); mc->default_machine_opts = "modern-hotplug-events=off"; - SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); + compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); + compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); smc->phb_placement = phb_placement_2_7; } @@ -4263,19 +4317,21 @@ DEFINE_SPAPR_MACHINE(2_7, "2.7", false); /* * pseries-2.6 */ -#define SPAPR_COMPAT_2_6 \ - HW_COMPAT_2_6 \ - { \ - .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ - .property = "ddw",\ - .value = stringify(off),\ - }, static void spapr_machine_2_6_class_options(MachineClass *mc) { + static GlobalProperty compat[] = { + { + .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, + .property = "ddw", + .value = stringify(off), + }, + }; + spapr_machine_2_7_class_options(mc); mc->has_hotpluggable_cpus = false; - SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); + compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); + compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); } DEFINE_SPAPR_MACHINE(2_6, "2.6", false); @@ -4283,21 +4339,22 @@ DEFINE_SPAPR_MACHINE(2_6, "2.6", false); /* * pseries-2.5 */ -#define SPAPR_COMPAT_2_5 \ - HW_COMPAT_2_5 \ - { \ - .driver = "spapr-vlan", \ - .property = "use-rx-buffer-pools", \ - .value = "off", \ - }, static void spapr_machine_2_5_class_options(MachineClass *mc) { sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + static GlobalProperty compat[] = { + { + .driver = "spapr-vlan", + .property = "use-rx-buffer-pools", + .value = "off", + }, + }; spapr_machine_2_6_class_options(mc); smc->use_ohci_by_default = true; - SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); + compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); + compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); } DEFINE_SPAPR_MACHINE(2_5, "2.5", false); @@ -4305,8 +4362,6 @@ DEFINE_SPAPR_MACHINE(2_5, "2.5", false); /* * pseries-2.4 */ -#define SPAPR_COMPAT_2_4 \ - HW_COMPAT_2_4 static void spapr_machine_2_4_class_options(MachineClass *mc) { @@ -4314,7 +4369,7 @@ static void spapr_machine_2_4_class_options(MachineClass *mc) spapr_machine_2_5_class_options(mc); smc->dr_lmb_enabled = false; - SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); + compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); } DEFINE_SPAPR_MACHINE(2_4, "2.4", false); @@ -4322,18 +4377,19 @@ DEFINE_SPAPR_MACHINE(2_4, "2.4", false); /* * pseries-2.3 */ -#define SPAPR_COMPAT_2_3 \ - HW_COMPAT_2_3 \ - {\ - .driver = "spapr-pci-host-bridge",\ - .property = "dynamic-reconfiguration",\ - .value = "off",\ - }, static void spapr_machine_2_3_class_options(MachineClass *mc) { + static GlobalProperty compat[] = { + { + .driver = "spapr-pci-host-bridge", + .property = "dynamic-reconfiguration", + .value = "off", + }, + }; spapr_machine_2_4_class_options(mc); - SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); + compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); + compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); } DEFINE_SPAPR_MACHINE(2_3, "2.3", false); @@ -4341,18 +4397,19 @@ DEFINE_SPAPR_MACHINE(2_3, "2.3", false); * pseries-2.2 */ -#define SPAPR_COMPAT_2_2 \ - HW_COMPAT_2_2 \ - {\ - .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ - .property = "mem_win_size",\ - .value = "0x20000000",\ - }, - static void spapr_machine_2_2_class_options(MachineClass *mc) { + static GlobalProperty compat[] = { + { + .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, + .property = "mem_win_size", + .value = "0x20000000", + }, + }; + spapr_machine_2_3_class_options(mc); - SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); + compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); + compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; } DEFINE_SPAPR_MACHINE(2_2, "2.2", false); @@ -4360,13 +4417,11 @@ DEFINE_SPAPR_MACHINE(2_2, "2.2", false); /* * pseries-2.1 */ -#define SPAPR_COMPAT_2_1 \ - HW_COMPAT_2_1 static void spapr_machine_2_1_class_options(MachineClass *mc) { spapr_machine_2_2_class_options(mc); - SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); + compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); } DEFINE_SPAPR_MACHINE(2_1, "2.1", false); diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 82666436e9..0405306d1e 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -194,7 +194,12 @@ static void spapr_unrealize_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc) vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data); } qemu_unregister_reset(spapr_cpu_reset, cpu); - object_unparent(cpu->intc); + if (cpu->icp) { + object_unparent(OBJECT(cpu->icp)); + } + if (cpu->tctx) { + object_unparent(OBJECT(cpu->tctx)); + } cpu_remove_sync(CPU(cpu)); object_unparent(OBJECT(cpu)); } @@ -232,7 +237,7 @@ static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr, qemu_register_reset(spapr_cpu_reset, cpu); spapr_cpu_reset(cpu); - cpu->intc = spapr->irq->cpu_intc_create(spapr, OBJECT(cpu), &local_err); + spapr->irq->cpu_intc_create(spapr, cpu, &local_err); if (local_err) { goto error_unregister; } diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index ae913d070f..17bcaa3822 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1654,6 +1654,17 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, (spapr_h_cas_compose_response(spapr, args[1], args[2], ov5_updates) != 0); } + + /* + * Generate a machine reset when we have an update of the + * interrupt mode. Only required when the machine supports both + * modes. + */ + if (!spapr->cas_reboot) { + spapr->cas_reboot = spapr_ovec_test(ov5_updates, OV5_XIVE_EXPLOIT) + && spapr->irq->ov5 & SPAPR_OV5_XIVE_BOTH; + } + spapr_ovec_cleanup(ov5_updates); if (spapr->cas_reboot) { @@ -1663,6 +1674,42 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, return H_SUCCESS; } +static target_ulong h_home_node_associativity(PowerPCCPU *cpu, + sPAPRMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + target_ulong flags = args[0]; + target_ulong procno = args[1]; + PowerPCCPU *tcpu; + int idx; + + /* only support procno from H_REGISTER_VPA */ + if (flags != 0x1) { + return H_FUNCTION; + } + + tcpu = spapr_find_cpu(procno); + if (tcpu == NULL) { + return H_P2; + } + + /* sequence is the same as in the "ibm,associativity" property */ + + idx = 0; +#define ASSOCIATIVITY(a, b) (((uint64_t)(a) << 32) | \ + ((uint64_t)(b) & 0xffffffff)) + args[idx++] = ASSOCIATIVITY(0, 0); + args[idx++] = ASSOCIATIVITY(0, tcpu->node_id); + args[idx++] = ASSOCIATIVITY(procno, -1); + for ( ; idx < 6; idx++) { + args[idx] = -1; + } +#undef ASSOCIATIVITY + + return H_SUCCESS; +} + static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, sPAPRMachineState *spapr, target_ulong opcode, @@ -1717,6 +1764,46 @@ static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, args[0] = characteristics; args[1] = behaviour; + return H_SUCCESS; +} + +static target_ulong h_update_dt(PowerPCCPU *cpu, sPAPRMachineState *spapr, + target_ulong opcode, target_ulong *args) +{ + target_ulong dt = ppc64_phys_to_real(args[0]); + struct fdt_header hdr = { 0 }; + unsigned cb; + sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); + void *fdt; + + cpu_physical_memory_read(dt, &hdr, sizeof(hdr)); + cb = fdt32_to_cpu(hdr.totalsize); + + if (!smc->update_dt_enabled) { + return H_SUCCESS; + } + + /* Check that the fdt did not grow out of proportion */ + if (cb > spapr->fdt_initial_size * 2) { + trace_spapr_update_dt_failed_size(spapr->fdt_initial_size, cb, + fdt32_to_cpu(hdr.magic)); + return H_PARAMETER; + } + + fdt = g_malloc0(cb); + cpu_physical_memory_read(dt, fdt, cb); + + /* Check the fdt consistency */ + if (fdt_check_full(fdt, cb)) { + trace_spapr_update_dt_failed_check(spapr->fdt_initial_size, cb, + fdt32_to_cpu(hdr.magic)); + return H_PARAMETER; + } + + g_free(spapr->fdt_blob); + spapr->fdt_size = cb; + spapr->fdt_blob = fdt; + trace_spapr_update_dt(cb); return H_SUCCESS; } @@ -1822,6 +1909,12 @@ static void hypercall_register_types(void) /* ibm,client-architecture-support support */ spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); + + spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); + + /* Virtual Processor Home Node */ + spapr_register_hypercall(H_HOME_NODE_ASSOCIATIVITY, + h_home_node_associativity); } type_init(hypercall_register_types) diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 7b3b5afec2..5fce72fe0f 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -171,7 +171,7 @@ static qemu_irq spapr_qirq_xics(sPAPRMachineState *spapr, int irq) uint32_t srcno = irq - ics->offset; if (ics_valid_irq(ics, irq)) { - return ics->qirqs[srcno]; + return spapr->qirqs[srcno]; } return NULL; @@ -184,16 +184,26 @@ static void spapr_irq_print_info_xics(sPAPRMachineState *spapr, Monitor *mon) CPU_FOREACH(cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); - icp_pic_print_info(ICP(cpu->intc), mon); + icp_pic_print_info(cpu->icp, mon); } ics_pic_print_info(spapr->ics, mon); } -static Object *spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr, - Object *cpu, Error **errp) +static void spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr, + PowerPCCPU *cpu, Error **errp) { - return icp_create(cpu, spapr->icp_type, XICS_FABRIC(spapr), errp); + Error *local_err = NULL; + Object *obj; + + obj = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr), + &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + cpu->icp = ICP(obj); } static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id) @@ -202,12 +212,29 @@ static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id) CPUState *cs; CPU_FOREACH(cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); - icp_resend(ICP(cpu->intc)); + icp_resend(cpu->icp); } } return 0; } +static void spapr_irq_set_irq_xics(void *opaque, int srcno, int val) +{ + sPAPRMachineState *spapr = opaque; + MachineState *machine = MACHINE(opaque); + + if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) { + ics_kvm_set_irq(spapr->ics, srcno, val); + } else { + ics_simple_set_irq(spapr->ics, srcno, val); + } +} + +static void spapr_irq_reset_xics(sPAPRMachineState *spapr, Error **errp) +{ + /* TODO: create the KVM XICS device */ +} + #define SPAPR_IRQ_XICS_NR_IRQS 0x1000 #define SPAPR_IRQ_XICS_NR_MSIS \ (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI) @@ -225,6 +252,8 @@ sPAPRIrq spapr_irq_xics = { .dt_populate = spapr_dt_xics, .cpu_intc_create = spapr_irq_cpu_intc_create_xics, .post_load = spapr_irq_post_load_xics, + .reset = spapr_irq_reset_xics, + .set_irq = spapr_irq_set_irq_xics, }; /* @@ -284,7 +313,16 @@ static void spapr_irq_free_xive(sPAPRMachineState *spapr, int irq, int num) static qemu_irq spapr_qirq_xive(sPAPRMachineState *spapr, int irq) { - return spapr_xive_qirq(spapr->xive, irq); + sPAPRXive *xive = spapr->xive; + + if (irq >= xive->nr_irqs) { + return NULL; + } + + /* The sPAPR machine/device should have claimed the IRQ before */ + assert(xive_eas_is_valid(&xive->eat[irq])); + + return spapr->qirqs[irq]; } static void spapr_irq_print_info_xive(sPAPRMachineState *spapr, @@ -295,23 +333,31 @@ static void spapr_irq_print_info_xive(sPAPRMachineState *spapr, CPU_FOREACH(cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); - xive_tctx_pic_print_info(XIVE_TCTX(cpu->intc), mon); + xive_tctx_pic_print_info(cpu->tctx, mon); } spapr_xive_pic_print_info(spapr->xive, mon); } -static Object *spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr, - Object *cpu, Error **errp) +static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr, + PowerPCCPU *cpu, Error **errp) { - Object *obj = xive_tctx_create(cpu, XIVE_ROUTER(spapr->xive), errp); + Error *local_err = NULL; + Object *obj; + + obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + cpu->tctx = XIVE_TCTX(obj); /* * (TCG) Early setting the OS CAM line for hotplugged CPUs as they - * don't benificiate from the reset of the XIVE IRQ backend + * don't beneficiate from the reset of the XIVE IRQ backend */ - spapr_xive_set_tctx_os_cam(XIVE_TCTX(obj)); - return obj; + spapr_xive_set_tctx_os_cam(cpu->tctx); } static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id) @@ -327,8 +373,18 @@ static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp) PowerPCCPU *cpu = POWERPC_CPU(cs); /* (TCG) Set the OS CAM line of the thread interrupt context. */ - spapr_xive_set_tctx_os_cam(XIVE_TCTX(cpu->intc)); + spapr_xive_set_tctx_os_cam(cpu->tctx); } + + /* Activate the XIVE MMIOs */ + spapr_xive_mmio_set_enabled(spapr->xive, true); +} + +static void spapr_irq_set_irq_xive(void *opaque, int srcno, int val) +{ + sPAPRMachineState *spapr = opaque; + + xive_source_set_irq(&spapr->xive->source, srcno, val); } /* @@ -353,6 +409,186 @@ sPAPRIrq spapr_irq_xive = { .cpu_intc_create = spapr_irq_cpu_intc_create_xive, .post_load = spapr_irq_post_load_xive, .reset = spapr_irq_reset_xive, + .set_irq = spapr_irq_set_irq_xive, +}; + +/* + * Dual XIVE and XICS IRQ backend. + * + * Both interrupt mode, XIVE and XICS, objects are created but the + * machine starts in legacy interrupt mode (XICS). It can be changed + * by the CAS negotiation process and, in that case, the new mode is + * activated after an extra machine reset. + */ + +/* + * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the + * default. + */ +static sPAPRIrq *spapr_irq_current(sPAPRMachineState *spapr) +{ + return spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) ? + &spapr_irq_xive : &spapr_irq_xics; +} + +static void spapr_irq_init_dual(sPAPRMachineState *spapr, Error **errp) +{ + MachineState *machine = MACHINE(spapr); + Error *local_err = NULL; + + if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) { + error_setg(errp, "No KVM support for the 'dual' machine"); + return; + } + + spapr_irq_xics.init(spapr, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + /* + * Align the XICS and the XIVE IRQ number space under QEMU. + * + * However, the XICS KVM device still considers that the IRQ + * numbers should start at XICS_IRQ_BASE (0x1000). Either we + * should introduce a KVM device ioctl to set the offset or ignore + * the lower 4K numbers when using the get/set ioctl of the XICS + * KVM device. The second option seems the least intrusive. + */ + spapr->ics->offset = 0; + + spapr_irq_xive.init(spapr, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } +} + +static int spapr_irq_claim_dual(sPAPRMachineState *spapr, int irq, bool lsi, + Error **errp) +{ + Error *local_err = NULL; + int ret; + + ret = spapr_irq_xics.claim(spapr, irq, lsi, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return ret; + } + + ret = spapr_irq_xive.claim(spapr, irq, lsi, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return ret; + } + + return ret; +} + +static void spapr_irq_free_dual(sPAPRMachineState *spapr, int irq, int num) +{ + spapr_irq_xics.free(spapr, irq, num); + spapr_irq_xive.free(spapr, irq, num); +} + +static qemu_irq spapr_qirq_dual(sPAPRMachineState *spapr, int irq) +{ + sPAPRXive *xive = spapr->xive; + ICSState *ics = spapr->ics; + + if (irq >= spapr->irq->nr_irqs) { + return NULL; + } + + /* + * The IRQ number should have been claimed under both interrupt + * controllers. + */ + assert(!ICS_IRQ_FREE(ics, irq - ics->offset)); + assert(xive_eas_is_valid(&xive->eat[irq])); + + return spapr->qirqs[irq]; +} + +static void spapr_irq_print_info_dual(sPAPRMachineState *spapr, Monitor *mon) +{ + spapr_irq_current(spapr)->print_info(spapr, mon); +} + +static void spapr_irq_dt_populate_dual(sPAPRMachineState *spapr, + uint32_t nr_servers, void *fdt, + uint32_t phandle) +{ + spapr_irq_current(spapr)->dt_populate(spapr, nr_servers, fdt, phandle); +} + +static void spapr_irq_cpu_intc_create_dual(sPAPRMachineState *spapr, + PowerPCCPU *cpu, Error **errp) +{ + Error *local_err = NULL; + + spapr_irq_xive.cpu_intc_create(spapr, cpu, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + spapr_irq_xics.cpu_intc_create(spapr, cpu, errp); +} + +static int spapr_irq_post_load_dual(sPAPRMachineState *spapr, int version_id) +{ + /* + * Force a reset of the XIVE backend after migration. The machine + * defaults to XICS at startup. + */ + if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { + spapr_irq_xive.reset(spapr, &error_fatal); + } + + return spapr_irq_current(spapr)->post_load(spapr, version_id); +} + +static void spapr_irq_reset_dual(sPAPRMachineState *spapr, Error **errp) +{ + /* + * Deactivate the XIVE MMIOs. The XIVE backend will reenable them + * if selected. + */ + spapr_xive_mmio_set_enabled(spapr->xive, false); + + spapr_irq_current(spapr)->reset(spapr, errp); +} + +static void spapr_irq_set_irq_dual(void *opaque, int srcno, int val) +{ + sPAPRMachineState *spapr = opaque; + + spapr_irq_current(spapr)->set_irq(spapr, srcno, val); +} + +/* + * Define values in sync with the XIVE and XICS backend + */ +#define SPAPR_IRQ_DUAL_NR_IRQS 0x2000 +#define SPAPR_IRQ_DUAL_NR_MSIS (SPAPR_IRQ_DUAL_NR_IRQS - SPAPR_IRQ_MSI) + +sPAPRIrq spapr_irq_dual = { + .nr_irqs = SPAPR_IRQ_DUAL_NR_IRQS, + .nr_msis = SPAPR_IRQ_DUAL_NR_MSIS, + .ov5 = SPAPR_OV5_XIVE_BOTH, + + .init = spapr_irq_init_dual, + .claim = spapr_irq_claim_dual, + .free = spapr_irq_free_dual, + .qirq = spapr_qirq_dual, + .print_info = spapr_irq_print_info_dual, + .dt_populate = spapr_irq_dt_populate_dual, + .cpu_intc_create = spapr_irq_cpu_intc_create_dual, + .post_load = spapr_irq_post_load_dual, + .reset = spapr_irq_reset_dual, + .set_irq = spapr_irq_set_irq_dual }; /* @@ -366,6 +602,9 @@ void spapr_irq_init(sPAPRMachineState *spapr, Error **errp) } spapr->irq->init(spapr, errp); + + spapr->qirqs = qemu_allocate_irqs(spapr->irq->set_irq, spapr, + spapr->irq->nr_irqs); } int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp) @@ -465,4 +704,5 @@ sPAPRIrq spapr_irq_xics_legacy = { .dt_populate = spapr_dt_xics, .cpu_intc_create = spapr_irq_cpu_intc_create_xics, .post_load = spapr_irq_post_load_xics, + .set_irq = spapr_irq_set_irq_xics, }; diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index bfb02ee96b..b74f2632ec 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1988,17 +1988,6 @@ static const TypeInfo spapr_phb_info = { } }; -PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index) -{ - DeviceState *dev; - - dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE); - qdev_prop_set_uint32(dev, "index", index); - qdev_init_nofail(dev); - - return PCI_HOST_BRIDGE(dev); -} - typedef struct sPAPRFDT { void *fdt; int node_off; diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index dc5e65aee9..0af155ed32 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -22,6 +22,9 @@ spapr_cas_pvr_try(uint32_t pvr) "0x%x" spapr_cas_pvr(uint32_t cur_pvr, bool explicit_match, uint32_t new_pvr) "current=0x%x, explicit_match=%u, new=0x%x" spapr_h_resize_hpt_prepare(uint64_t flags, uint64_t shift) "flags=0x%"PRIx64", shift=%"PRIu64 spapr_h_resize_hpt_commit(uint64_t flags, uint64_t shift) "flags=0x%"PRIx64", shift=%"PRIu64 +spapr_update_dt(unsigned cb) "New blob %u bytes" +spapr_update_dt_failed_size(unsigned cbold, unsigned cbnew, unsigned magic) "Old blob %u bytes, new blob %u bytes, magic 0x%x" +spapr_update_dt_failed_check(unsigned cbold, unsigned cbnew, unsigned magic) "Old blob %u bytes, new blob %u bytes, magic 0x%x" # hw/ppc/spapr_iommu.c spapr_iommu_put(uint64_t liobn, uint64_t ioba, uint64_t tce, uint64_t ret) "liobn=0x%"PRIx64" ioba=0x%"PRIx64" tce=0x%"PRIx64" ret=%"PRId64 diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index fd9d0b0542..c737507053 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -28,7 +28,6 @@ #include "hw/s390x/storage-keys.h" #include "hw/s390x/storage-attributes.h" #include "hw/s390x/event-facility.h" -#include "hw/compat.h" #include "ipl.h" #include "hw/s390x/s390-virtio-ccw.h" #include "hw/s390x/css-bridge.h" @@ -651,100 +650,6 @@ bool css_migration_enabled(void) } \ type_init(ccw_machine_register_##suffix) -#define CCW_COMPAT_3_1 \ - HW_COMPAT_3_1 - -#define CCW_COMPAT_3_0 \ - HW_COMPAT_3_0 - -#define CCW_COMPAT_2_12 \ - HW_COMPAT_2_12 - -#define CCW_COMPAT_2_11 \ - HW_COMPAT_2_11 \ - {\ - .driver = TYPE_SCLP_EVENT_FACILITY,\ - .property = "allow_all_mask_sizes",\ - .value = "off",\ - }, - -#define CCW_COMPAT_2_10 \ - HW_COMPAT_2_10 - -#define CCW_COMPAT_2_9 \ - HW_COMPAT_2_9 \ - {\ - .driver = TYPE_S390_STATTRIB,\ - .property = "migration-enabled",\ - .value = "off",\ - }, - -#define CCW_COMPAT_2_8 \ - HW_COMPAT_2_8 \ - {\ - .driver = TYPE_S390_FLIC_COMMON,\ - .property = "adapter_routes_max_batch",\ - .value = "64",\ - }, - -#define CCW_COMPAT_2_7 \ - HW_COMPAT_2_7 - -#define CCW_COMPAT_2_6 \ - HW_COMPAT_2_6 \ - {\ - .driver = TYPE_S390_IPL,\ - .property = "iplbext_migration",\ - .value = "off",\ - }, {\ - .driver = TYPE_VIRTUAL_CSS_BRIDGE,\ - .property = "css_dev_path",\ - .value = "off",\ - }, - -#define CCW_COMPAT_2_5 \ - HW_COMPAT_2_5 - -#define CCW_COMPAT_2_4 \ - HW_COMPAT_2_4 \ - {\ - .driver = TYPE_S390_SKEYS,\ - .property = "migration-enabled",\ - .value = "off",\ - },{\ - .driver = "virtio-blk-ccw",\ - .property = "max_revision",\ - .value = "0",\ - },{\ - .driver = "virtio-balloon-ccw",\ - .property = "max_revision",\ - .value = "0",\ - },{\ - .driver = "virtio-serial-ccw",\ - .property = "max_revision",\ - .value = "0",\ - },{\ - .driver = "virtio-9p-ccw",\ - .property = "max_revision",\ - .value = "0",\ - },{\ - .driver = "virtio-rng-ccw",\ - .property = "max_revision",\ - .value = "0",\ - },{\ - .driver = "virtio-net-ccw",\ - .property = "max_revision",\ - .value = "0",\ - },{\ - .driver = "virtio-scsi-ccw",\ - .property = "max_revision",\ - .value = "0",\ - },{\ - .driver = "vhost-scsi-ccw",\ - .property = "max_revision",\ - .value = "0",\ - }, - static void ccw_machine_4_0_instance_options(MachineState *machine) { } @@ -762,7 +667,7 @@ static void ccw_machine_3_1_instance_options(MachineState *machine) static void ccw_machine_3_1_class_options(MachineClass *mc) { ccw_machine_4_0_class_options(mc); - SET_MACHINE_COMPAT(mc, CCW_COMPAT_3_1); + compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); } DEFINE_CCW_MACHINE(3_1, "3.1", false); @@ -777,7 +682,7 @@ static void ccw_machine_3_0_class_options(MachineClass *mc) s390mc->hpage_1m_allowed = false; ccw_machine_3_1_class_options(mc); - SET_MACHINE_COMPAT(mc, CCW_COMPAT_3_0); + compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); } DEFINE_CCW_MACHINE(3_0, "3.0", false); @@ -791,7 +696,7 @@ static void ccw_machine_2_12_instance_options(MachineState *machine) static void ccw_machine_2_12_class_options(MachineClass *mc) { ccw_machine_3_0_class_options(mc); - SET_MACHINE_COMPAT(mc, CCW_COMPAT_2_12); + compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); } DEFINE_CCW_MACHINE(2_12, "2.12", false); @@ -806,8 +711,17 @@ static void ccw_machine_2_11_instance_options(MachineState *machine) static void ccw_machine_2_11_class_options(MachineClass *mc) { + static GlobalProperty compat[] = { + { + .driver = TYPE_SCLP_EVENT_FACILITY, + .property = "allow_all_mask_sizes", + .value = "off", + }, + }; + ccw_machine_2_12_class_options(mc); - SET_MACHINE_COMPAT(mc, CCW_COMPAT_2_11); + compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); + compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); } DEFINE_CCW_MACHINE(2_11, "2.11", false); @@ -819,7 +733,7 @@ static void ccw_machine_2_10_instance_options(MachineState *machine) static void ccw_machine_2_10_class_options(MachineClass *mc) { ccw_machine_2_11_class_options(mc); - SET_MACHINE_COMPAT(mc, CCW_COMPAT_2_10); + compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); } DEFINE_CCW_MACHINE(2_10, "2.10", false); @@ -836,9 +750,17 @@ static void ccw_machine_2_9_instance_options(MachineState *machine) static void ccw_machine_2_9_class_options(MachineClass *mc) { S390CcwMachineClass *s390mc = S390_MACHINE_CLASS(mc); + static GlobalProperty compat[] = { + { + .driver = TYPE_S390_STATTRIB, + .property = "migration-enabled", + .value = "off", + }, + }; ccw_machine_2_10_class_options(mc); - SET_MACHINE_COMPAT(mc, CCW_COMPAT_2_9); + compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); + compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); s390mc->css_migration_enabled = false; } DEFINE_CCW_MACHINE(2_9, "2.9", false); @@ -850,8 +772,17 @@ static void ccw_machine_2_8_instance_options(MachineState *machine) static void ccw_machine_2_8_class_options(MachineClass *mc) { + static GlobalProperty compat[] = { + { + .driver = TYPE_S390_FLIC_COMMON, + .property = "adapter_routes_max_batch", + .value = "64", + }, + }; + ccw_machine_2_9_class_options(mc); - SET_MACHINE_COMPAT(mc, CCW_COMPAT_2_8); + compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); + compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); } DEFINE_CCW_MACHINE(2_8, "2.8", false); @@ -866,7 +797,7 @@ static void ccw_machine_2_7_class_options(MachineClass *mc) s390mc->cpu_model_allowed = false; ccw_machine_2_8_class_options(mc); - SET_MACHINE_COMPAT(mc, CCW_COMPAT_2_7); + compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); } DEFINE_CCW_MACHINE(2_7, "2.7", false); @@ -878,10 +809,22 @@ static void ccw_machine_2_6_instance_options(MachineState *machine) static void ccw_machine_2_6_class_options(MachineClass *mc) { S390CcwMachineClass *s390mc = S390_MACHINE_CLASS(mc); + static GlobalProperty compat[] = { + { + .driver = TYPE_S390_IPL, + .property = "iplbext_migration", + .value = "off", + }, { + .driver = TYPE_VIRTUAL_CSS_BRIDGE, + .property = "css_dev_path", + .value = "off", + }, + }; s390mc->ri_allowed = false; ccw_machine_2_7_class_options(mc); - SET_MACHINE_COMPAT(mc, CCW_COMPAT_2_6); + compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); + compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); } DEFINE_CCW_MACHINE(2_6, "2.6", false); @@ -893,7 +836,7 @@ static void ccw_machine_2_5_instance_options(MachineState *machine) static void ccw_machine_2_5_class_options(MachineClass *mc) { ccw_machine_2_6_class_options(mc); - SET_MACHINE_COMPAT(mc, CCW_COMPAT_2_5); + compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); } DEFINE_CCW_MACHINE(2_5, "2.5", false); @@ -904,8 +847,49 @@ static void ccw_machine_2_4_instance_options(MachineState *machine) static void ccw_machine_2_4_class_options(MachineClass *mc) { + static GlobalProperty compat[] = { + { + .driver = TYPE_S390_SKEYS, + .property = "migration-enabled", + .value = "off", + },{ + .driver = "virtio-blk-ccw", + .property = "max_revision", + .value = "0", + },{ + .driver = "virtio-balloon-ccw", + .property = "max_revision", + .value = "0", + },{ + .driver = "virtio-serial-ccw", + .property = "max_revision", + .value = "0", + },{ + .driver = "virtio-9p-ccw", + .property = "max_revision", + .value = "0", + },{ + .driver = "virtio-rng-ccw", + .property = "max_revision", + .value = "0", + },{ + .driver = "virtio-net-ccw", + .property = "max_revision", + .value = "0", + },{ + .driver = "virtio-scsi-ccw", + .property = "max_revision", + .value = "0", + },{ + .driver = "vhost-scsi-ccw", + .property = "max_revision", + .value = "0", + }, + }; + ccw_machine_2_5_class_options(mc); - SET_MACHINE_COMPAT(mc, CCW_COMPAT_2_4); + compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); + compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); } DEFINE_CCW_MACHINE(2_4, "2.4", false); diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 639906cca3..709ee37e08 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -37,7 +37,6 @@ #include "net/net.h" #include "hw/boards.h" #include "hw/scsi/esp.h" -#include "hw/isa/isa.h" #include "hw/nvram/sun_nvram.h" #include "hw/nvram/chrp_nvram.h" #include "hw/nvram/fw_cfg.h" diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index b32194d153..0e9a4530f8 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -23,6 +23,7 @@ common-obj-$(CONFIG_IMX) += imx_gpt.o common-obj-$(CONFIG_LM32) += lm32_timer.o common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-rtc.o +common-obj-$(CONFIG_NRF51_SOC) += nrf51_timer.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o diff --git a/hw/timer/i8254.c b/hw/timer/i8254.c index 1057850808..20f834e7da 100644 --- a/hw/timer/i8254.c +++ b/hw/timer/i8254.c @@ -23,7 +23,6 @@ */ #include "qemu/osdep.h" #include "hw/hw.h" -#include "hw/isa/isa.h" #include "qemu/timer.h" #include "hw/timer/i8254.h" #include "hw/timer/i8254_internal.h" diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c new file mode 100644 index 0000000000..0c90662896 --- /dev/null +++ b/hw/timer/nrf51_timer.c @@ -0,0 +1,393 @@ +/* + * nRF51 System-on-Chip Timer peripheral + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf + * + * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de> + * Copyright (c) 2019 Red Hat, Inc. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/arm/nrf51.h" +#include "hw/timer/nrf51_timer.h" +#include "trace.h" + +#define TIMER_CLK_FREQ 16000000UL + +static uint32_t const bitwidths[] = {16, 8, 24, 32}; + +static uint32_t ns_to_ticks(NRF51TimerState *s, int64_t ns) +{ + uint32_t freq = TIMER_CLK_FREQ >> s->prescaler; + + return muldiv64(ns, freq, NANOSECONDS_PER_SECOND); +} + +static int64_t ticks_to_ns(NRF51TimerState *s, uint32_t ticks) +{ + uint32_t freq = TIMER_CLK_FREQ >> s->prescaler; + + return muldiv64(ticks, NANOSECONDS_PER_SECOND, freq); +} + +/* Returns number of ticks since last call */ +static uint32_t update_counter(NRF51TimerState *s, int64_t now) +{ + uint32_t ticks = ns_to_ticks(s, now - s->update_counter_ns); + + s->counter = (s->counter + ticks) % BIT(bitwidths[s->bitmode]); + s->update_counter_ns = now; + return ticks; +} + +/* Assumes s->counter is up-to-date */ +static void rearm_timer(NRF51TimerState *s, int64_t now) +{ + int64_t min_ns = INT64_MAX; + size_t i; + + for (i = 0; i < NRF51_TIMER_REG_COUNT; i++) { + int64_t delta_ns; + + if (s->events_compare[i]) { + continue; /* already expired, ignore it for now */ + } + + if (s->cc[i] <= s->counter) { + delta_ns = ticks_to_ns(s, BIT(bitwidths[s->bitmode]) - + s->counter + s->cc[i]); + } else { + delta_ns = ticks_to_ns(s, s->cc[i] - s->counter); + } + + if (delta_ns < min_ns) { + min_ns = delta_ns; + } + } + + if (min_ns != INT64_MAX) { + timer_mod_ns(&s->timer, now + min_ns); + } +} + +static void update_irq(NRF51TimerState *s) +{ + bool flag = false; + size_t i; + + for (i = 0; i < NRF51_TIMER_REG_COUNT; i++) { + flag |= s->events_compare[i] && extract32(s->inten, 16 + i, 1); + } + qemu_set_irq(s->irq, flag); +} + +static void timer_expire(void *opaque) +{ + NRF51TimerState *s = NRF51_TIMER(opaque); + int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint32_t cc_remaining[NRF51_TIMER_REG_COUNT]; + bool should_stop = false; + uint32_t ticks; + size_t i; + + for (i = 0; i < NRF51_TIMER_REG_COUNT; i++) { + if (s->cc[i] > s->counter) { + cc_remaining[i] = s->cc[i] - s->counter; + } else { + cc_remaining[i] = BIT(bitwidths[s->bitmode]) - + s->counter + s->cc[i]; + } + } + + ticks = update_counter(s, now); + + for (i = 0; i < NRF51_TIMER_REG_COUNT; i++) { + if (cc_remaining[i] <= ticks) { + s->events_compare[i] = 1; + + if (s->shorts & BIT(i)) { + s->timer_start_ns = now; + s->update_counter_ns = s->timer_start_ns; + s->counter = 0; + } + + should_stop |= s->shorts & BIT(i + 8); + } + } + + update_irq(s); + + if (should_stop) { + s->running = false; + timer_del(&s->timer); + } else { + rearm_timer(s, now); + } +} + +static void counter_compare(NRF51TimerState *s) +{ + uint32_t counter = s->counter; + size_t i; + + for (i = 0; i < NRF51_TIMER_REG_COUNT; i++) { + if (counter == s->cc[i]) { + s->events_compare[i] = 1; + + if (s->shorts & BIT(i)) { + s->counter = 0; + } + } + } +} + +static uint64_t nrf51_timer_read(void *opaque, hwaddr offset, unsigned int size) +{ + NRF51TimerState *s = NRF51_TIMER(opaque); + uint64_t r = 0; + + switch (offset) { + case NRF51_TIMER_EVENT_COMPARE_0 ... NRF51_TIMER_EVENT_COMPARE_3: + r = s->events_compare[(offset - NRF51_TIMER_EVENT_COMPARE_0) / 4]; + break; + case NRF51_TIMER_REG_SHORTS: + r = s->shorts; + break; + case NRF51_TIMER_REG_INTENSET: + r = s->inten; + break; + case NRF51_TIMER_REG_INTENCLR: + r = s->inten; + break; + case NRF51_TIMER_REG_MODE: + r = s->mode; + break; + case NRF51_TIMER_REG_BITMODE: + r = s->bitmode; + break; + case NRF51_TIMER_REG_PRESCALER: + r = s->prescaler; + break; + case NRF51_TIMER_REG_CC0 ... NRF51_TIMER_REG_CC3: + r = s->cc[(offset - NRF51_TIMER_REG_CC0) / 4]; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad read offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + trace_nrf51_timer_read(offset, r, size); + + return r; +} + +static void nrf51_timer_write(void *opaque, hwaddr offset, + uint64_t value, unsigned int size) +{ + NRF51TimerState *s = NRF51_TIMER(opaque); + uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + size_t idx; + + trace_nrf51_timer_write(offset, value, size); + + switch (offset) { + case NRF51_TIMER_TASK_START: + if (value == NRF51_TRIGGER_TASK && s->mode == NRF51_TIMER_TIMER) { + s->running = true; + s->timer_start_ns = now - ticks_to_ns(s, s->counter); + s->update_counter_ns = s->timer_start_ns; + rearm_timer(s, now); + } + break; + case NRF51_TIMER_TASK_STOP: + case NRF51_TIMER_TASK_SHUTDOWN: + if (value == NRF51_TRIGGER_TASK) { + s->running = false; + timer_del(&s->timer); + } + break; + case NRF51_TIMER_TASK_COUNT: + if (value == NRF51_TRIGGER_TASK && s->mode == NRF51_TIMER_COUNTER) { + s->counter = (s->counter + 1) % BIT(bitwidths[s->bitmode]); + counter_compare(s); + } + break; + case NRF51_TIMER_TASK_CLEAR: + if (value == NRF51_TRIGGER_TASK) { + s->timer_start_ns = now; + s->update_counter_ns = s->timer_start_ns; + s->counter = 0; + if (s->running) { + rearm_timer(s, now); + } + } + break; + case NRF51_TIMER_TASK_CAPTURE_0 ... NRF51_TIMER_TASK_CAPTURE_3: + if (value == NRF51_TRIGGER_TASK) { + if (s->running) { + timer_expire(s); /* update counter and all state */ + } + + idx = (offset - NRF51_TIMER_TASK_CAPTURE_0) / 4; + s->cc[idx] = s->counter; + } + break; + case NRF51_TIMER_EVENT_COMPARE_0 ... NRF51_TIMER_EVENT_COMPARE_3: + if (value == NRF51_EVENT_CLEAR) { + s->events_compare[(offset - NRF51_TIMER_EVENT_COMPARE_0) / 4] = 0; + + if (s->running) { + timer_expire(s); /* update counter and all state */ + } + } + break; + case NRF51_TIMER_REG_SHORTS: + s->shorts = value & NRF51_TIMER_REG_SHORTS_MASK; + break; + case NRF51_TIMER_REG_INTENSET: + s->inten |= value & NRF51_TIMER_REG_INTEN_MASK; + break; + case NRF51_TIMER_REG_INTENCLR: + s->inten &= ~(value & NRF51_TIMER_REG_INTEN_MASK); + break; + case NRF51_TIMER_REG_MODE: + s->mode = value; + break; + case NRF51_TIMER_REG_BITMODE: + if (s->mode == NRF51_TIMER_TIMER && s->running) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: erroneous change of BITMODE while timer is running\n", + __func__); + } + s->bitmode = value & NRF51_TIMER_REG_BITMODE_MASK; + break; + case NRF51_TIMER_REG_PRESCALER: + if (s->mode == NRF51_TIMER_TIMER && s->running) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: erroneous change of PRESCALER while timer is running\n", + __func__); + } + s->prescaler = value & NRF51_TIMER_REG_PRESCALER_MASK; + break; + case NRF51_TIMER_REG_CC0 ... NRF51_TIMER_REG_CC3: + if (s->running) { + timer_expire(s); /* update counter */ + } + + idx = (offset - NRF51_TIMER_REG_CC0) / 4; + s->cc[idx] = value % BIT(bitwidths[s->bitmode]); + + if (s->running) { + rearm_timer(s, now); + } + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad write offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + + update_irq(s); +} + +static const MemoryRegionOps rng_ops = { + .read = nrf51_timer_read, + .write = nrf51_timer_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4, +}; + +static void nrf51_timer_init(Object *obj) +{ + NRF51TimerState *s = NRF51_TIMER(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &rng_ops, s, + TYPE_NRF51_TIMER, NRF51_TIMER_SIZE); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); + + timer_init_ns(&s->timer, QEMU_CLOCK_VIRTUAL, timer_expire, s); +} + +static void nrf51_timer_reset(DeviceState *dev) +{ + NRF51TimerState *s = NRF51_TIMER(dev); + + timer_del(&s->timer); + s->timer_start_ns = 0x00; + s->update_counter_ns = 0x00; + s->counter = 0x00; + s->running = false; + + memset(s->events_compare, 0x00, sizeof(s->events_compare)); + memset(s->cc, 0x00, sizeof(s->cc)); + + s->shorts = 0x00; + s->inten = 0x00; + s->mode = 0x00; + s->bitmode = 0x00; + s->prescaler = 0x00; +} + +static int nrf51_timer_post_load(void *opaque, int version_id) +{ + NRF51TimerState *s = NRF51_TIMER(opaque); + + if (s->running && s->mode == NRF51_TIMER_TIMER) { + timer_expire(s); + } + return 0; +} + +static const VMStateDescription vmstate_nrf51_timer = { + .name = TYPE_NRF51_TIMER, + .version_id = 1, + .post_load = nrf51_timer_post_load, + .fields = (VMStateField[]) { + VMSTATE_TIMER(timer, NRF51TimerState), + VMSTATE_INT64(timer_start_ns, NRF51TimerState), + VMSTATE_INT64(update_counter_ns, NRF51TimerState), + VMSTATE_UINT32(counter, NRF51TimerState), + VMSTATE_BOOL(running, NRF51TimerState), + VMSTATE_UINT8_ARRAY(events_compare, NRF51TimerState, + NRF51_TIMER_REG_COUNT), + VMSTATE_UINT32_ARRAY(cc, NRF51TimerState, NRF51_TIMER_REG_COUNT), + VMSTATE_UINT32(shorts, NRF51TimerState), + VMSTATE_UINT32(inten, NRF51TimerState), + VMSTATE_UINT32(mode, NRF51TimerState), + VMSTATE_UINT32(bitmode, NRF51TimerState), + VMSTATE_UINT32(prescaler, NRF51TimerState), + VMSTATE_END_OF_LIST() + } +}; + +static void nrf51_timer_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = nrf51_timer_reset; + dc->vmsd = &vmstate_nrf51_timer; +} + +static const TypeInfo nrf51_timer_info = { + .name = TYPE_NRF51_TIMER, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NRF51TimerState), + .instance_init = nrf51_timer_init, + .class_init = nrf51_timer_class_init +}; + +static void nrf51_timer_register_types(void) +{ + type_register_static(&nrf51_timer_info); +} + +type_init(nrf51_timer_register_types) diff --git a/hw/timer/trace-events b/hw/timer/trace-events index 75bd3b1042..0144a68951 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -72,3 +72,8 @@ sun4v_rtc_write(uint64_t addr, uint64_t value) "write: addr 0x%" PRIx64 " value # hw/timer/xlnx-zynqmp-rtc.c xlnx_zynqmp_rtc_gettime(int year, int month, int day, int hour, int min, int sec) "Get time from host: %d-%d-%d %2d:%02d:%02d" + +# hw/timer/nrf51_timer.c +nrf51_timer_read(uint64_t addr, uint32_t value, unsigned size) "read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" +nrf51_timer_write(uint64_t addr, uint32_t value, unsigned size) "write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" + diff --git a/hw/usb/bus.c b/hw/usb/bus.c index bf796d67e6..6fffab7bfa 100644 --- a/hw/usb/bus.c +++ b/hw/usb/bus.c @@ -59,12 +59,6 @@ static int usb_device_post_load(void *opaque, int version_id) } else { dev->attached = true; } - if (dev->setup_index < 0 || - dev->setup_len < 0 || - dev->setup_index > dev->setup_len || - dev->setup_len > sizeof(dev->data_buf)) { - return -EINVAL; - } return 0; } diff --git a/hw/usb/ccid-card-emulated.c b/hw/usb/ccid-card-emulated.c index 25976ed84f..e0457d305b 100644 --- a/hw/usb/ccid-card-emulated.c +++ b/hw/usb/ccid-card-emulated.c @@ -549,6 +549,8 @@ static void emulated_realize(CCIDCardState *base, Error **errp) qemu_thread_create(&card->apdu_thread_id, "ccid/apdu", handle_apdu_thread, card, QEMU_THREAD_JOINABLE); + return; + out2: clean_event_notifier(card); out1: diff --git a/hw/usb/dev-mtp.c b/hw/usb/dev-mtp.c index 6098005cd4..b19b576278 100644 --- a/hw/usb/dev-mtp.c +++ b/hw/usb/dev-mtp.c @@ -1729,6 +1729,7 @@ static void usb_mtp_write_metadata(MTPState *s, uint64_t dlen) if (strchr(filename, '/')) { usb_mtp_queue_result(s, RES_PARAMETER_NOT_SUPPORTED, d->trans, 0, 0, 0, 0); + g_free(filename); return; } diff --git a/hw/usb/hcd-ehci-pci.c b/hw/usb/hcd-ehci-pci.c index 8c0fc53a26..69abbf7b7b 100644 --- a/hw/usb/hcd-ehci-pci.c +++ b/hw/usb/hcd-ehci-pci.c @@ -230,56 +230,3 @@ static void ehci_pci_register_types(void) } type_init(ehci_pci_register_types) - -struct ehci_companions { - const char *name; - int func; - int port; -}; - -static const struct ehci_companions ich9_1d[] = { - { .name = "ich9-usb-uhci1", .func = 0, .port = 0 }, - { .name = "ich9-usb-uhci2", .func = 1, .port = 2 }, - { .name = "ich9-usb-uhci3", .func = 2, .port = 4 }, -}; - -static const struct ehci_companions ich9_1a[] = { - { .name = "ich9-usb-uhci4", .func = 0, .port = 0 }, - { .name = "ich9-usb-uhci5", .func = 1, .port = 2 }, - { .name = "ich9-usb-uhci6", .func = 2, .port = 4 }, -}; - -int ehci_create_ich9_with_companions(PCIBus *bus, int slot) -{ - const struct ehci_companions *comp; - PCIDevice *ehci, *uhci; - BusState *usbbus; - const char *name; - int i; - - switch (slot) { - case 0x1d: - name = "ich9-usb-ehci1"; - comp = ich9_1d; - break; - case 0x1a: - name = "ich9-usb-ehci2"; - comp = ich9_1a; - break; - default: - return -1; - } - - ehci = pci_create_multifunction(bus, PCI_DEVFN(slot, 7), true, name); - qdev_init_nofail(&ehci->qdev); - usbbus = QLIST_FIRST(&ehci->qdev.child_bus); - - for (i = 0; i < 3; i++) { - uhci = pci_create_multifunction(bus, PCI_DEVFN(slot, comp[i].func), - true, comp[i].name); - qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); - qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); - qdev_init_nofail(&uhci->qdev); - } - return 0; -} diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c index 3b83beb140..331faf8bc3 100644 --- a/hw/usb/hcd-ehci-sysbus.c +++ b/hw/usb/hcd-ehci-sysbus.c @@ -94,6 +94,22 @@ static const TypeInfo ehci_type_info = { .class_size = sizeof(SysBusEHCIClass), }; +static void ehci_platform_class_init(ObjectClass *oc, void *data) +{ + SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); + DeviceClass *dc = DEVICE_CLASS(oc); + + sec->capsbase = 0x0; + sec->opregbase = 0x20; + set_bit(DEVICE_CATEGORY_USB, dc->categories); +} + +static const TypeInfo ehci_platform_type_info = { + .name = TYPE_PLATFORM_EHCI, + .parent = TYPE_SYS_BUS_EHCI, + .class_init = ehci_platform_class_init, +}; + static void ehci_xlnx_class_init(ObjectClass *oc, void *data) { SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); @@ -245,6 +261,7 @@ static const TypeInfo ehci_fusbh200_type_info = { static void ehci_sysbus_register_types(void) { type_register_static(&ehci_type_info); + type_register_static(&ehci_platform_type_info); type_register_static(&ehci_xlnx_type_info); type_register_static(&ehci_exynos4210_type_info); type_register_static(&ehci_tegra2_type_info); diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h index 0bc364b286..cd30b5d5e0 100644 --- a/hw/usb/hcd-ehci.h +++ b/hw/usb/hcd-ehci.h @@ -342,6 +342,7 @@ typedef struct EHCIPCIState { #define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb" +#define TYPE_PLATFORM_EHCI "platform-ehci-usb" #define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb" #define TYPE_TEGRA2_EHCI "tegra2-ehci-usb" #define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb" diff --git a/hw/xen/xen-common.c b/hw/xen/xen-common.c index 6ec14c73ca..d51148b6b3 100644 --- a/hw/xen/xen-common.c +++ b/hw/xen/xen-common.c @@ -159,33 +159,34 @@ static int xen_init(MachineState *ms) return 0; } -static GlobalProperty xen_compat_props[] = { - { - .driver = "migration", - .property = "store-global-state", - .value = "off", - }, - { - .driver = "migration", - .property = "send-configuration", - .value = "off", - }, - { - .driver = "migration", - .property = "send-section-footer", - .value = "off", - }, - { /* end of list */ }, -}; - static void xen_accel_class_init(ObjectClass *oc, void *data) { AccelClass *ac = ACCEL_CLASS(oc); + static GlobalProperty compat[] = { + { + .driver = "migration", + .property = "store-global-state", + .value = "off", + }, + { + .driver = "migration", + .property = "send-configuration", + .value = "off", + }, + { + .driver = "migration", + .property = "send-section-footer", + .value = "off", + } + }; + ac->name = "Xen"; ac->init_machine = xen_init; ac->setup_post = xen_setup_post; ac->allowed = &xen_allowed; - ac->global_props = xen_compat_props; + ac->compat_props = g_ptr_array_new(); + + compat_props_add(ac->compat_props, compat, G_N_ELEMENTS(compat)); } #define TYPE_XEN_ACCEL ACCEL_CLASS_NAME("xen") diff --git a/include/block/nbd.h b/include/block/nbd.h index 6a5bfe5d55..65402d3396 100644 --- a/include/block/nbd.h +++ b/include/block/nbd.h @@ -343,5 +343,10 @@ static inline bool nbd_reply_is_structured(NBDReply *reply) } const char *nbd_reply_type_lookup(uint16_t type); +const char *nbd_opt_lookup(uint32_t opt); +const char *nbd_rep_lookup(uint32_t rep); +const char *nbd_info_lookup(uint16_t info); +const char *nbd_cmd_lookup(uint16_t info); +const char *nbd_err_lookup(int err); #endif diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index efb8fc8123..389e128d0f 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -35,6 +35,7 @@ typedef struct AwA10State { AwA10PICState intc; AwEmacState emac; AllwinnerAHCIState sata; + MemoryRegion sram_a; } AwA10State; #define ALLWINNER_H_ diff --git a/include/hw/arm/nrf51.h b/include/hw/arm/nrf51.h new file mode 100644 index 0000000000..175bb6c301 --- /dev/null +++ b/include/hw/arm/nrf51.h @@ -0,0 +1,45 @@ +/* + * Nordic Semiconductor nRF51 Series SOC Common Defines + * + * This file hosts generic defines used in various nRF51 peripheral devices. + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf + * + * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de> + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#ifndef NRF51_H +#define NRF51_H + +#define NRF51_FLASH_BASE 0x00000000 +#define NRF51_FICR_BASE 0x10000000 +#define NRF51_FICR_SIZE 0x00000100 +#define NRF51_UICR_BASE 0x10001000 +#define NRF51_SRAM_BASE 0x20000000 + +#define NRF51_IOMEM_BASE 0x40000000 +#define NRF51_IOMEM_SIZE 0x20000000 + +#define NRF51_UART_BASE 0x40002000 +#define NRF51_TIMER_BASE 0x40008000 +#define NRF51_TIMER_SIZE 0x00001000 +#define NRF51_RNG_BASE 0x4000D000 +#define NRF51_NVMC_BASE 0x4001E000 +#define NRF51_GPIO_BASE 0x50000000 + +#define NRF51_PRIVATE_BASE 0xF0000000 +#define NRF51_PRIVATE_SIZE 0x10000000 + +#define NRF51_PAGE_SIZE 1024 + +/* Trigger */ +#define NRF51_TRIGGER_TASK 0x01 + +/* Events */ +#define NRF51_EVENT_CLEAR 0x00 + +#endif diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index 73fc92e9a8..e06f0304b4 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -13,11 +13,16 @@ #include "hw/sysbus.h" #include "hw/arm/armv7m.h" #include "hw/char/nrf51_uart.h" +#include "hw/misc/nrf51_rng.h" +#include "hw/gpio/nrf51_gpio.h" +#include "hw/timer/nrf51_timer.h" #define TYPE_NRF51_SOC "nrf51-soc" #define NRF51_SOC(obj) \ OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC) +#define NRF51_NUM_TIMERS 3 + typedef struct NRF51State { /*< private >*/ SysBusDevice parent_obj; @@ -26,10 +31,14 @@ typedef struct NRF51State { ARMv7MState cpu; NRF51UARTState uart; + NRF51RNGState rng; + NRF51GPIOState gpio; + NRF51TimerState timer[NRF51_NUM_TIMERS]; MemoryRegion iomem; MemoryRegion sram; MemoryRegion flash; + MemoryRegion clock; uint32_t sram_size; uint32_t flash_size; diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 98f925ab84..591515c760 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -31,6 +31,7 @@ #include "hw/display/xlnx_dp.h" #include "hw/intc/xlnx-zynqmp-ipi.h" #include "hw/timer/xlnx-zynqmp-rtc.h" +#include "hw/cpu/cluster.h" #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ @@ -77,6 +78,8 @@ typedef struct XlnxZynqMPState { DeviceState parent_obj; /*< public >*/ + CPUClusterState apu_cluster; + CPUClusterState rpu_cluster; ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; GICState gic; diff --git a/include/hw/boards.h b/include/hw/boards.h index 362384815e..02f114085f 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -69,7 +69,6 @@ int machine_kvm_shadow_mem(MachineState *machine); int machine_phandle_start(MachineState *machine); bool machine_dump_guest_core(MachineState *machine); bool machine_mem_merge(MachineState *machine); -void machine_register_compat_props(MachineState *machine); HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine); void machine_set_cpu_numa_node(MachineState *machine, const CpuInstanceProperties *props, @@ -191,7 +190,7 @@ struct MachineClass { const char *default_machine_opts; const char *default_boot_order; const char *default_display; - GArray *compat_props; + GPtrArray *compat_props; const char *hw_version; ram_addr_t default_ram_size; const char *default_cpu_type; @@ -289,20 +288,46 @@ struct MachineState { } \ type_init(machine_initfn##_register_types) -#define SET_MACHINE_COMPAT(m, COMPAT) \ - do { \ - int i; \ - static GlobalProperty props[] = { \ - COMPAT \ - { /* end of list */ } \ - }; \ - if (!m->compat_props) { \ - m->compat_props = g_array_new(false, false, sizeof(void *)); \ - } \ - for (i = 0; props[i].driver != NULL; i++) { \ - GlobalProperty *prop = &props[i]; \ - g_array_append_val(m->compat_props, prop); \ - } \ - } while (0) +extern GlobalProperty hw_compat_3_1[]; +extern const size_t hw_compat_3_1_len; + +extern GlobalProperty hw_compat_3_0[]; +extern const size_t hw_compat_3_0_len; + +extern GlobalProperty hw_compat_2_12[]; +extern const size_t hw_compat_2_12_len; + +extern GlobalProperty hw_compat_2_11[]; +extern const size_t hw_compat_2_11_len; + +extern GlobalProperty hw_compat_2_10[]; +extern const size_t hw_compat_2_10_len; + +extern GlobalProperty hw_compat_2_9[]; +extern const size_t hw_compat_2_9_len; + +extern GlobalProperty hw_compat_2_8[]; +extern const size_t hw_compat_2_8_len; + +extern GlobalProperty hw_compat_2_7[]; +extern const size_t hw_compat_2_7_len; + +extern GlobalProperty hw_compat_2_6[]; +extern const size_t hw_compat_2_6_len; + +extern GlobalProperty hw_compat_2_5[]; +extern const size_t hw_compat_2_5_len; + +extern GlobalProperty hw_compat_2_4[]; +extern const size_t hw_compat_2_4_len; + +extern GlobalProperty hw_compat_2_3[]; +extern const size_t hw_compat_2_3_len; + +extern GlobalProperty hw_compat_2_2[]; +extern const size_t hw_compat_2_2_len; + +extern GlobalProperty hw_compat_2_1[]; +extern const size_t hw_compat_2_1_len; #endif diff --git a/include/hw/char/nrf51_uart.h b/include/hw/char/nrf51_uart.h index e3ecb7c81c..eb1c15b490 100644 --- a/include/hw/char/nrf51_uart.h +++ b/include/hw/char/nrf51_uart.h @@ -16,7 +16,6 @@ #include "hw/registerfields.h" #define UART_FIFO_LENGTH 6 -#define UART_BASE 0x40002000 #define UART_SIZE 0x1000 #define TYPE_NRF51_UART "nrf51_soc.uart" diff --git a/include/hw/compat.h b/include/hw/compat.h deleted file mode 100644 index 3ca85b037c..0000000000 --- a/include/hw/compat.h +++ /dev/null @@ -1,299 +0,0 @@ -#ifndef HW_COMPAT_H -#define HW_COMPAT_H - -#define HW_COMPAT_3_1 \ - {\ - .driver = "pcie-root-port",\ - .property = "x-speed",\ - .value = "2_5",\ - },{\ - .driver = "pcie-root-port",\ - .property = "x-width",\ - .value = "1",\ - }, - -#define HW_COMPAT_3_0 \ - /* empty */ - -#define HW_COMPAT_2_12 \ - {\ - .driver = "migration",\ - .property = "decompress-error-check",\ - .value = "off",\ - },{\ - .driver = "hda-audio",\ - .property = "use-timer",\ - .value = "false",\ - },{\ - .driver = "cirrus-vga",\ - .property = "global-vmstate",\ - .value = "true",\ - },{\ - .driver = "VGA",\ - .property = "global-vmstate",\ - .value = "true",\ - },{\ - .driver = "vmware-svga",\ - .property = "global-vmstate",\ - .value = "true",\ - },{\ - .driver = "qxl-vga",\ - .property = "global-vmstate",\ - .value = "true",\ - }, - -#define HW_COMPAT_2_11 \ - {\ - .driver = "hpet",\ - .property = "hpet-offset-saved",\ - .value = "false",\ - },{\ - .driver = "virtio-blk-pci",\ - .property = "vectors",\ - .value = "2",\ - },{\ - .driver = "vhost-user-blk-pci",\ - .property = "vectors",\ - .value = "2",\ - },{\ - .driver = "e1000",\ - .property = "migrate_tso_props",\ - .value = "off",\ - }, - -#define HW_COMPAT_2_10 \ - {\ - .driver = "virtio-mouse-device",\ - .property = "wheel-axis",\ - .value = "false",\ - },{\ - .driver = "virtio-tablet-device",\ - .property = "wheel-axis",\ - .value = "false",\ - }, - -#define HW_COMPAT_2_9 \ - {\ - .driver = "pci-bridge",\ - .property = "shpc",\ - .value = "off",\ - },{\ - .driver = "intel-iommu",\ - .property = "pt",\ - .value = "off",\ - },{\ - .driver = "virtio-net-device",\ - .property = "x-mtu-bypass-backend",\ - .value = "off",\ - },{\ - .driver = "pcie-root-port",\ - .property = "x-migrate-msix",\ - .value = "false",\ - }, - -#define HW_COMPAT_2_8 \ - {\ - .driver = "fw_cfg_mem",\ - .property = "x-file-slots",\ - .value = stringify(0x10),\ - },{\ - .driver = "fw_cfg_io",\ - .property = "x-file-slots",\ - .value = stringify(0x10),\ - },{\ - .driver = "pflash_cfi01",\ - .property = "old-multiple-chip-handling",\ - .value = "on",\ - },{\ - .driver = "pci-bridge",\ - .property = "shpc",\ - .value = "on",\ - },{\ - .driver = TYPE_PCI_DEVICE,\ - .property = "x-pcie-extcap-init",\ - .value = "off",\ - },{\ - .driver = "virtio-pci",\ - .property = "x-pcie-deverr-init",\ - .value = "off",\ - },{\ - .driver = "virtio-pci",\ - .property = "x-pcie-lnkctl-init",\ - .value = "off",\ - },{\ - .driver = "virtio-pci",\ - .property = "x-pcie-pm-init",\ - .value = "off",\ - },{\ - .driver = "cirrus-vga",\ - .property = "vgamem_mb",\ - .value = "8",\ - },{\ - .driver = "isa-cirrus-vga",\ - .property = "vgamem_mb",\ - .value = "8",\ - }, - -#define HW_COMPAT_2_7 \ - {\ - .driver = "virtio-pci",\ - .property = "page-per-vq",\ - .value = "on",\ - },{\ - .driver = "virtio-serial-device",\ - .property = "emergency-write",\ - .value = "off",\ - },{\ - .driver = "ioapic",\ - .property = "version",\ - .value = "0x11",\ - },{\ - .driver = "intel-iommu",\ - .property = "x-buggy-eim",\ - .value = "true",\ - },{\ - .driver = "virtio-pci",\ - .property = "x-ignore-backend-features",\ - .value = "on",\ - }, - -#define HW_COMPAT_2_6 \ - {\ - .driver = "virtio-mmio",\ - .property = "format_transport_address",\ - .value = "off",\ - },{\ - .driver = "virtio-pci",\ - .property = "disable-modern",\ - .value = "on",\ - },{\ - .driver = "virtio-pci",\ - .property = "disable-legacy",\ - .value = "off",\ - }, - -#define HW_COMPAT_2_5 \ - {\ - .driver = "isa-fdc",\ - .property = "fallback",\ - .value = "144",\ - },{\ - .driver = "pvscsi",\ - .property = "x-old-pci-configuration",\ - .value = "on",\ - },{\ - .driver = "pvscsi",\ - .property = "x-disable-pcie",\ - .value = "on",\ - },\ - {\ - .driver = "vmxnet3",\ - .property = "x-old-msi-offsets",\ - .value = "on",\ - },{\ - .driver = "vmxnet3",\ - .property = "x-disable-pcie",\ - .value = "on",\ - }, - -#define HW_COMPAT_2_4 \ - {\ - .driver = "virtio-blk-device",\ - .property = "scsi",\ - .value = "true",\ - },{\ - .driver = "e1000",\ - .property = "extra_mac_registers",\ - .value = "off",\ - },{\ - .driver = "virtio-pci",\ - .property = "x-disable-pcie",\ - .value = "on",\ - },{\ - .driver = "virtio-pci",\ - .property = "migrate-extra",\ - .value = "off",\ - },{\ - .driver = "fw_cfg_mem",\ - .property = "dma_enabled",\ - .value = "off",\ - },{\ - .driver = "fw_cfg_io",\ - .property = "dma_enabled",\ - .value = "off",\ - }, - -#define HW_COMPAT_2_3 \ - {\ - .driver = "virtio-blk-pci",\ - .property = "any_layout",\ - .value = "off",\ - },{\ - .driver = "virtio-balloon-pci",\ - .property = "any_layout",\ - .value = "off",\ - },{\ - .driver = "virtio-serial-pci",\ - .property = "any_layout",\ - .value = "off",\ - },{\ - .driver = "virtio-9p-pci",\ - .property = "any_layout",\ - .value = "off",\ - },{\ - .driver = "virtio-rng-pci",\ - .property = "any_layout",\ - .value = "off",\ - },{\ - .driver = TYPE_PCI_DEVICE,\ - .property = "x-pcie-lnksta-dllla",\ - .value = "off",\ - },{\ - .driver = "migration",\ - .property = "send-configuration",\ - .value = "off",\ - },{\ - .driver = "migration",\ - .property = "send-section-footer",\ - .value = "off",\ - },{\ - .driver = "migration",\ - .property = "store-global-state",\ - .value = "off",\ - }, - -#define HW_COMPAT_2_2 \ - /* empty */ - -#define HW_COMPAT_2_1 \ - {\ - .driver = "intel-hda",\ - .property = "old_msi_addr",\ - .value = "on",\ - },{\ - .driver = "VGA",\ - .property = "qemu-extended-regs",\ - .value = "off",\ - },{\ - .driver = "secondary-vga",\ - .property = "qemu-extended-regs",\ - .value = "off",\ - },{\ - .driver = "virtio-scsi-pci",\ - .property = "any_layout",\ - .value = "off",\ - },{\ - .driver = "usb-mouse",\ - .property = "usb_version",\ - .value = stringify(1),\ - },{\ - .driver = "usb-kbd",\ - .property = "usb_version",\ - .value = stringify(1),\ - },{\ - .driver = "virtio-pci",\ - .property = "virtio-pci-bus-master-bug-migration",\ - .value = "on",\ - }, - -#endif /* HW_COMPAT_H */ diff --git a/include/hw/cpu/cluster.h b/include/hw/cpu/cluster.h new file mode 100644 index 0000000000..7381823243 --- /dev/null +++ b/include/hw/cpu/cluster.h @@ -0,0 +1,58 @@ +/* + * QEMU CPU cluster + * + * Copyright (c) 2018 GreenSocs SAS + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * <http://www.gnu.org/licenses/gpl-2.0.html> + */ +#ifndef HW_CPU_CLUSTER_H +#define HW_CPU_CLUSTER_H + +#include "qemu/osdep.h" +#include "hw/qdev.h" + +/* + * CPU Cluster type + * + * A cluster is a group of CPUs which are all identical and have the same view + * of the rest of the system. It is mainly an internal QEMU representation and + * does not necessarily match with the notion of clusters on the real hardware. + * + * If CPUs are not identical (for example, Cortex-A53 and Cortex-A57 CPUs in an + * Arm big.LITTLE system) they should be in different clusters. If the CPUs do + * not have the same view of memory (for example the main CPU and a management + * controller processor) they should be in different clusters. + */ + +#define TYPE_CPU_CLUSTER "cpu-cluster" +#define CPU_CLUSTER(obj) \ + OBJECT_CHECK(CPUClusterState, (obj), TYPE_CPU_CLUSTER) + +/** + * CPUClusterState: + * @cluster_id: The cluster ID. This value is for internal use only and should + * not be exposed directly to the user or to the guest. + * + * State of a CPU cluster. + */ +typedef struct CPUClusterState { + /*< private >*/ + DeviceState parent_obj; + + /*< public >*/ + uint32_t cluster_id; +} CPUClusterState; + +#endif diff --git a/include/hw/gpio/nrf51_gpio.h b/include/hw/gpio/nrf51_gpio.h new file mode 100644 index 0000000000..337ee534bb --- /dev/null +++ b/include/hw/gpio/nrf51_gpio.h @@ -0,0 +1,69 @@ +/* + * nRF51 System-on-Chip general purpose input/output register definition + * + * QEMU interface: + * + sysbus MMIO regions 0: GPIO registers + * + Unnamed GPIO inputs 0-31: Set tri-state input level for GPIO pin. + * Level -1: Externally Disconnected/Floating; Pull-up/down will be regarded + * Level 0: Input externally driven LOW + * Level 1: Input externally driven HIGH + * + Unnamed GPIO outputs 0-31: + * Level -1: Disconnected/Floating + * Level 0: Driven LOW + * Level 1: Driven HIGH + * + * Accuracy of the peripheral model: + * + The nRF51 GPIO output driver supports two modes, standard and high-current + * mode. These different drive modes are not modeled and handled the same. + * + Pin SENSEing is not modeled/implemented. + * + * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de> + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + * + */ +#ifndef NRF51_GPIO_H +#define NRF51_GPIO_H + +#include "hw/sysbus.h" +#define TYPE_NRF51_GPIO "nrf51_soc.gpio" +#define NRF51_GPIO(obj) OBJECT_CHECK(NRF51GPIOState, (obj), TYPE_NRF51_GPIO) + +#define NRF51_GPIO_PINS 32 + +#define NRF51_GPIO_SIZE 0x1000 + +#define NRF51_GPIO_REG_OUT 0x504 +#define NRF51_GPIO_REG_OUTSET 0x508 +#define NRF51_GPIO_REG_OUTCLR 0x50C +#define NRF51_GPIO_REG_IN 0x510 +#define NRF51_GPIO_REG_DIR 0x514 +#define NRF51_GPIO_REG_DIRSET 0x518 +#define NRF51_GPIO_REG_DIRCLR 0x51C +#define NRF51_GPIO_REG_CNF_START 0x700 +#define NRF51_GPIO_REG_CNF_END 0x77F + +#define NRF51_GPIO_PULLDOWN 1 +#define NRF51_GPIO_PULLUP 3 + +typedef struct NRF51GPIOState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + qemu_irq irq; + + uint32_t out; + uint32_t in; + uint32_t in_mask; + uint32_t dir; + uint32_t cnf[NRF51_GPIO_PINS]; + + uint32_t old_out; + uint32_t old_out_connected; + + qemu_irq output[NRF51_GPIO_PINS]; +} NRF51GPIOState; + + +#endif diff --git a/include/hw/i386/ioapic.h b/include/hw/i386/ioapic.h index 9c8816f11f..59fcb158a7 100644 --- a/include/hw/i386/ioapic.h +++ b/include/hw/i386/ioapic.h @@ -23,6 +23,9 @@ #define IOAPIC_NUM_PINS 24 #define IO_APIC_DEFAULT_ADDRESS 0xfec00000 +#define TYPE_KVM_IOAPIC "kvm-ioapic" +#define TYPE_IOAPIC "ioapic" + void ioapic_eoi_broadcast(int vector); #endif /* HW_IOAPIC_H */ diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index c7c0c944e8..84720bede9 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -13,7 +13,6 @@ #include "qemu/bitmap.h" #include "sysemu/sysemu.h" #include "hw/pci/pci.h" -#include "hw/compat.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" #include "hw/acpi/acpi_dev_interface.h" @@ -294,171 +293,62 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t); int e820_get_num_entries(void); bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); -#define PC_COMPAT_3_1 \ - HW_COMPAT_3_1 \ - {\ - .driver = "intel-iommu",\ - .property = "dma-drain",\ - .value = "off",\ - }, +extern GlobalProperty pc_compat_3_1[]; +extern const size_t pc_compat_3_1_len; -#define PC_COMPAT_3_0 \ - HW_COMPAT_3_0 \ - {\ - .driver = TYPE_X86_CPU,\ - .property = "x-hv-synic-kvm-only",\ - .value = "on",\ - },{\ - .driver = "Skylake-Server" "-" TYPE_X86_CPU,\ - .property = "pku",\ - .value = "off",\ - },{\ - .driver = "Skylake-Server-IBRS" "-" TYPE_X86_CPU,\ - .property = "pku",\ - .value = "off",\ - }, +extern GlobalProperty pc_compat_3_0[]; +extern const size_t pc_compat_3_0_len; -#define PC_COMPAT_2_12 \ - HW_COMPAT_2_12 \ - {\ - .driver = TYPE_X86_CPU,\ - .property = "legacy-cache",\ - .value = "on",\ - },{\ - .driver = TYPE_X86_CPU,\ - .property = "topoext",\ - .value = "off",\ - },{\ - .driver = "EPYC-" TYPE_X86_CPU,\ - .property = "xlevel",\ - .value = stringify(0x8000000a),\ - },{\ - .driver = "EPYC-IBPB-" TYPE_X86_CPU,\ - .property = "xlevel",\ - .value = stringify(0x8000000a),\ - }, +extern GlobalProperty pc_compat_2_12[]; +extern const size_t pc_compat_2_12_len; -#define PC_COMPAT_2_11 \ - HW_COMPAT_2_11 \ - {\ - .driver = TYPE_X86_CPU,\ - .property = "x-migrate-smi-count",\ - .value = "off",\ - },{\ - .driver = "Skylake-Server" "-" TYPE_X86_CPU,\ - .property = "clflushopt",\ - .value = "off",\ - }, +extern GlobalProperty pc_compat_2_11[]; +extern const size_t pc_compat_2_11_len; -#define PC_COMPAT_2_10 \ - HW_COMPAT_2_10 \ - {\ - .driver = TYPE_X86_CPU,\ - .property = "x-hv-max-vps",\ - .value = "0x40",\ - },{\ - .driver = "i440FX-pcihost",\ - .property = "x-pci-hole64-fix",\ - .value = "off",\ - },{\ - .driver = "q35-pcihost",\ - .property = "x-pci-hole64-fix",\ - .value = "off",\ - }, +extern GlobalProperty pc_compat_2_10[]; +extern const size_t pc_compat_2_10_len; -#define PC_COMPAT_2_9 \ - HW_COMPAT_2_9 \ - {\ - .driver = "mch",\ - .property = "extended-tseg-mbytes",\ - .value = stringify(0),\ - },\ +extern GlobalProperty pc_compat_2_9[]; +extern const size_t pc_compat_2_9_len; -#define PC_COMPAT_2_8 \ - HW_COMPAT_2_8 \ - {\ - .driver = TYPE_X86_CPU,\ - .property = "tcg-cpuid",\ - .value = "off",\ - },\ - {\ - .driver = "kvmclock",\ - .property = "x-mach-use-reliable-get-clock",\ - .value = "off",\ - },\ - {\ - .driver = "ICH9-LPC",\ - .property = "x-smi-broadcast",\ - .value = "off",\ - },\ - {\ - .driver = TYPE_X86_CPU,\ - .property = "vmware-cpuid-freq",\ - .value = "off",\ - },\ - {\ - .driver = "Haswell-" TYPE_X86_CPU,\ - .property = "stepping",\ - .value = "1",\ - }, +extern GlobalProperty pc_compat_2_8[]; +extern const size_t pc_compat_2_8_len; -#define PC_COMPAT_2_7 \ - HW_COMPAT_2_7 \ - {\ - .driver = TYPE_X86_CPU,\ - .property = "l3-cache",\ - .value = "off",\ - },\ - {\ - .driver = TYPE_X86_CPU,\ - .property = "full-cpuid-auto-level",\ - .value = "off",\ - },\ - {\ - .driver = "Opteron_G3" "-" TYPE_X86_CPU,\ - .property = "family",\ - .value = "15",\ - },\ - {\ - .driver = "Opteron_G3" "-" TYPE_X86_CPU,\ - .property = "model",\ - .value = "6",\ - },\ - {\ - .driver = "Opteron_G3" "-" TYPE_X86_CPU,\ - .property = "stepping",\ - .value = "1",\ - },\ - {\ - .driver = "isa-pcspk",\ - .property = "migrate",\ - .value = "off",\ - }, +extern GlobalProperty pc_compat_2_7[]; +extern const size_t pc_compat_2_7_len; -#define PC_COMPAT_2_6 \ - HW_COMPAT_2_6 \ - {\ - .driver = TYPE_X86_CPU,\ - .property = "cpuid-0xb",\ - .value = "off",\ - },{\ - .driver = "vmxnet3",\ - .property = "romfile",\ - .value = "",\ - },\ - {\ - .driver = TYPE_X86_CPU,\ - .property = "fill-mtrr-mask",\ - .value = "off",\ - },\ - {\ - .driver = "apic-common",\ - .property = "legacy-instance-id",\ - .value = "on",\ - }, +extern GlobalProperty pc_compat_2_6[]; +extern const size_t pc_compat_2_6_len; -#define PC_COMPAT_2_5 \ - HW_COMPAT_2_5 +extern GlobalProperty pc_compat_2_5[]; +extern const size_t pc_compat_2_5_len; + +extern GlobalProperty pc_compat_2_4[]; +extern const size_t pc_compat_2_4_len; + +extern GlobalProperty pc_compat_2_3[]; +extern const size_t pc_compat_2_3_len; + +extern GlobalProperty pc_compat_2_2[]; +extern const size_t pc_compat_2_2_len; + +extern GlobalProperty pc_compat_2_1[]; +extern const size_t pc_compat_2_1_len; + +extern GlobalProperty pc_compat_2_0[]; +extern const size_t pc_compat_2_0_len; + +extern GlobalProperty pc_compat_1_7[]; +extern const size_t pc_compat_1_7_len; + +extern GlobalProperty pc_compat_1_6[]; +extern const size_t pc_compat_1_6_len; + +extern GlobalProperty pc_compat_1_5[]; +extern const size_t pc_compat_1_5_len; + +extern GlobalProperty pc_compat_1_4[]; +extern const size_t pc_compat_1_4_len; /* Helper for setting model-id for CPU models that changed model-id * depending on QEMU versions up to QEMU 2.4. @@ -480,491 +370,6 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); .value = "QEMU Virtual CPU version " v,\ }, -#define PC_COMPAT_2_4 \ - HW_COMPAT_2_4 \ - PC_CPU_MODEL_IDS("2.4.0") \ - {\ - .driver = "Haswell-" TYPE_X86_CPU,\ - .property = "abm",\ - .value = "off",\ - },\ - {\ - .driver = "Haswell-noTSX-" TYPE_X86_CPU,\ - .property = "abm",\ - .value = "off",\ - },\ - {\ - .driver = "Broadwell-" TYPE_X86_CPU,\ - .property = "abm",\ - .value = "off",\ - },\ - {\ - .driver = "Broadwell-noTSX-" TYPE_X86_CPU,\ - .property = "abm",\ - .value = "off",\ - },\ - {\ - .driver = "host" "-" TYPE_X86_CPU,\ - .property = "host-cache-info",\ - .value = "on",\ - },\ - {\ - .driver = TYPE_X86_CPU,\ - .property = "check",\ - .value = "off",\ - },\ - {\ - .driver = "qemu64" "-" TYPE_X86_CPU,\ - .property = "sse4a",\ - .value = "on",\ - },\ - {\ - .driver = "qemu64" "-" TYPE_X86_CPU,\ - .property = "abm",\ - .value = "on",\ - },\ - {\ - .driver = "qemu64" "-" TYPE_X86_CPU,\ - .property = "popcnt",\ - .value = "on",\ - },\ - {\ - .driver = "qemu32" "-" TYPE_X86_CPU,\ - .property = "popcnt",\ - .value = "on",\ - },{\ - .driver = "Opteron_G2" "-" TYPE_X86_CPU,\ - .property = "rdtscp",\ - .value = "on",\ - },{\ - .driver = "Opteron_G3" "-" TYPE_X86_CPU,\ - .property = "rdtscp",\ - .value = "on",\ - },{\ - .driver = "Opteron_G4" "-" TYPE_X86_CPU,\ - .property = "rdtscp",\ - .value = "on",\ - },{\ - .driver = "Opteron_G5" "-" TYPE_X86_CPU,\ - .property = "rdtscp",\ - .value = "on",\ - }, - - -#define PC_COMPAT_2_3 \ - HW_COMPAT_2_3 \ - PC_CPU_MODEL_IDS("2.3.0") \ - {\ - .driver = TYPE_X86_CPU,\ - .property = "arat",\ - .value = "off",\ - },{\ - .driver = "qemu64" "-" TYPE_X86_CPU,\ - .property = "min-level",\ - .value = stringify(4),\ - },{\ - .driver = "kvm64" "-" TYPE_X86_CPU,\ - .property = "min-level",\ - .value = stringify(5),\ - },{\ - .driver = "pentium3" "-" TYPE_X86_CPU,\ - .property = "min-level",\ - .value = stringify(2),\ - },{\ - .driver = "n270" "-" TYPE_X86_CPU,\ - .property = "min-level",\ - .value = stringify(5),\ - },{\ - .driver = "Conroe" "-" TYPE_X86_CPU,\ - .property = "min-level",\ - .value = stringify(4),\ - },{\ - .driver = "Penryn" "-" TYPE_X86_CPU,\ - .property = "min-level",\ - .value = stringify(4),\ - },{\ - .driver = "Nehalem" "-" TYPE_X86_CPU,\ - .property = "min-level",\ - .value = stringify(4),\ - },{\ - .driver = "n270" "-" TYPE_X86_CPU,\ - .property = "min-xlevel",\ - .value = stringify(0x8000000a),\ - },{\ - .driver = "Penryn" "-" TYPE_X86_CPU,\ - .property = "min-xlevel",\ - .value = stringify(0x8000000a),\ - },{\ - .driver = "Conroe" "-" TYPE_X86_CPU,\ - .property = "min-xlevel",\ - .value = stringify(0x8000000a),\ - },{\ - .driver = "Nehalem" "-" TYPE_X86_CPU,\ - .property = "min-xlevel",\ - .value = stringify(0x8000000a),\ - },{\ - .driver = "Westmere" "-" TYPE_X86_CPU,\ - .property = "min-xlevel",\ - .value = stringify(0x8000000a),\ - },{\ - .driver = "SandyBridge" "-" TYPE_X86_CPU,\ - .property = "min-xlevel",\ - .value = stringify(0x8000000a),\ - },{\ - .driver = "IvyBridge" "-" TYPE_X86_CPU,\ - .property = "min-xlevel",\ - .value = stringify(0x8000000a),\ - },{\ - .driver = "Haswell" "-" TYPE_X86_CPU,\ - .property = "min-xlevel",\ - .value = stringify(0x8000000a),\ - },{\ - .driver = "Haswell-noTSX" "-" TYPE_X86_CPU,\ - .property = "min-xlevel",\ - .value = stringify(0x8000000a),\ - },{\ - .driver = "Broadwell" "-" TYPE_X86_CPU,\ - .property = "min-xlevel",\ - .value = stringify(0x8000000a),\ - },{\ - .driver = "Broadwell-noTSX" "-" TYPE_X86_CPU,\ - .property = "min-xlevel",\ - .value = stringify(0x8000000a),\ - },{\ - .driver = TYPE_X86_CPU,\ - .property = "kvm-no-smi-migration",\ - .value = "on",\ - }, - -#define PC_COMPAT_2_2 \ - HW_COMPAT_2_2 \ - PC_CPU_MODEL_IDS("2.2.0") \ - {\ - .driver = "kvm64" "-" TYPE_X86_CPU,\ - .property = "vme",\ - .value = "off",\ - },\ - {\ - .driver = "kvm32" "-" TYPE_X86_CPU,\ - .property = "vme",\ - .value = "off",\ - },\ - {\ - .driver = "Conroe" "-" TYPE_X86_CPU,\ - .property = "vme",\ - .value = "off",\ - },\ - {\ - .driver = "Penryn" "-" TYPE_X86_CPU,\ - .property = "vme",\ - .value = "off",\ - },\ - {\ - .driver = "Nehalem" "-" TYPE_X86_CPU,\ - .property = "vme",\ - .value = "off",\ - },\ - {\ - .driver = "Westmere" "-" TYPE_X86_CPU,\ - .property = "vme",\ - .value = "off",\ - },\ - {\ - .driver = "SandyBridge" "-" TYPE_X86_CPU,\ - .property = "vme",\ - .value = "off",\ - },\ - {\ - .driver = "Haswell" "-" TYPE_X86_CPU,\ - .property = "vme",\ - .value = "off",\ - },\ - {\ - .driver = "Broadwell" "-" TYPE_X86_CPU,\ - .property = "vme",\ - .value = "off",\ - },\ - {\ - .driver = "Opteron_G1" "-" TYPE_X86_CPU,\ - .property = "vme",\ - .value = "off",\ - },\ - {\ - .driver = "Opteron_G2" "-" TYPE_X86_CPU,\ - .property = "vme",\ - .value = "off",\ - },\ - {\ - .driver = "Opteron_G3" "-" TYPE_X86_CPU,\ - .property = "vme",\ - .value = "off",\ - },\ - {\ - .driver = "Opteron_G4" "-" TYPE_X86_CPU,\ - .property = "vme",\ - .value = "off",\ - },\ - {\ - .driver = "Opteron_G5" "-" TYPE_X86_CPU,\ - .property = "vme",\ - .value = "off",\ - },\ - {\ - .driver = "Haswell" "-" TYPE_X86_CPU,\ - .property = "f16c",\ - .value = "off",\ - },\ - {\ - .driver = "Haswell" "-" TYPE_X86_CPU,\ - .property = "rdrand",\ - .value = "off",\ - },\ - {\ - .driver = "Broadwell" "-" TYPE_X86_CPU,\ - .property = "f16c",\ - .value = "off",\ - },\ - {\ - .driver = "Broadwell" "-" TYPE_X86_CPU,\ - .property = "rdrand",\ - .value = "off",\ - }, - -#define PC_COMPAT_2_1 \ - HW_COMPAT_2_1 \ - PC_CPU_MODEL_IDS("2.1.0") \ - {\ - .driver = "coreduo" "-" TYPE_X86_CPU,\ - .property = "vmx",\ - .value = "on",\ - },\ - {\ - .driver = "core2duo" "-" TYPE_X86_CPU,\ - .property = "vmx",\ - .value = "on",\ - }, - -#define PC_COMPAT_2_0 \ - PC_CPU_MODEL_IDS("2.0.0") \ - {\ - .driver = "virtio-scsi-pci",\ - .property = "any_layout",\ - .value = "off",\ - },{\ - .driver = "PIIX4_PM",\ - .property = "memory-hotplug-support",\ - .value = "off",\ - },\ - {\ - .driver = "apic",\ - .property = "version",\ - .value = stringify(0x11),\ - },\ - {\ - .driver = "nec-usb-xhci",\ - .property = "superspeed-ports-first",\ - .value = "off",\ - },\ - {\ - .driver = "nec-usb-xhci",\ - .property = "force-pcie-endcap",\ - .value = "on",\ - },\ - {\ - .driver = "pci-serial",\ - .property = "prog_if",\ - .value = stringify(0),\ - },\ - {\ - .driver = "pci-serial-2x",\ - .property = "prog_if",\ - .value = stringify(0),\ - },\ - {\ - .driver = "pci-serial-4x",\ - .property = "prog_if",\ - .value = stringify(0),\ - },\ - {\ - .driver = "virtio-net-pci",\ - .property = "guest_announce",\ - .value = "off",\ - },\ - {\ - .driver = "ICH9-LPC",\ - .property = "memory-hotplug-support",\ - .value = "off",\ - },{\ - .driver = "xio3130-downstream",\ - .property = COMPAT_PROP_PCP,\ - .value = "off",\ - },{\ - .driver = "ioh3420",\ - .property = COMPAT_PROP_PCP,\ - .value = "off",\ - }, - -#define PC_COMPAT_1_7 \ - PC_CPU_MODEL_IDS("1.7.0") \ - {\ - .driver = TYPE_USB_DEVICE,\ - .property = "msos-desc",\ - .value = "no",\ - },\ - {\ - .driver = "PIIX4_PM",\ - .property = "acpi-pci-hotplug-with-bridge-support",\ - .value = "off",\ - },\ - {\ - .driver = "hpet",\ - .property = HPET_INTCAP,\ - .value = stringify(4),\ - }, - -#define PC_COMPAT_1_6 \ - PC_CPU_MODEL_IDS("1.6.0") \ - {\ - .driver = "e1000",\ - .property = "mitigation",\ - .value = "off",\ - },{\ - .driver = "qemu64-" TYPE_X86_CPU,\ - .property = "model",\ - .value = stringify(2),\ - },{\ - .driver = "qemu32-" TYPE_X86_CPU,\ - .property = "model",\ - .value = stringify(3),\ - },{\ - .driver = "i440FX-pcihost",\ - .property = "short_root_bus",\ - .value = stringify(1),\ - },{\ - .driver = "q35-pcihost",\ - .property = "short_root_bus",\ - .value = stringify(1),\ - }, - -#define PC_COMPAT_1_5 \ - PC_CPU_MODEL_IDS("1.5.0") \ - {\ - .driver = "Conroe-" TYPE_X86_CPU,\ - .property = "model",\ - .value = stringify(2),\ - },{\ - .driver = "Conroe-" TYPE_X86_CPU,\ - .property = "min-level",\ - .value = stringify(2),\ - },{\ - .driver = "Penryn-" TYPE_X86_CPU,\ - .property = "model",\ - .value = stringify(2),\ - },{\ - .driver = "Penryn-" TYPE_X86_CPU,\ - .property = "min-level",\ - .value = stringify(2),\ - },{\ - .driver = "Nehalem-" TYPE_X86_CPU,\ - .property = "model",\ - .value = stringify(2),\ - },{\ - .driver = "Nehalem-" TYPE_X86_CPU,\ - .property = "min-level",\ - .value = stringify(2),\ - },{\ - .driver = "virtio-net-pci",\ - .property = "any_layout",\ - .value = "off",\ - },{\ - .driver = TYPE_X86_CPU,\ - .property = "pmu",\ - .value = "on",\ - },{\ - .driver = "i440FX-pcihost",\ - .property = "short_root_bus",\ - .value = stringify(0),\ - },{\ - .driver = "q35-pcihost",\ - .property = "short_root_bus",\ - .value = stringify(0),\ - }, - -#define PC_COMPAT_1_4 \ - PC_CPU_MODEL_IDS("1.4.0") \ - {\ - .driver = "scsi-hd",\ - .property = "discard_granularity",\ - .value = stringify(0),\ - },{\ - .driver = "scsi-cd",\ - .property = "discard_granularity",\ - .value = stringify(0),\ - },{\ - .driver = "scsi-disk",\ - .property = "discard_granularity",\ - .value = stringify(0),\ - },{\ - .driver = "ide-hd",\ - .property = "discard_granularity",\ - .value = stringify(0),\ - },{\ - .driver = "ide-cd",\ - .property = "discard_granularity",\ - .value = stringify(0),\ - },{\ - .driver = "ide-drive",\ - .property = "discard_granularity",\ - .value = stringify(0),\ - },{\ - .driver = "virtio-blk-pci",\ - .property = "discard_granularity",\ - .value = stringify(0),\ - },{\ - .driver = "virtio-serial-pci",\ - .property = "vectors",\ - /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\ - .value = stringify(0xFFFFFFFF),\ - },{ \ - .driver = "virtio-net-pci", \ - .property = "ctrl_guest_offloads", \ - .value = "off", \ - },{\ - .driver = "e1000",\ - .property = "romfile",\ - .value = "pxe-e1000.rom",\ - },{\ - .driver = "ne2k_pci",\ - .property = "romfile",\ - .value = "pxe-ne2k_pci.rom",\ - },{\ - .driver = "pcnet",\ - .property = "romfile",\ - .value = "pxe-pcnet.rom",\ - },{\ - .driver = "rtl8139",\ - .property = "romfile",\ - .value = "pxe-rtl8139.rom",\ - },{\ - .driver = "virtio-net-pci",\ - .property = "romfile",\ - .value = "pxe-virtio.rom",\ - },{\ - .driver = "486-" TYPE_X86_CPU,\ - .property = "model",\ - .value = stringify(0),\ - },\ - {\ - .driver = "n270" "-" TYPE_X86_CPU,\ - .property = "movbe",\ - .value = "off",\ - },\ - {\ - .driver = "Westmere" "-" TYPE_X86_CPU,\ - .property = "pclmulqdq",\ - .value = "off",\ - }, - #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \ { \ diff --git a/include/hw/loader.h b/include/hw/loader.h index 0a0ad808ea..de8a29603b 100644 --- a/include/hw/loader.h +++ b/include/hw/loader.h @@ -175,10 +175,15 @@ void load_elf_hdr(const char *filename, void *hdr, bool *is64, Error **errp); int load_aout(const char *filename, hwaddr addr, int max_sz, int bswap_needed, hwaddr target_page_size); +#define LOAD_UIMAGE_LOADADDR_INVALID (-1) + /** load_uimage_as: * @filename: Path of uimage file * @ep: Populated with program entry point. Ignored if NULL. - * @loadaddr: Populated with the load address. Ignored if NULL. + * @loadaddr: load address if none specified in the image or when loading a + * ramdisk. Populated with the load address. Ignored if NULL or + * LOAD_UIMAGE_LOADADDR_INVALID (images which do not specify a load + * address will not be loadable). * @is_linux: Is set to true if the image loaded is Linux. Ignored if NULL. * @translate_fn: optional function to translate load addresses * @translate_opaque: opaque data passed to @translate_fn diff --git a/include/hw/misc/nrf51_rng.h b/include/hw/misc/nrf51_rng.h new file mode 100644 index 0000000000..3d6bf79997 --- /dev/null +++ b/include/hw/misc/nrf51_rng.h @@ -0,0 +1,83 @@ +/* + * nRF51 Random Number Generator + * + * QEMU interface: + * + Property "period_unfiltered_us": Time between two biased values in + * microseconds. + * + Property "period_filtered_us": Time between two unbiased values in + * microseconds. + * + sysbus MMIO regions 0: Memory Region with tasks, events and registers + * to be mapped to the peripherals instance address by the SOC. + * + Named GPIO output "irq": Interrupt line of the peripheral. Must be + * connected to the associated peripheral interrupt line of the NVIC. + * + Named GPIO output "eep_valrdy": Event set when new random value is ready + * to be read. + * + Named GPIO input "tep_start": Task that triggers start of continuous + * generation of random values. + * + Named GPIO input "tep_stop": Task that ends continuous generation of + * random values. + * + * Accuracy of the peripheral model: + * + Stochastic properties of different configurations of the random source + * are not modeled. + * + Generation of unfiltered and filtered random values take at least the + * average generation time stated in the production specification; + * non-deterministic generation times are not modeled. + * + * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de> + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + * + */ +#ifndef NRF51_RNG_H +#define NRF51_RNG_H + +#include "hw/sysbus.h" +#include "qemu/timer.h" +#define TYPE_NRF51_RNG "nrf51_soc.rng" +#define NRF51_RNG(obj) OBJECT_CHECK(NRF51RNGState, (obj), TYPE_NRF51_RNG) + +#define NRF51_RNG_SIZE 0x1000 + +#define NRF51_RNG_TASK_START 0x000 +#define NRF51_RNG_TASK_STOP 0x004 +#define NRF51_RNG_EVENT_VALRDY 0x100 +#define NRF51_RNG_REG_SHORTS 0x200 +#define NRF51_RNG_REG_SHORTS_VALRDY_STOP 0 +#define NRF51_RNG_REG_INTEN 0x300 +#define NRF51_RNG_REG_INTEN_VALRDY 0 +#define NRF51_RNG_REG_INTENSET 0x304 +#define NRF51_RNG_REG_INTENCLR 0x308 +#define NRF51_RNG_REG_CONFIG 0x504 +#define NRF51_RNG_REG_CONFIG_DECEN 0 +#define NRF51_RNG_REG_VALUE 0x508 + +typedef struct { + SysBusDevice parent_obj; + + MemoryRegion mmio; + qemu_irq irq; + + /* Event End Points */ + qemu_irq eep_valrdy; + + QEMUTimer timer; + + /* Time between generation of successive unfiltered values in us */ + uint16_t period_unfiltered_us; + /* Time between generation of successive filtered values in us */ + uint16_t period_filtered_us; + + uint8_t value; + + uint32_t active; + uint32_t event_valrdy; + uint32_t shortcut_stop_on_valrdy; + uint32_t interrupt_enabled; + uint32_t filter_enabled; + +} NRF51RNGState; + + +#endif /* NRF51_RNG_H_ */ diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index 7c66c3872f..4eb3a2ce3e 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -94,11 +94,13 @@ struct sPAPRPHBState { ((1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET) #define SPAPR_PCI_MEM64_WIN_SIZE 0x10000000000ULL /* 1 TiB */ -/* Without manual configuration, all PCI outbound windows will be - * within this range */ +/* All PCI outbound windows will be within this range */ #define SPAPR_PCI_BASE (1ULL << 45) /* 32 TiB */ #define SPAPR_PCI_LIMIT (1ULL << 46) /* 64 TiB */ +#define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ + SPAPR_PCI_MEM64_WIN_SIZE - 1) + #define SPAPR_PCI_2_7_MMIO_WIN_SIZE 0xf80000000 #define SPAPR_PCI_IO_WIN_SIZE 0x10000 @@ -111,8 +113,6 @@ static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin) return spapr_qirq(spapr, phb->lsi_table[pin].irq); } -PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index); - int spapr_populate_pci_dt(sPAPRPHBState *phb, uint32_t xics_phandle, void *fdt, uint32_t nr_msis); diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index eb12fa112e..d87f5f93e9 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -405,8 +405,10 @@ PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, MemoryRegion *address_space_mem, MemoryRegion *address_space_io, uint8_t devfn_min, const char *typename); +void pci_root_bus_cleanup(PCIBus *bus); void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, void *irq_opaque, int nirq); +void pci_bus_irqs_cleanup(PCIBus *bus); int pci_bus_get_irq_level(PCIBus *bus, int irq_num); /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); @@ -417,6 +419,7 @@ PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, MemoryRegion *address_space_io, uint8_t devfn_min, int nirq, const char *typename); +void pci_unregister_root_bus(PCIBus *bus); void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn); PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin); bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 86d5f54e54..6b65397b7e 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -98,7 +98,7 @@ typedef struct PnvChipClass { DeviceRealize parent_realize; uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); - Object *(*intc_create)(PnvChip *chip, Object *child, Error **errp); + void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); ISABus *(*isa_create)(PnvChip *chip, Error **errp); } PnvChipClass; diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h index f6af5eae1f..64ac73512e 100644 --- a/include/hw/ppc/pnv_psi.h +++ b/include/hw/ppc/pnv_psi.h @@ -40,6 +40,7 @@ typedef struct PnvPsi { /* Interrupt generation */ ICSState ics; + qemu_irq *qirqs; /* Registers */ uint64_t regs[PSIHB_XSCOM_MAX]; diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 2c77a8ba88..9e01a5a12e 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -103,6 +103,7 @@ struct sPAPRMachineClass { /*< public >*/ bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ + bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ bool pre_2_10_has_unused_icps; bool legacy_irq_allocation; @@ -139,6 +140,9 @@ struct sPAPRMachineState { int vrma_adjust; ssize_t rtas_size; void *rtas_blob; + uint32_t fdt_size; + uint32_t fdt_initial_size; + void *fdt_blob; long kernel_size; bool kernel_le; uint32_t initrd_base; @@ -178,6 +182,7 @@ struct sPAPRMachineState { unsigned long *irq_map; sPAPRXive *xive; sPAPRIrq *irq; + qemu_irq *qirqs; bool cmd_line_caps[SPAPR_CAP_NUM]; sPAPRCapabilities def, eff, mig; @@ -444,6 +449,7 @@ struct sPAPRMachineState { #define H_GET_EM_PARMS 0x2B8 #define H_SET_MPP 0x2D0 #define H_GET_MPP 0x2D4 +#define H_HOME_NODE_ASSOCIATIVITY 0x2EC #define H_XIRR_X 0x2FC #define H_RANDOM 0x300 #define H_SET_MODE 0x31C @@ -480,7 +486,8 @@ struct sPAPRMachineState { #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) /* Client Architecture support */ #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) -#define KVMPPC_HCALL_MAX KVMPPC_H_CAS +#define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) +#define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT typedef struct sPAPRDeviceTreeUpdateHeader { uint32_t version_id; diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index b34d5a0038..14b02c3aca 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -42,15 +42,17 @@ typedef struct sPAPRIrq { void (*print_info)(sPAPRMachineState *spapr, Monitor *mon); void (*dt_populate)(sPAPRMachineState *spapr, uint32_t nr_servers, void *fdt, uint32_t phandle); - Object *(*cpu_intc_create)(sPAPRMachineState *spapr, Object *cpu, - Error **errp); + void (*cpu_intc_create)(sPAPRMachineState *spapr, PowerPCCPU *cpu, + Error **errp); int (*post_load)(sPAPRMachineState *spapr, int version_id); void (*reset)(sPAPRMachineState *spapr, Error **errp); + void (*set_irq)(void *opaque, int srcno, int val); } sPAPRIrq; extern sPAPRIrq spapr_irq_xics; extern sPAPRIrq spapr_irq_xics_legacy; extern sPAPRIrq spapr_irq_xive; +extern sPAPRIrq spapr_irq_dual; void spapr_irq_init(sPAPRMachineState *spapr, Error **errp); int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp); diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h index 728735dbcf..7fdc250574 100644 --- a/include/hw/ppc/spapr_xive.h +++ b/include/hw/ppc/spapr_xive.h @@ -40,7 +40,6 @@ typedef struct sPAPRXive { bool spapr_xive_irq_claim(sPAPRXive *xive, uint32_t lisn, bool lsi); bool spapr_xive_irq_free(sPAPRXive *xive, uint32_t lisn); void spapr_xive_pic_print_info(sPAPRXive *xive, Monitor *mon); -qemu_irq spapr_xive_qirq(sPAPRXive *xive, uint32_t lisn); typedef struct sPAPRMachineState sPAPRMachineState; @@ -48,5 +47,6 @@ void spapr_xive_hcall_init(sPAPRMachineState *spapr); void spapr_dt_xive(sPAPRMachineState *spapr, uint32_t nr_servers, void *fdt, uint32_t phandle); void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx); +void spapr_xive_mmio_set_enabled(sPAPRXive *xive, bool enable); #endif /* PPC_SPAPR_XIVE_H */ diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 14afda198c..07508cbd21 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -131,7 +131,6 @@ struct ICSState { /*< public >*/ uint32_t nr_irqs; uint32_t offset; - qemu_irq *qirqs; ICSIRQState *irqs; XICSFabric *xics; }; @@ -140,8 +139,7 @@ struct ICSState { static inline bool ics_valid_irq(ICSState *ics, uint32_t nr) { - return (ics->offset != 0) && (nr >= ics->offset) - && (nr < (ics->offset + ics->nr_irqs)); + return (nr >= ics->offset) && (nr < (ics->offset + ics->nr_irqs)); } struct ICSIRQState { @@ -192,6 +190,8 @@ void icp_eoi(ICPState *icp, uint32_t xirr); void ics_simple_write_xive(ICSState *ics, int nr, int server, uint8_t priority, uint8_t saved_priority); +void ics_simple_set_irq(void *opaque, int srcno, int val); +void ics_kvm_set_irq(void *opaque, int srcno, int val); void ics_set_irq_type(ICSState *ics, int srcno, bool lsi); void icp_pic_print_info(ICPState *icp, Monitor *mon); diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 18cd114eb2..ec23253ba4 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -184,7 +184,6 @@ typedef struct XiveSource { /* IRQs */ uint32_t nr_irqs; - qemu_irq *qirqs; unsigned long *lsi_map; /* PQ bits and LSI assertion bit */ @@ -278,12 +277,6 @@ uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq); void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset, Monitor *mon); -static inline qemu_irq xive_source_qirq(XiveSource *xsrc, uint32_t srcno) -{ - assert(srcno < xsrc->nr_irqs); - return xsrc->qirqs[srcno]; -} - static inline bool xive_source_irq_is_lsi(XiveSource *xsrc, uint32_t srcno) { assert(srcno < xsrc->nr_irqs); @@ -299,6 +292,8 @@ static inline void xive_source_irq_set(XiveSource *xsrc, uint32_t srcno, } } +void xive_source_set_irq(void *opaque, int srcno, int val); + /* * XIVE Router */ diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 92851e55df..bc014c1c9f 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -249,24 +249,27 @@ struct PropertyInfo { /** * GlobalProperty: - * @user_provided: Set to true if property comes from user-provided config - * (command-line or config file). * @used: Set to true if property was used when initializing a device. - * @errp: Error destination, used like first argument of error_setg() - * in case property setting fails later. If @errp is NULL, we - * print warnings instead of ignoring errors silently. For - * hotplugged devices, errp is always ignored and warnings are - * printed instead. + * + * An error is fatal for non-hotplugged devices, when the global is applied. */ typedef struct GlobalProperty { const char *driver; const char *property; const char *value; - bool user_provided; bool used; - Error **errp; } GlobalProperty; +static inline void +compat_props_add(GPtrArray *arr, + GlobalProperty props[], size_t nelem) +{ + int i; + for (i = 0; i < nelem; i++) { + g_ptr_array_add(arr, (void *)&props[i]); + } +} + /*** Board API. This should go away once we have a machine config file. ***/ DeviceState *qdev_create(BusState *bus, const char *name); @@ -412,6 +415,8 @@ const char *qdev_fw_name(DeviceState *dev); Object *qdev_get_machine(void); +void object_apply_compat_props(Object *obj); + /* FIXME: make this a link<> */ void qdev_set_parent_bus(DeviceState *dev, BusState *bus); diff --git a/include/hw/timer/nrf51_timer.h b/include/hw/timer/nrf51_timer.h new file mode 100644 index 0000000000..85cad2300d --- /dev/null +++ b/include/hw/timer/nrf51_timer.h @@ -0,0 +1,80 @@ +/* + * nRF51 System-on-Chip Timer peripheral + * + * QEMU interface: + * + sysbus MMIO regions 0: GPIO registers + * + sysbus irq + * + * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de> + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ +#ifndef NRF51_TIMER_H +#define NRF51_TIMER_H + +#include "hw/sysbus.h" +#include "qemu/timer.h" +#define TYPE_NRF51_TIMER "nrf51_soc.timer" +#define NRF51_TIMER(obj) OBJECT_CHECK(NRF51TimerState, (obj), TYPE_NRF51_TIMER) + +#define NRF51_TIMER_REG_COUNT 4 + +#define NRF51_TIMER_TASK_START 0x000 +#define NRF51_TIMER_TASK_STOP 0x004 +#define NRF51_TIMER_TASK_COUNT 0x008 +#define NRF51_TIMER_TASK_CLEAR 0x00C +#define NRF51_TIMER_TASK_SHUTDOWN 0x010 +#define NRF51_TIMER_TASK_CAPTURE_0 0x040 +#define NRF51_TIMER_TASK_CAPTURE_3 0x04C + +#define NRF51_TIMER_EVENT_COMPARE_0 0x140 +#define NRF51_TIMER_EVENT_COMPARE_1 0x144 +#define NRF51_TIMER_EVENT_COMPARE_2 0x148 +#define NRF51_TIMER_EVENT_COMPARE_3 0x14C + +#define NRF51_TIMER_REG_SHORTS 0x200 +#define NRF51_TIMER_REG_SHORTS_MASK 0xf0f +#define NRF51_TIMER_REG_INTENSET 0x304 +#define NRF51_TIMER_REG_INTENCLR 0x308 +#define NRF51_TIMER_REG_INTEN_MASK 0xf0000 +#define NRF51_TIMER_REG_MODE 0x504 +#define NRF51_TIMER_REG_MODE_MASK 0x01 +#define NRF51_TIMER_TIMER 0 +#define NRF51_TIMER_COUNTER 1 +#define NRF51_TIMER_REG_BITMODE 0x508 +#define NRF51_TIMER_REG_BITMODE_MASK 0x03 +#define NRF51_TIMER_WIDTH_16 0 +#define NRF51_TIMER_WIDTH_8 1 +#define NRF51_TIMER_WIDTH_24 2 +#define NRF51_TIMER_WIDTH_32 3 +#define NRF51_TIMER_REG_PRESCALER 0x510 +#define NRF51_TIMER_REG_PRESCALER_MASK 0x0F +#define NRF51_TIMER_REG_CC0 0x540 +#define NRF51_TIMER_REG_CC3 0x54C + +typedef struct NRF51TimerState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + qemu_irq irq; + + QEMUTimer timer; + int64_t timer_start_ns; + int64_t update_counter_ns; + uint32_t counter; + + bool running; + + uint8_t events_compare[NRF51_TIMER_REG_COUNT]; + uint32_t cc[NRF51_TIMER_REG_COUNT]; + uint32_t shorts; + uint32_t inten; + uint32_t mode; + uint32_t bitmode; + uint32_t prescaler; + +} NRF51TimerState; + + +#endif diff --git a/include/hw/usb.h b/include/hw/usb.h index a5080adecc..4961405fa0 100644 --- a/include/hw/usb.h +++ b/include/hw/usb.h @@ -593,8 +593,6 @@ const char *usb_device_get_product_desc(USBDevice *dev); const USBDesc *usb_device_get_usb_desc(USBDevice *dev); -int ehci_create_ich9_with_companions(PCIBus *bus, int slot); - /* quirks.c */ /* In bulk endpoints are streaming data sources (iow behave like isoc eps) */ diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index d59df20c4d..741935fe36 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -4,7 +4,7 @@ /* A load of opaque types so that device init declarations don't have to pull in all the real definitions. */ -/* Please keep this list in alphabetical order */ +/* Please keep this list in case-insensitive alphabetical order */ typedef struct AdapterInfo AdapterInfo; typedef struct AddressSpace AddressSpace; typedef struct AioContext AioContext; @@ -40,6 +40,7 @@ typedef struct HCIInfo HCIInfo; typedef struct HVFX86EmulatorState HVFX86EmulatorState; typedef struct I2CBus I2CBus; typedef struct I2SCodec I2SCodec; +typedef struct IOMMUMemoryRegion IOMMUMemoryRegion; typedef struct ISABus ISABus; typedef struct ISADevice ISADevice; typedef struct IsaDma IsaDma; @@ -49,7 +50,6 @@ typedef struct MachineState MachineState; typedef struct MemoryListener MemoryListener; typedef struct MemoryMappingList MemoryMappingList; typedef struct MemoryRegion MemoryRegion; -typedef struct IOMMUMemoryRegion IOMMUMemoryRegion; typedef struct MemoryRegionCache MemoryRegionCache; typedef struct MemoryRegionSection MemoryRegionSection; typedef struct MigrationIncomingState MigrationIncomingState; @@ -84,6 +84,8 @@ typedef struct PostcopyDiscardState PostcopyDiscardState; typedef struct Property Property; typedef struct PropertyInfo PropertyInfo; typedef struct PS2State PS2State; +typedef struct QBool QBool; +typedef struct QDict QDict; typedef struct QEMUBH QEMUBH; typedef struct QemuConsole QemuConsole; typedef struct QemuDmaBuf QemuDmaBuf; @@ -93,12 +95,10 @@ typedef struct QemuMutex QemuMutex; typedef struct QemuOpt QemuOpt; typedef struct QemuOpts QemuOpts; typedef struct QemuOptsList QemuOptsList; -typedef struct QemuSpin QemuSpin; typedef struct QEMUSGList QEMUSGList; +typedef struct QemuSpin QemuSpin; typedef struct QEMUTimer QEMUTimer; typedef struct QEMUTimerListGroup QEMUTimerListGroup; -typedef struct QBool QBool; -typedef struct QDict QDict; typedef struct QJSON QJSON; typedef struct QList QList; typedef struct QNull QNull; diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 1396f53e5b..6d1ba53d72 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -26,6 +26,7 @@ #include "exec/memattrs.h" #include "qapi/qapi-types-run-state.h" #include "qemu/bitmap.h" +#include "qemu/fprintf-fn.h" #include "qemu/rcu_queue.h" #include "qemu/queue.h" #include "qemu/thread.h" diff --git a/include/qom/object.h b/include/qom/object.h index bcae3f4951..e0262962b5 100644 --- a/include/qom/object.h +++ b/include/qom/object.h @@ -675,6 +675,9 @@ Object *object_new_with_propv(const char *typename, Error **errp, va_list vargs); +void object_apply_global_props(Object *obj, const GPtrArray *props, + Error **errp); + /** * object_set_props: * @obj: the object instance to set properties on diff --git a/include/sysemu/accel.h b/include/sysemu/accel.h index 637358f430..f331d128e9 100644 --- a/include/sysemu/accel.h +++ b/include/sysemu/accel.h @@ -49,7 +49,7 @@ typedef struct AccelClass { * global properties may be overridden by machine-type * compat_props or user-provided global properties. */ - GlobalProperty *global_props; + GPtrArray *compat_props; } AccelClass; #define TYPE_ACCEL "accel" @@ -67,8 +67,6 @@ typedef struct AccelClass { extern unsigned long tcg_tb_size; void configure_accelerator(MachineState *ms); -/* Register accelerator specific global properties */ -void accel_register_compat_props(AccelState *accel); /* Called just before os_setup_post (ie just before drop OS privs) */ void accel_setup_post(MachineState *ms); diff --git a/include/sysemu/hostmem.h b/include/sysemu/hostmem.h index 6e6bd2c1cb..a023b372a4 100644 --- a/include/sysemu/hostmem.h +++ b/include/sysemu/hostmem.h @@ -53,7 +53,7 @@ struct HostMemoryBackend { /* protected */ uint64_t size; - bool merge, dump; + bool merge, dump, use_canonical_path; bool prealloc, force_prealloc, is_mapped, share; DECLARE_BITMAP(host_nodes, MAX_NODES + 1); HostMemPolicy policy; @@ -67,5 +67,6 @@ MemoryRegion *host_memory_backend_get_memory(HostMemoryBackend *backend); void host_memory_backend_set_mapped(HostMemoryBackend *backend, bool mapped); bool host_memory_backend_is_mapped(HostMemoryBackend *backend); size_t host_memory_backend_pagesize(HostMemoryBackend *memdev); +char *host_memory_backend_get_name(HostMemoryBackend *backend); #endif diff --git a/include/ui/console.h b/include/ui/console.h index c17803c530..853fcf4eb7 100644 --- a/include/ui/console.h +++ b/include/ui/console.h @@ -257,10 +257,6 @@ DisplaySurface *qemu_create_displaysurface_from(int width, int height, pixman_format_code_t format, int linesize, uint8_t *data); DisplaySurface *qemu_create_displaysurface_pixman(pixman_image_t *image); -DisplaySurface *qemu_create_displaysurface_guestmem(int width, int height, - pixman_format_code_t format, - int linesize, - uint64_t addr); DisplaySurface *qemu_create_message_surface(int w, int h, const char *msg); PixelFormat qemu_default_pixelformat(int bpp); diff --git a/include/ui/qemu-spice.h b/include/ui/qemu-spice.h index c6d50eb87a..8c23dfe717 100644 --- a/include/ui/qemu-spice.h +++ b/include/ui/qemu-spice.h @@ -46,13 +46,7 @@ int qemu_spice_migrate_info(const char *hostname, int port, int tls_port, #else #define SPICE_NEEDS_SET_MM_TIME 0 #endif - -#if SPICE_SERVER_VERSION >= 0x000c02 void qemu_spice_register_ports(void); -#else -static inline Chardev *qemu_chr_open_spice_port(const char *name) -{ return NULL; } -#endif #else /* CONFIG_SPICE */ diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c index 2ae120a2bc..619a56950d 100644 --- a/linux-user/ppc/signal.c +++ b/linux-user/ppc/signal.c @@ -258,8 +258,8 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame) /* Save Altivec registers if necessary. */ if (env->insns_flags & PPC_ALTIVEC) { uint32_t *vrsave; - for (i = 0; i < ARRAY_SIZE(env->avr); i++) { - ppc_avr_t *avr = &env->avr[i]; + for (i = 0; i < 32; i++) { + ppc_avr_t *avr = cpu_avr_ptr(env, i); ppc_avr_t *vreg = (ppc_avr_t *)&frame->mc_vregs.altivec[i]; __put_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); @@ -281,15 +281,17 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame) /* Save VSX second halves */ if (env->insns_flags2 & PPC2_VSX) { uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34]; - for (i = 0; i < ARRAY_SIZE(env->vsr); i++) { - __put_user(env->vsr[i], &vsregs[i]); + for (i = 0; i < 32; i++) { + uint64_t *vsrl = cpu_vsrl_ptr(env, i); + __put_user(*vsrl, &vsregs[i]); } } /* Save floating point registers. */ if (env->insns_flags & PPC_FLOAT) { - for (i = 0; i < ARRAY_SIZE(env->fpr); i++) { - __put_user(env->fpr[i], &frame->mc_fregs[i]); + for (i = 0; i < 32; i++) { + uint64_t *fpr = cpu_fpr_ptr(env, i); + __put_user(*fpr, &frame->mc_fregs[i]); } __put_user((uint64_t) env->fpscr, &frame->mc_fregs[32]); } @@ -373,8 +375,8 @@ static void restore_user_regs(CPUPPCState *env, #else v_regs = (ppc_avr_t *)frame->mc_vregs.altivec; #endif - for (i = 0; i < ARRAY_SIZE(env->avr); i++) { - ppc_avr_t *avr = &env->avr[i]; + for (i = 0; i < 32; i++) { + ppc_avr_t *avr = cpu_avr_ptr(env, i); ppc_avr_t *vreg = &v_regs[i]; __get_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); @@ -393,16 +395,18 @@ static void restore_user_regs(CPUPPCState *env, /* Restore VSX second halves */ if (env->insns_flags2 & PPC2_VSX) { uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34]; - for (i = 0; i < ARRAY_SIZE(env->vsr); i++) { - __get_user(env->vsr[i], &vsregs[i]); + for (i = 0; i < 32; i++) { + uint64_t *vsrl = cpu_vsrl_ptr(env, i); + __get_user(*vsrl, &vsregs[i]); } } /* Restore floating point registers. */ if (env->insns_flags & PPC_FLOAT) { uint64_t fpscr; - for (i = 0; i < ARRAY_SIZE(env->fpr); i++) { - __get_user(env->fpr[i], &frame->mc_fregs[i]); + for (i = 0; i < 32; i++) { + uint64_t *fpr = cpu_fpr_ptr(env, i); + __get_user(*fpr, &frame->mc_fregs[i]); } __get_user(fpscr, &frame->mc_fregs[32]); env->fpscr = (uint32_t) fpscr; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 280137da8c..d6605b8b50 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -2352,6 +2352,45 @@ static abi_long do_getsockopt(int sockfd, int level, int optname, break; } break; + case SOL_IPV6: + switch (optname) { + case IPV6_MTU_DISCOVER: + case IPV6_MTU: + case IPV6_V6ONLY: + case IPV6_RECVPKTINFO: + case IPV6_UNICAST_HOPS: + case IPV6_MULTICAST_HOPS: + case IPV6_MULTICAST_LOOP: + case IPV6_RECVERR: + case IPV6_RECVHOPLIMIT: + case IPV6_2292HOPLIMIT: + case IPV6_CHECKSUM: + if (get_user_u32(len, optlen)) + return -TARGET_EFAULT; + if (len < 0) + return -TARGET_EINVAL; + lv = sizeof(lv); + ret = get_errno(getsockopt(sockfd, level, optname, &val, &lv)); + if (ret < 0) + return ret; + if (len < sizeof(int) && len > 0 && val >= 0 && val < 255) { + len = 1; + if (put_user_u32(len, optlen) + || put_user_u8(val, optval_addr)) + return -TARGET_EFAULT; + } else { + if (len > sizeof(int)) + len = sizeof(int); + if (put_user_u32(len, optlen) + || put_user_u32(val, optval_addr)) + return -TARGET_EFAULT; + } + break; + default: + ret = -TARGET_ENOPROTOOPT; + break; + } + break; default: unimplemented: gemu_log("getsockopt level=%d optname=%d not yet supported\n", @@ -9677,8 +9716,15 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, arg4 = arg5; arg5 = arg6; } - if (!(p = lock_user(VERIFY_WRITE, arg2, arg3, 0))) - return -TARGET_EFAULT; + if (arg2 == 0 && arg3 == 0) { + /* Special-case NULL buffer and zero length, which should succeed */ + p = 0; + } else { + p = lock_user(VERIFY_WRITE, arg2, arg3, 0); + if (!p) { + return -TARGET_EFAULT; + } + } ret = get_errno(pread64(arg1, p, arg3, target_offset64(arg4, arg5))); unlock_user(p, arg2, ret); return ret; @@ -9687,8 +9733,15 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, arg4 = arg5; arg5 = arg6; } - if (!(p = lock_user(VERIFY_READ, arg2, arg3, 1))) - return -TARGET_EFAULT; + if (arg2 == 0 && arg3 == 0) { + /* Special-case NULL buffer and zero length, which should succeed */ + p = 0; + } else { + p = lock_user(VERIFY_READ, arg2, arg3, 1); + if (!p) { + return -TARGET_EFAULT; + } + } ret = get_errno(pwrite64(arg1, p, arg3, target_offset64(arg4, arg5))); unlock_user(p, arg2, 0); return ret; diff --git a/nbd/client.c b/nbd/client.c index b4d457a19a..f625c207c5 100644 --- a/nbd/client.c +++ b/nbd/client.c @@ -132,8 +132,9 @@ static int nbd_receive_option_reply(QIOChannel *ioc, uint32_t opt, return -1; } if (reply->option != opt) { - error_setg(errp, "Unexpected option type %x expected %x", - reply->option, opt); + error_setg(errp, "Unexpected option type %u (%s), expected %u (%s)", + reply->option, nbd_opt_lookup(reply->option), + opt, nbd_opt_lookup(opt)); nbd_send_opt_abort(ioc); return -1; } @@ -171,6 +172,8 @@ static int nbd_handle_reply_err(QIOChannel *ioc, NBDOptionReply *reply, goto cleanup; } msg[reply->length] = '\0'; + trace_nbd_server_error_msg(reply->type, + nbd_reply_type_lookup(reply->type), msg); } switch (reply->type) { @@ -265,8 +268,9 @@ static int nbd_receive_list(QIOChannel *ioc, const char *want, bool *match, } return 0; } else if (reply.type != NBD_REP_SERVER) { - error_setg(errp, "Unexpected reply type %" PRIx32 " expected %x", - reply.type, NBD_REP_SERVER); + error_setg(errp, "Unexpected reply type %u (%s), expected %u (%s)", + reply.type, nbd_rep_lookup(reply.type), + NBD_REP_SERVER, nbd_rep_lookup(NBD_REP_SERVER)); nbd_send_opt_abort(ioc); return -1; } @@ -378,9 +382,9 @@ static int nbd_opt_go(QIOChannel *ioc, const char *wantname, return 1; } if (reply.type != NBD_REP_INFO) { - error_setg(errp, "unexpected reply type %" PRIu32 - " (%s), expected %u", - reply.type, nbd_rep_lookup(reply.type), NBD_REP_INFO); + error_setg(errp, "unexpected reply type %u (%s), expected %u (%s)", + reply.type, nbd_rep_lookup(reply.type), + NBD_REP_INFO, nbd_rep_lookup(NBD_REP_INFO)); nbd_send_opt_abort(ioc); return -1; } @@ -704,8 +708,9 @@ static int nbd_negotiate_simple_meta_context(QIOChannel *ioc, } if (reply.type != NBD_REP_ACK) { - error_setg(errp, "Unexpected reply type %" PRIx32 " expected %x", - reply.type, NBD_REP_ACK); + error_setg(errp, "Unexpected reply type %u (%s), expected %u (%s)", + reply.type, nbd_rep_lookup(reply.type), + NBD_REP_ACK, nbd_rep_lookup(NBD_REP_ACK)); nbd_send_opt_abort(ioc); return -1; } @@ -728,7 +733,6 @@ int nbd_receive_negotiate(QIOChannel *ioc, const char *name, QIOChannel **outioc, NBDExportInfo *info, Error **errp) { - char buf[256]; uint64_t magic; int rc; bool zeroes = true; @@ -749,27 +753,20 @@ int nbd_receive_negotiate(QIOChannel *ioc, const char *name, goto fail; } - if (nbd_read(ioc, buf, 8, errp) < 0) { - error_prepend(errp, "Failed to read data: "); - goto fail; - } - - buf[8] = '\0'; - if (strlen(buf) == 0) { - error_setg(errp, "Server connection closed unexpectedly"); + if (nbd_read(ioc, &magic, sizeof(magic), errp) < 0) { + error_prepend(errp, "Failed to read initial magic: "); goto fail; } - - magic = ldq_be_p(buf); + magic = be64_to_cpu(magic); trace_nbd_receive_negotiate_magic(magic); - if (memcmp(buf, "NBDMAGIC", 8) != 0) { - error_setg(errp, "Invalid magic received"); + if (magic != NBD_INIT_MAGIC) { + error_setg(errp, "Bad initial magic received: 0x%" PRIx64, magic); goto fail; } if (nbd_read(ioc, &magic, sizeof(magic), errp) < 0) { - error_prepend(errp, "Failed to read magic: "); + error_prepend(errp, "Failed to read server magic: "); goto fail; } magic = be64_to_cpu(magic); @@ -908,7 +905,7 @@ int nbd_receive_negotiate(QIOChannel *ioc, const char *name, } info->flags = oldflags; } else { - error_setg(errp, "Bad magic received"); + error_setg(errp, "Bad server magic received: 0x%" PRIx64, magic); goto fail; } @@ -1026,23 +1023,7 @@ int nbd_disconnect(int fd) return 0; } -#else -int nbd_init(int fd, QIOChannelSocket *ioc, NBDExportInfo *info, - Error **errp) -{ - error_setg(errp, "nbd_init is only supported on Linux"); - return -ENOTSUP; -} - -int nbd_client(int fd) -{ - return -ENOTSUP; -} -int nbd_disconnect(int fd) -{ - return -ENOTSUP; -} -#endif +#endif /* __linux__ */ int nbd_send_request(QIOChannel *ioc, NBDRequest *request) { diff --git a/nbd/nbd-internal.h b/nbd/nbd-internal.h index eeff78d3c9..82aa221227 100644 --- a/nbd/nbd-internal.h +++ b/nbd/nbd-internal.h @@ -46,8 +46,9 @@ /* Size of oldstyle negotiation */ #define NBD_OLDSTYLE_NEGOTIATE_SIZE (8 + 8 + 8 + 4 + 124) +#define NBD_INIT_MAGIC 0x4e42444d41474943LL /* ASCII "NBDMAGIC" */ #define NBD_REQUEST_MAGIC 0x25609513 -#define NBD_OPTS_MAGIC 0x49484156454F5054LL +#define NBD_OPTS_MAGIC 0x49484156454F5054LL /* ASCII "IHAVEOPT" */ #define NBD_CLIENT_MAGIC 0x0000420281861253LL #define NBD_REP_MAGIC 0x0003e889045565a9LL @@ -100,11 +101,6 @@ struct NBDTLSHandshakeData { void nbd_tls_handshake(QIOTask *task, void *opaque); -const char *nbd_opt_lookup(uint32_t opt); -const char *nbd_rep_lookup(uint32_t rep); -const char *nbd_info_lookup(uint16_t info); -const char *nbd_cmd_lookup(uint16_t info); -const char *nbd_err_lookup(int err); int nbd_drop(QIOChannel *ioc, size_t size, Error **errp); diff --git a/nbd/trace-events b/nbd/trace-events index 5e1d4afe8e..5492042acb 100644 --- a/nbd/trace-events +++ b/nbd/trace-events @@ -1,6 +1,7 @@ # nbd/client.c nbd_send_option_request(uint32_t opt, const char *name, uint32_t len) "Sending option request %" PRIu32" (%s), len %" PRIu32 nbd_receive_option_reply(uint32_t option, const char *optname, uint32_t type, const char *typename, uint32_t length) "Received option reply %" PRIu32" (%s), type %" PRIu32" (%s), len %" PRIu32 +nbd_server_error_msg(uint32_t err, const char *type, const char *msg) "server reported error 0x%" PRIx32 " (%s) with additional message: %s" nbd_reply_err_unsup(uint32_t option, const char *name) "server doesn't understand request %" PRIu32 " (%s), attempting fallback" nbd_opt_go_start(const char *name) "Attempting NBD_OPT_GO for export '%s'" nbd_opt_go_success(void) "Export is good to go" diff --git a/pc-bios/keymaps/common b/pc-bios/keymaps/common deleted file mode 100644 index adc56c77d2..0000000000 --- a/pc-bios/keymaps/common +++ /dev/null @@ -1,157 +0,0 @@ -include modifiers - -# -# Top row -# -1 0x2 -2 0x3 -3 0x4 -4 0x5 -5 0x6 -6 0x7 -7 0x8 -8 0x9 -9 0xa -0 0xb -BackSpace 0xe - -# -# QWERTY first row -# -Tab 0xf localstate -ISO_Left_Tab 0xf shift -q 0x10 addupper -w 0x11 addupper -e 0x12 addupper -r 0x13 addupper -t 0x14 addupper -y 0x15 addupper -u 0x16 addupper -i 0x17 addupper -o 0x18 addupper -p 0x19 addupper - -# -# QWERTY second row -# -a 0x1e addupper -s 0x1f addupper -d 0x20 addupper -f 0x21 addupper -g 0x22 addupper -h 0x23 addupper -j 0x24 addupper -k 0x25 addupper -l 0x26 addupper -Return 0x1c localstate - -# -# QWERTY third row -# -z 0x2c addupper -x 0x2d addupper -c 0x2e addupper -v 0x2f addupper -b 0x30 addupper -n 0x31 addupper -m 0x32 addupper - -space 0x39 localstate - -less 0x56 -greater 0x56 shift -bar 0x56 altgr -brokenbar 0x56 shift altgr - -# -# Esc and Function keys -# -Escape 0x1 localstate -F1 0x3b localstate -F2 0x3c localstate -F3 0x3d localstate -F4 0x3e localstate -F5 0x3f localstate -F6 0x40 localstate -F7 0x41 localstate -F8 0x42 localstate -F9 0x43 localstate -F10 0x44 localstate -F11 0x57 localstate -F12 0x58 localstate - -# Printscreen, Scrollock and Pause -# Printscreen really requires four scancodes (0xe0, 0x2a, 0xe0, 0x37), -# but (0xe0, 0x37) seems to work. -Print 0xb7 localstate -Sys_Req 0xb7 localstate -Execute 0xb7 localstate -Scroll_Lock 0x46 - -# -# Insert - PgDown -# -Insert 0xd2 localstate -Delete 0xd3 localstate -Home 0xc7 localstate -End 0xcf localstate -Page_Up 0xc9 localstate -Page_Down 0xd1 localstate - -# -# Arrow keys -# -Left 0xcb localstate -Up 0xc8 localstate -Down 0xd0 localstate -Right 0xcd localstate - -# -# Numpad -# -Num_Lock 0x45 -KP_Divide 0xb5 -KP_Multiply 0x37 -KP_Subtract 0x4a -KP_Add 0x4e -KP_Enter 0x9c - -KP_Decimal 0x53 numlock -KP_Separator 0x53 numlock -KP_Delete 0x53 - -KP_0 0x52 numlock -KP_Insert 0x52 - -KP_1 0x4f numlock -KP_End 0x4f - -KP_2 0x50 numlock -KP_Down 0x50 - -KP_3 0x51 numlock -KP_Next 0x51 - -KP_4 0x4b numlock -KP_Left 0x4b - -KP_5 0x4c numlock -KP_Begin 0x4c - -KP_6 0x4d numlock -KP_Right 0x4d - -KP_7 0x47 numlock -KP_Home 0x47 - -KP_8 0x48 numlock -KP_Up 0x48 - -KP_9 0x49 numlock -KP_Prior 0x49 - -Caps_Lock 0x3a -# -# Inhibited keys -# -Multi_key 0x0 inhibit diff --git a/pc-bios/keymaps/modifiers b/pc-bios/keymaps/modifiers deleted file mode 100644 index d73b7a6637..0000000000 --- a/pc-bios/keymaps/modifiers +++ /dev/null @@ -1,18 +0,0 @@ -Shift_R 0x36 -Shift_L 0x2a - -Alt_R 0xb8 -Mode_switch 0xb8 -ISO_Level3_Shift 0xb8 -Alt_L 0x38 - -Control_R 0x9d -Control_L 0x1d - -# Translate Super to Windows keys. -# This is hardcoded. See documentation for details. -Super_R 0xdc -Super_L 0xdb - -# Translate Menu to the Windows Application key. -Menu 0xdd diff --git a/pc-bios/keymaps/nl-be b/pc-bios/keymaps/nl-be deleted file mode 100644 index 34fc881ad0..0000000000 --- a/pc-bios/keymaps/nl-be +++ /dev/null @@ -1,3 +0,0 @@ -# Dutch (Belgium) -map 0x813 -include common diff --git a/pc-bios/keymaps/sl b/pc-bios/keymaps/sl index 56835a92c3..73eb956d04 100644 --- a/pc-bios/keymaps/sl +++ b/pc-bios/keymaps/sl @@ -1,5 +1,180 @@ # generated from XKB map sl -include common + +Shift_R 0x36 +Shift_L 0x2a + +Alt_R 0xb8 +Mode_switch 0xb8 +ISO_Level3_Shift 0xb8 +Alt_L 0x38 + +Control_R 0x9d +Control_L 0x1d + +# Translate Super to Windows keys. +# This is hardcoded. See documentation for details. +Super_R 0xdc +Super_L 0xdb + +# Translate Menu to the Windows Application key. +Menu 0xdd + +# +# Top row +# +1 0x2 +2 0x3 +3 0x4 +4 0x5 +5 0x6 +6 0x7 +7 0x8 +8 0x9 +9 0xa +0 0xb +BackSpace 0xe + +# +# QWERTY first row +# +Tab 0xf localstate +ISO_Left_Tab 0xf shift +q 0x10 addupper +w 0x11 addupper +e 0x12 addupper +r 0x13 addupper +t 0x14 addupper +y 0x15 addupper +u 0x16 addupper +i 0x17 addupper +o 0x18 addupper +p 0x19 addupper + +# +# QWERTY second row +# +a 0x1e addupper +s 0x1f addupper +d 0x20 addupper +f 0x21 addupper +g 0x22 addupper +h 0x23 addupper +j 0x24 addupper +k 0x25 addupper +l 0x26 addupper +Return 0x1c localstate + +# +# QWERTY third row +# +z 0x2c addupper +x 0x2d addupper +c 0x2e addupper +v 0x2f addupper +b 0x30 addupper +n 0x31 addupper +m 0x32 addupper + +space 0x39 localstate + +less 0x56 +greater 0x56 shift +bar 0x56 altgr +brokenbar 0x56 shift altgr + +# +# Esc and Function keys +# +Escape 0x1 localstate +F1 0x3b localstate +F2 0x3c localstate +F3 0x3d localstate +F4 0x3e localstate +F5 0x3f localstate +F6 0x40 localstate +F7 0x41 localstate +F8 0x42 localstate +F9 0x43 localstate +F10 0x44 localstate +F11 0x57 localstate +F12 0x58 localstate + +# Printscreen, Scrollock and Pause +# Printscreen really requires four scancodes (0xe0, 0x2a, 0xe0, 0x37), +# but (0xe0, 0x37) seems to work. +Print 0xb7 localstate +Sys_Req 0xb7 localstate +Execute 0xb7 localstate +Scroll_Lock 0x46 + +# +# Insert - PgDown +# +Insert 0xd2 localstate +Delete 0xd3 localstate +Home 0xc7 localstate +End 0xcf localstate +Page_Up 0xc9 localstate +Page_Down 0xd1 localstate + +# +# Arrow keys +# +Left 0xcb localstate +Up 0xc8 localstate +Down 0xd0 localstate +Right 0xcd localstate + +# +# Numpad +# +Num_Lock 0x45 +KP_Divide 0xb5 +KP_Multiply 0x37 +KP_Subtract 0x4a +KP_Add 0x4e +KP_Enter 0x9c + +KP_Decimal 0x53 numlock +KP_Separator 0x53 numlock +KP_Delete 0x53 + +KP_0 0x52 numlock +KP_Insert 0x52 + +KP_1 0x4f numlock +KP_End 0x4f + +KP_2 0x50 numlock +KP_Down 0x50 + +KP_3 0x51 numlock +KP_Next 0x51 + +KP_4 0x4b numlock +KP_Left 0x4b + +KP_5 0x4c numlock +KP_Begin 0x4c + +KP_6 0x4d numlock +KP_Right 0x4d + +KP_7 0x47 numlock +KP_Home 0x47 + +KP_8 0x48 numlock +KP_Up 0x48 + +KP_9 0x49 numlock +KP_Prior 0x49 + +Caps_Lock 0x3a +# +# Inhibited keys +# +Multi_key 0x0 inhibit + map 0x424 exclam 0x02 shift asciitilde 0x02 altgr diff --git a/pc-bios/keymaps/sv b/pc-bios/keymaps/sv index 5d9080eff1..0717b7114f 100644 --- a/pc-bios/keymaps/sv +++ b/pc-bios/keymaps/sv @@ -1,5 +1,179 @@ map 0x0000041d -include common + +Shift_R 0x36 +Shift_L 0x2a + +Alt_R 0xb8 +Mode_switch 0xb8 +ISO_Level3_Shift 0xb8 +Alt_L 0x38 + +Control_R 0x9d +Control_L 0x1d + +# Translate Super to Windows keys. +# This is hardcoded. See documentation for details. +Super_R 0xdc +Super_L 0xdb + +# Translate Menu to the Windows Application key. +Menu 0xdd + +# +# Top row +# +1 0x2 +2 0x3 +3 0x4 +4 0x5 +5 0x6 +6 0x7 +7 0x8 +8 0x9 +9 0xa +0 0xb +BackSpace 0xe + +# +# QWERTY first row +# +Tab 0xf localstate +ISO_Left_Tab 0xf shift +q 0x10 addupper +w 0x11 addupper +e 0x12 addupper +r 0x13 addupper +t 0x14 addupper +y 0x15 addupper +u 0x16 addupper +i 0x17 addupper +o 0x18 addupper +p 0x19 addupper + +# +# QWERTY second row +# +a 0x1e addupper +s 0x1f addupper +d 0x20 addupper +f 0x21 addupper +g 0x22 addupper +h 0x23 addupper +j 0x24 addupper +k 0x25 addupper +l 0x26 addupper +Return 0x1c localstate + +# +# QWERTY third row +# +z 0x2c addupper +x 0x2d addupper +c 0x2e addupper +v 0x2f addupper +b 0x30 addupper +n 0x31 addupper +m 0x32 addupper + +space 0x39 localstate + +less 0x56 +greater 0x56 shift +bar 0x56 altgr +brokenbar 0x56 shift altgr + +# +# Esc and Function keys +# +Escape 0x1 localstate +F1 0x3b localstate +F2 0x3c localstate +F3 0x3d localstate +F4 0x3e localstate +F5 0x3f localstate +F6 0x40 localstate +F7 0x41 localstate +F8 0x42 localstate +F9 0x43 localstate +F10 0x44 localstate +F11 0x57 localstate +F12 0x58 localstate + +# Printscreen, Scrollock and Pause +# Printscreen really requires four scancodes (0xe0, 0x2a, 0xe0, 0x37), +# but (0xe0, 0x37) seems to work. +Print 0xb7 localstate +Sys_Req 0xb7 localstate +Execute 0xb7 localstate +Scroll_Lock 0x46 + +# +# Insert - PgDown +# +Insert 0xd2 localstate +Delete 0xd3 localstate +Home 0xc7 localstate +End 0xcf localstate +Page_Up 0xc9 localstate +Page_Down 0xd1 localstate + +# +# Arrow keys +# +Left 0xcb localstate +Up 0xc8 localstate +Down 0xd0 localstate +Right 0xcd localstate + +# +# Numpad +# +Num_Lock 0x45 +KP_Divide 0xb5 +KP_Multiply 0x37 +KP_Subtract 0x4a +KP_Add 0x4e +KP_Enter 0x9c + +KP_Decimal 0x53 numlock +KP_Separator 0x53 numlock +KP_Delete 0x53 + +KP_0 0x52 numlock +KP_Insert 0x52 + +KP_1 0x4f numlock +KP_End 0x4f + +KP_2 0x50 numlock +KP_Down 0x50 + +KP_3 0x51 numlock +KP_Next 0x51 + +KP_4 0x4b numlock +KP_Left 0x4b + +KP_5 0x4c numlock +KP_Begin 0x4c + +KP_6 0x4d numlock +KP_Right 0x4d + +KP_7 0x47 numlock +KP_Home 0x47 + +KP_8 0x48 numlock +KP_Up 0x48 + +KP_9 0x49 numlock +KP_Prior 0x49 + +Caps_Lock 0x3a +# +# Inhibited keys +# +Multi_key 0x0 inhibit # # Top row diff --git a/pc-bios/palcode-clipper b/pc-bios/palcode-clipper Binary files differindex 1df377a0fd..fb9026ae64 100644 --- a/pc-bios/palcode-clipper +++ b/pc-bios/palcode-clipper diff --git a/qemu-nbd.c b/qemu-nbd.c index ca7109652e..2807e13239 100644 --- a/qemu-nbd.c +++ b/qemu-nbd.c @@ -43,6 +43,12 @@ #include "trace/control.h" #include "qemu-version.h" +#ifdef __linux__ +#define HAVE_NBD_DEVICE 1 +#else +#define HAVE_NBD_DEVICE 0 +#endif + #define SOCKET_PATH "/var/lock/qemu-nbd-%s" #define QEMU_NBD_OPT_CACHE 256 #define QEMU_NBD_OPT_AIO 257 @@ -98,11 +104,11 @@ static void usage(const char *name) " specify tracing options\n" " --fork fork off the server process and exit the parent\n" " once the server is running\n" -#ifdef __linux__ +#if HAVE_NBD_DEVICE +"\n" "Kernel NBD client support:\n" " -c, --connect=DEV connect FILE to the local NBD device DEV\n" " -d, --disconnect disconnect the specified device\n" -"\n" #endif "\n" "Block device options:\n" @@ -236,6 +242,7 @@ static void termsig_handler(int signum) } +#if HAVE_NBD_DEVICE static void *show_parts(void *arg) { char *device = arg; @@ -321,6 +328,7 @@ out: kill(getpid(), SIGTERM); return (void *) EXIT_FAILURE; } +#endif /* HAVE_NBD_DEVICE */ static int nbd_can_accept(void) { @@ -571,6 +579,7 @@ int main(int argc, char **argv) #endif module_call_init(MODULE_INIT_TRACE); + error_set_progname(argv[0]); qcrypto_init(&error_fatal); module_call_init(MODULE_INIT_QOM); @@ -813,6 +822,12 @@ int main(int argc, char **argv) } } +#if !HAVE_NBD_DEVICE + if (disconnect || device) { + error_report("Kernel /dev/nbdN support not available"); + exit(EXIT_FAILURE); + } +#else /* HAVE_NBD_DEVICE */ if (disconnect) { int nbdfd = open(argv[optind], O_RDWR); if (nbdfd < 0) { @@ -828,6 +843,7 @@ int main(int argc, char **argv) return 0; } +#endif if ((device && !verbose) || fork_process) { int stderr_fd[2]; @@ -1005,6 +1021,7 @@ int main(int argc, char **argv) nbd_export_set_description(exp, export_description); if (device) { +#if HAVE_NBD_DEVICE int ret; ret = pthread_create(&client_thread, NULL, nbd_client_thread, device); @@ -1012,6 +1029,7 @@ int main(int argc, char **argv) error_report("Failed to create client thread: %s", strerror(ret)); exit(EXIT_FAILURE); } +#endif } else { /* Shut up GCC warnings. */ memset(&client_thread, 0, sizeof(client_thread)); diff --git a/qemu-options.hx b/qemu-options.hx index df42116ecc..d4f3564b78 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -538,8 +538,8 @@ ETEXI DEF("name", HAS_ARG, QEMU_OPTION_name, "-name string1[,process=string2][,debug-threads=on|off]\n" " set the name of the guest\n" - " string1 sets the window title and string2 the process name (on Linux)\n" - " When debug-threads is enabled, individual threads are given a separate name (on Linux)\n" + " string1 sets the window title and string2 the process name\n" + " When debug-threads is enabled, individual threads are given a separate name\n" " NOTE: The thread names are for debugging and not a stable API.\n", QEMU_ARCH_ALL) STEXI @@ -312,7 +312,6 @@ static void cpu_common_parse_features(const char *typename, char *features, prop->driver = typename; prop->property = g_strdup(featurestr); prop->value = g_strdup(val); - prop->errp = &error_fatal; qdev_prop_register_global(prop); } else { error_setg(errp, "Expected key=value format, found %s.", diff --git a/qom/object.c b/qom/object.c index 17921c0a71..aa6f3a2a71 100644 --- a/qom/object.c +++ b/qom/object.c @@ -370,6 +370,41 @@ static void object_post_init_with_type(Object *obj, TypeImpl *ti) } } +void object_apply_global_props(Object *obj, const GPtrArray *props, Error **errp) +{ + Error *err = NULL; + int i; + + if (!props) { + return; + } + + for (i = 0; i < props->len; i++) { + GlobalProperty *p = g_ptr_array_index(props, i); + + if (object_dynamic_cast(obj, p->driver) == NULL) { + continue; + } + p->used = true; + object_property_parse(obj, p->value, p->property, &err); + if (err != NULL) { + error_prepend(&err, "can't apply global %s.%s=%s: ", + p->driver, p->property, p->value); + /* + * If errp != NULL, propagate error and return. + * If errp == NULL, report a warning, but keep going + * with the remaining globals. + */ + if (errp) { + error_propagate(errp, err); + return; + } else { + warn_report_err(err); + } + } + } +} + static void object_initialize_with_type(void *data, size_t size, TypeImpl *type) { Object *obj = data; @@ -164,6 +164,17 @@ static bool qtest_opened; * where NUM is an IRQ number. For the PC, interrupts can be intercepted * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with * NUM=0 even though it is remapped to GSI 2). + * + * Setting interrupt level: + * + * > set_irq_in QOM-PATH NAME NUM LEVEL + * < OK + * + * where NAME is the name of the irq/gpio list, NUM is an IRQ number and + * LEVEL is an signed integer IRQ level. + * + * Forcibly set the given interrupt pin to the given level. + * */ static int hex2nib(char ch) @@ -326,7 +337,39 @@ static void qtest_process_command(CharBackend *chr, gchar **words) irq_intercept_dev = dev; qtest_send_prefix(chr); qtest_send(chr, "OK\n"); + } else if (strcmp(words[0], "set_irq_in") == 0) { + DeviceState *dev; + qemu_irq irq; + char *name; + int ret; + int num; + int level; + + g_assert(words[1] && words[2] && words[3] && words[4]); + dev = DEVICE(object_resolve_path(words[1], NULL)); + if (!dev) { + qtest_send_prefix(chr); + qtest_send(chr, "FAIL Unknown device\n"); + return; + } + + if (strcmp(words[2], "unnamed-gpio-in") == 0) { + name = NULL; + } else { + name = words[2]; + } + + ret = qemu_strtoi(words[3], NULL, 0, &num); + g_assert(!ret); + ret = qemu_strtoi(words[4], NULL, 0, &level); + g_assert(!ret); + + irq = qdev_get_gpio_in_named(dev, name, num); + + qemu_set_irq(irq, level); + qtest_send_prefix(chr); + qtest_send(chr, "OK\n"); } else if (strcmp(words[0], "outb") == 0 || strcmp(words[0], "outw") == 0 || strcmp(words[0], "outl") == 0) { diff --git a/roms/qemu-palcode b/roms/qemu-palcode -Subproject f3c7e44c70254975df2a00af39701eafbac4d47 +Subproject 51c237d7e20d05100eacadee2f61abc17e6bc09 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index a953897fcc..1fd95d6c0f 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -205,9 +205,9 @@ static void alpha_cpu_initfn(Object *obj) env->lock_addr = -1; #if defined(CONFIG_USER_ONLY) env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; - cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD - | FPCR_UNFD | FPCR_INED | FPCR_DNOD - | FPCR_DYN_NORMAL)); + cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD + | FPCR_UNFD | FPCR_INED | FPCR_DNOD + | FPCR_DYN_NORMAL) << 32); #else env->flags = ENV_FLAG_PAL_MODE | ENV_FLAG_FEN; #endif diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index d135ff8e06..2049fa9612 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -35,6 +35,8 @@ struct arm_boot_info; #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU +typedef struct ARMCPUInfo ARMCPUInfo; + /** * ARMCPUClass: * @parent_realize: The parent class' realize handler. @@ -47,6 +49,7 @@ typedef struct ARMCPUClass { CPUClass parent_class; /*< public >*/ + const ARMCPUInfo *info; DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); } ARMCPUClass; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c8505eaaee..4c4e9e169e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -740,7 +740,7 @@ static Property arm_cpu_pmsav7_dregion_property = static Property arm_cpu_initsvtor_property = DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0); -static void arm_cpu_post_init(Object *obj) +void arm_cpu_post_init(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -1457,8 +1457,10 @@ static void cortex_m33_initfn(Object *obj) static void arm_v7m_class_init(ObjectClass *oc, void *data) { + ARMCPUClass *acc = ARM_CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(oc); + acc->info = data; #ifndef CONFIG_USER_ONLY cc->do_interrupt = arm_v7m_cpu_do_interrupt; #endif @@ -1959,11 +1961,11 @@ static void arm_max_initfn(Object *obj) #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ -typedef struct ARMCPUInfo { +struct ARMCPUInfo { const char *name; void (*initfn)(Object *obj); void (*class_init)(ObjectClass *oc, void *data); -} ARMCPUInfo; +}; static const ARMCPUInfo arm_cpus[] = { #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) @@ -2113,6 +2115,7 @@ static void arm_host_initfn(Object *obj) ARMCPU *cpu = ARM_CPU(obj); kvm_arm_set_cpu_features_from_host(cpu); + arm_cpu_post_init(obj); } static const TypeInfo host_arm_cpu_type_info = { @@ -2127,14 +2130,30 @@ static const TypeInfo host_arm_cpu_type_info = { #endif +static void arm_cpu_instance_init(Object *obj) +{ + ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); + + acc->info->initfn(obj); + arm_cpu_post_init(obj); +} + +static void cpu_register_class_init(ObjectClass *oc, void *data) +{ + ARMCPUClass *acc = ARM_CPU_CLASS(oc); + + acc->info = data; +} + static void cpu_register(const ARMCPUInfo *info) { TypeInfo type_info = { .parent = TYPE_ARM_CPU, .instance_size = sizeof(ARMCPU), - .instance_init = info->initfn, + .instance_init = arm_cpu_instance_init, .class_size = sizeof(ARMCPUClass), - .class_init = info->class_init, + .class_init = info->class_init ?: cpu_register_class_init, + .class_data = (void *)info, }; type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); @@ -2147,7 +2166,6 @@ static const TypeInfo arm_cpu_type_info = { .parent = TYPE_CPU, .instance_size = sizeof(ARMCPU), .instance_init = arm_cpu_initfn, - .instance_post_init = arm_cpu_post_init, .instance_finalize = arm_cpu_finalizefn, .abstract = true, .class_size = sizeof(ARMCPUClass), diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c943f35dd9..6f606eb97b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -884,6 +884,8 @@ static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) return container_of(env, ARMCPU, env); } +void arm_cpu_post_init(Object *obj); + uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) @@ -2944,102 +2946,40 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. */ -#define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 -#define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) -#define ARM_TBFLAG_MMUIDX_SHIFT 28 -#define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) -#define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 -#define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) -#define ARM_TBFLAG_PSTATE_SS_SHIFT 26 -#define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) +FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) +FIELD(TBFLAG_ANY, MMUIDX, 28, 3) +FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) +FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Target EL if we take a floating-point-disabled exception */ -#define ARM_TBFLAG_FPEXC_EL_SHIFT 24 -#define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) +FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) +FIELD(TBFLAG_ANY, BE_DATA, 23, 1) /* Bit usage when in AArch32 state: */ -#define ARM_TBFLAG_THUMB_SHIFT 0 -#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) -#define ARM_TBFLAG_VECLEN_SHIFT 1 -#define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) -#define ARM_TBFLAG_VECSTRIDE_SHIFT 4 -#define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) -#define ARM_TBFLAG_VFPEN_SHIFT 7 -#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) -#define ARM_TBFLAG_CONDEXEC_SHIFT 8 -#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) -#define ARM_TBFLAG_SCTLR_B_SHIFT 16 -#define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) +FIELD(TBFLAG_A32, THUMB, 0, 1) +FIELD(TBFLAG_A32, VECLEN, 1, 3) +FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) +FIELD(TBFLAG_A32, VFPEN, 7, 1) +FIELD(TBFLAG_A32, CONDEXEC, 8, 8) +FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime */ -#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 -#define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) +FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2) /* Indicates whether cp register reads and writes by guest code should access * the secure or nonsecure bank of banked registers; note that this is not * the same thing as the current security state of the processor! */ -#define ARM_TBFLAG_NS_SHIFT 19 -#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) -#define ARM_TBFLAG_BE_DATA_SHIFT 20 -#define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) +FIELD(TBFLAG_A32, NS, 19, 1) /* For M profile only, Handler (ie not Thread) mode */ -#define ARM_TBFLAG_HANDLER_SHIFT 21 -#define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT) +FIELD(TBFLAG_A32, HANDLER, 21, 1) /* For M profile only, whether we should generate stack-limit checks */ -#define ARM_TBFLAG_STACKCHECK_SHIFT 22 -#define ARM_TBFLAG_STACKCHECK_MASK (1 << ARM_TBFLAG_STACKCHECK_SHIFT) +FIELD(TBFLAG_A32, STACKCHECK, 22, 1) /* Bit usage when in AArch64 state */ -#define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */ -#define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) -#define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ -#define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) -#define ARM_TBFLAG_SVEEXC_EL_SHIFT 2 -#define ARM_TBFLAG_SVEEXC_EL_MASK (0x3 << ARM_TBFLAG_SVEEXC_EL_SHIFT) -#define ARM_TBFLAG_ZCR_LEN_SHIFT 4 -#define ARM_TBFLAG_ZCR_LEN_MASK (0xf << ARM_TBFLAG_ZCR_LEN_SHIFT) - -/* some convenience accessor macros */ -#define ARM_TBFLAG_AARCH64_STATE(F) \ - (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) -#define ARM_TBFLAG_MMUIDX(F) \ - (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) -#define ARM_TBFLAG_SS_ACTIVE(F) \ - (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) -#define ARM_TBFLAG_PSTATE_SS(F) \ - (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) -#define ARM_TBFLAG_FPEXC_EL(F) \ - (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) -#define ARM_TBFLAG_THUMB(F) \ - (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) -#define ARM_TBFLAG_VECLEN(F) \ - (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) -#define ARM_TBFLAG_VECSTRIDE(F) \ - (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) -#define ARM_TBFLAG_VFPEN(F) \ - (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) -#define ARM_TBFLAG_CONDEXEC(F) \ - (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) -#define ARM_TBFLAG_SCTLR_B(F) \ - (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) -#define ARM_TBFLAG_XSCALE_CPAR(F) \ - (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) -#define ARM_TBFLAG_NS(F) \ - (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) -#define ARM_TBFLAG_BE_DATA(F) \ - (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) -#define ARM_TBFLAG_HANDLER(F) \ - (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT) -#define ARM_TBFLAG_STACKCHECK(F) \ - (((F) & ARM_TBFLAG_STACKCHECK_MASK) >> ARM_TBFLAG_STACKCHECK_SHIFT) -#define ARM_TBFLAG_TBI0(F) \ - (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) -#define ARM_TBFLAG_TBI1(F) \ - (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) -#define ARM_TBFLAG_SVEEXC_EL(F) \ - (((F) & ARM_TBFLAG_SVEEXC_EL_MASK) >> ARM_TBFLAG_SVEEXC_EL_SHIFT) -#define ARM_TBFLAG_ZCR_LEN(F) \ - (((F) & ARM_TBFLAG_ZCR_LEN_MASK) >> ARM_TBFLAG_ZCR_LEN_SHIFT) +FIELD(TBFLAG_A64, TBI0, 0, 1) +FIELD(TBFLAG_A64, TBI1, 1, 1) +FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) +FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1d57be0c91..4b544a1c58 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -364,11 +364,11 @@ static void aarch64_max_initfn(Object *obj) } } -typedef struct ARMCPUInfo { +struct ARMCPUInfo { const char *name; void (*initfn)(Object *obj); void (*class_init)(ObjectClass *oc, void *data); -} ARMCPUInfo; +}; static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, @@ -452,14 +452,30 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_arch_name = aarch64_gdb_arch_name; } +static void aarch64_cpu_instance_init(Object *obj) +{ + ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); + + acc->info->initfn(obj); + arm_cpu_post_init(obj); +} + +static void cpu_register_class_init(ObjectClass *oc, void *data) +{ + ARMCPUClass *acc = ARM_CPU_CLASS(oc); + + acc->info = data; +} + static void aarch64_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info = { .parent = TYPE_AARCH64_CPU, .instance_size = sizeof(ARMCPU), - .instance_init = info->initfn, + .instance_init = aarch64_cpu_instance_init, .class_size = sizeof(ARMCPUClass), - .class_init = info->class_init, + .class_init = info->class_init ?: cpu_register_class_init, + .class_data = (void *)info, }; type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); diff --git a/target/arm/helper.c b/target/arm/helper.c index 644599b29d..f00c141ef9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12955,16 +12955,18 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); int current_el = arm_current_el(env); int fp_el = fp_exception_el(env, current_el); - uint32_t flags; + uint32_t flags = 0; if (is_a64(env)) { ARMCPU *cpu = arm_env_get_cpu(env); *pc = env->pc; - flags = ARM_TBFLAG_AARCH64_STATE_MASK; + flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); /* Get control bits for tagged addresses */ - flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); - flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); + flags = FIELD_DP32(flags, TBFLAG_A64, TBI0, + arm_regime_tbi0(env, mmu_idx)); + flags = FIELD_DP32(flags, TBFLAG_A64, TBI1, + arm_regime_tbi1(env, mmu_idx)); if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el = sve_exception_el(env, current_el); @@ -12978,28 +12980,25 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } else { zcr_len = sve_zcr_len_for_el(env, current_el); } - flags |= sve_el << ARM_TBFLAG_SVEEXC_EL_SHIFT; - flags |= zcr_len << ARM_TBFLAG_ZCR_LEN_SHIFT; + flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); + flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } } else { *pc = env->regs[15]; - flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) - | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) - | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) - | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) - | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); - if (!(access_secure_reg(env))) { - flags |= ARM_TBFLAG_NS_MASK; - } + flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); + flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); + flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); + flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); + flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); + flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1)) { - flags |= ARM_TBFLAG_VFPEN_MASK; + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); } - flags |= (extract32(env->cp15.c15_cpar, 0, 2) - << ARM_TBFLAG_XSCALE_CPAR_SHIFT); + flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); } - flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); + flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: @@ -13009,24 +13008,24 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * 1 1 Active-not-pending */ if (arm_singlestep_active(env)) { - flags |= ARM_TBFLAG_SS_ACTIVE_MASK; + flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); if (is_a64(env)) { if (env->pstate & PSTATE_SS) { - flags |= ARM_TBFLAG_PSTATE_SS_MASK; + flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); } } else { if (env->uncached_cpsr & PSTATE_SS) { - flags |= ARM_TBFLAG_PSTATE_SS_MASK; + flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); } } } if (arm_cpu_data_is_big_endian(env)) { - flags |= ARM_TBFLAG_BE_DATA_MASK; + flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); } - flags |= fp_el << ARM_TBFLAG_FPEXC_EL_SHIFT; + flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); if (arm_v7m_is_handler_mode(env)) { - flags |= ARM_TBFLAG_HANDLER_MASK; + flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); } /* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is @@ -13036,7 +13035,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, arm_feature(env, ARM_FEATURE_M) && !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { - flags |= ARM_TBFLAG_STACKCHECK_MASK; + flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); } *pflags = flags; diff --git a/target/arm/sve.decode b/target/arm/sve.decode index e10b689454..4f580a25e7 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -99,6 +99,7 @@ # Two operand with governing predicate, flags setting @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s +@pd_pg_pn_s0 ........ . . ...... .. pg:4 . rn:4 . rd:4 &rpr_s s=0 # Three operand with unused vector element size @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 @@ -667,8 +668,8 @@ BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s # SVE partition break condition BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s -BRKA_m 00100101 0. 01000001 .... 0 .... 1 .... @pd_pg_pn_s -BRKB_m 00100101 1. 01000001 .... 0 .... 1 .... @pd_pg_pn_s +BRKA_m 00100101 00 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 +BRKB_m 00100101 10 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 # SVE propagate break to next partition BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e1da1e4d6f..b7b6ab6371 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13380,7 +13380,8 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; ARMCPU *arm_cpu = arm_env_get_cpu(env); - int bound; + uint32_t tb_flags = dc->base.tb->flags; + int bound, core_mmu_idx; dc->isar = &arm_cpu->isar; dc->pc = dc->base.pc_first; @@ -13394,19 +13395,20 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, !arm_el_is_aa64(env, 3); dc->thumb = 0; dc->sctlr_b = 0; - dc->be_data = ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; + dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; dc->condexec_mask = 0; dc->condexec_cond = 0; - dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb->flags)); - dc->tbi0 = ARM_TBFLAG_TBI0(dc->base.tb->flags); - dc->tbi1 = ARM_TBFLAG_TBI1(dc->base.tb->flags); + core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); + dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx); + dc->tbi0 = FIELD_EX32(tb_flags, TBFLAG_A64, TBI0); + dc->tbi1 = FIELD_EX32(tb_flags, TBFLAG_A64, TBI1); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user = (dc->current_el == 0); #endif - dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); - dc->sve_excp_el = ARM_TBFLAG_SVEEXC_EL(dc->base.tb->flags); - dc->sve_len = (ARM_TBFLAG_ZCR_LEN(dc->base.tb->flags) + 1) * 16; + dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); + dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); + dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; @@ -13427,8 +13429,8 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, * emit code to generate a software step exception * end the TB */ - dc->ss_active = ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); - dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); + dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); + dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); dc->is_ldex = false; dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); diff --git a/target/arm/translate.c b/target/arm/translate.c index 7c4675ffd8..66cf28c8cb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9733,6 +9733,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) rd = (insn >> 12) & 0xf; if (insn & (1 << 23)) { /* load/store exclusive */ + bool is_ld = extract32(insn, 20, 1); + bool is_lasr = !extract32(insn, 8, 1); int op2 = (insn >> 8) & 3; op1 = (insn >> 21) & 0x3; @@ -9760,11 +9762,12 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) addr = tcg_temp_local_new_i32(); load_reg_var(s, addr, rn); - /* Since the emulation does not have barriers, - the acquire/release semantics need no special - handling */ + if (is_lasr && !is_ld) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + if (op2 == 0) { - if (insn & (1 << 20)) { + if (is_ld) { tmp = tcg_temp_new_i32(); switch (op1) { case 0: /* lda */ @@ -9810,7 +9813,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } tcg_temp_free_i32(tmp); } - } else if (insn & (1 << 20)) { + } else if (is_ld) { switch (op1) { case 0: /* ldrex */ gen_load_exclusive(s, rd, 15, addr, 2); @@ -9847,6 +9850,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } } tcg_temp_free_i32(addr); + + if (is_lasr && is_ld) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } } else if ((insn & 0x00300f00) == 0) { /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx * - SWP, SWPB @@ -10862,6 +10869,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_gen_addi_i32(tmp, tmp, s->pc); store_reg(s, 15, tmp); } else { + bool is_lasr = false; + bool is_ld = extract32(insn, 20, 1); int op2 = (insn >> 6) & 0x3; op = (insn >> 4) & 0x3; switch (op2) { @@ -10883,12 +10892,18 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 3: /* Load-acquire/store-release exclusive */ ARCH(8); + is_lasr = true; break; } + + if (is_lasr && !is_ld) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + addr = tcg_temp_local_new_i32(); load_reg_var(s, addr, rn); if (!(op2 & 1)) { - if (insn & (1 << 20)) { + if (is_ld) { tmp = tcg_temp_new_i32(); switch (op) { case 0: /* ldab */ @@ -10927,12 +10942,16 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } tcg_temp_free_i32(tmp); } - } else if (insn & (1 << 20)) { + } else if (is_ld) { gen_load_exclusive(s, rs, rd, addr, op); } else { gen_store_exclusive(s, rm, rs, rd, addr, op); } tcg_temp_free_i32(addr); + + if (is_lasr && is_ld) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } } } else { /* Load/store multiple, RFE, SRS. */ @@ -13021,6 +13040,8 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cs->env_ptr; ARMCPU *cpu = arm_env_get_cpu(env); + uint32_t tb_flags = dc->base.tb->flags; + uint32_t condexec, core_mmu_idx; dc->isar = &cpu->isar; dc->pc = dc->base.pc_first; @@ -13032,26 +13053,28 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) */ dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb = ARM_TBFLAG_THUMB(dc->base.tb->flags); - dc->sctlr_b = ARM_TBFLAG_SCTLR_B(dc->base.tb->flags); - dc->be_data = ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; - dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) & 0xf) << 1; - dc->condexec_cond = ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) >> 4; - dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb->flags)); + dc->thumb = FIELD_EX32(tb_flags, TBFLAG_A32, THUMB); + dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B); + dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE; + condexec = FIELD_EX32(tb_flags, TBFLAG_A32, CONDEXEC); + dc->condexec_mask = (condexec & 0xf) << 1; + dc->condexec_cond = condexec >> 4; + core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); + dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx); dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user = (dc->current_el == 0); #endif - dc->ns = ARM_TBFLAG_NS(dc->base.tb->flags); - dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); - dc->vfp_enabled = ARM_TBFLAG_VFPEN(dc->base.tb->flags); - dc->vec_len = ARM_TBFLAG_VECLEN(dc->base.tb->flags); - dc->vec_stride = ARM_TBFLAG_VECSTRIDE(dc->base.tb->flags); - dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(dc->base.tb->flags); - dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(dc->base.tb->flags); + dc->ns = FIELD_EX32(tb_flags, TBFLAG_A32, NS); + dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); + dc->vfp_enabled = FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); + dc->vec_len = FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN); + dc->vec_stride = FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE); + dc->c15_cpar = FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR); + dc->v7m_handler_mode = FIELD_EX32(tb_flags, TBFLAG_A32, HANDLER); dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) && regime_is_secure(env, dc->mmu_idx); - dc->v8m_stackcheck = ARM_TBFLAG_STACKCHECK(dc->base.tb->flags); + dc->v8m_stackcheck = FIELD_EX32(tb_flags, TBFLAG_A32, STACKCHECK); dc->cp_regs = cpu->cp_regs; dc->features = env->features; @@ -13070,8 +13093,8 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) * emit code to generate a software step exception * end the TB */ - dc->ss_active = ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); - dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); + dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE); + dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS); dc->is_ldex = false; dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */ @@ -13516,11 +13539,11 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) DisasContext dc; const TranslatorOps *ops = &arm_translator_ops; - if (ARM_TBFLAG_THUMB(tb->flags)) { + if (FIELD_EX32(tb->flags, TBFLAG_A32, THUMB)) { ops = &thumb_translator_ops; } #ifdef TARGET_AARCH64 - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + if (FIELD_EX32(tb->flags, TBFLAG_ANY, AARCH64_STATE)) { ops = &aarch64_translator_ops; } #endif diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 677a3bd5fb..fa37203d89 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3568,7 +3568,6 @@ static void x86_cpu_parse_featurestr(const char *typename, char *features, prop->driver = typename; prop->property = g_strdup(name); prop->value = g_strdup(val); - prop->errp = &error_fatal; qdev_prop_register_global(prop); } diff --git a/target/ppc/arch_dump.c b/target/ppc/arch_dump.c index cc1460e4e3..3a00606d01 100644 --- a/target/ppc/arch_dump.c +++ b/target/ppc/arch_dump.c @@ -140,7 +140,8 @@ static void ppc_write_elf_fpregset(NoteFuncArg *arg, PowerPCCPU *cpu) memset(fpregset, 0, sizeof(*fpregset)); for (i = 0; i < 32; i++) { - fpregset->fpr[i] = cpu_to_dump64(s, cpu->env.fpr[i]); + uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); + fpregset->fpr[i] = cpu_to_dump64(s, *fpr); } fpregset->fpscr = cpu_to_dump_reg(s, cpu->env.fpscr); } @@ -158,6 +159,7 @@ static void ppc_write_elf_vmxregset(NoteFuncArg *arg, PowerPCCPU *cpu) for (i = 0; i < 32; i++) { bool needs_byteswap; + ppc_avr_t *avr = cpu_avr_ptr(&cpu->env, i); #ifdef HOST_WORDS_BIGENDIAN needs_byteswap = s->dump_info.d_endian == ELFDATA2LSB; @@ -166,11 +168,11 @@ static void ppc_write_elf_vmxregset(NoteFuncArg *arg, PowerPCCPU *cpu) #endif if (needs_byteswap) { - vmxregset->avr[i].u64[0] = bswap64(cpu->env.avr[i].u64[1]); - vmxregset->avr[i].u64[1] = bswap64(cpu->env.avr[i].u64[0]); + vmxregset->avr[i].u64[0] = bswap64(avr->u64[1]); + vmxregset->avr[i].u64[1] = bswap64(avr->u64[0]); } else { - vmxregset->avr[i].u64[0] = cpu->env.avr[i].u64[0]; - vmxregset->avr[i].u64[1] = cpu->env.avr[i].u64[1]; + vmxregset->avr[i].u64[0] = avr->u64[0]; + vmxregset->avr[i].u64[1] = avr->u64[1]; } } vmxregset->vscr.u32[3] = cpu_to_dump32(s, cpu->env.vscr); @@ -188,7 +190,8 @@ static void ppc_write_elf_vsxregset(NoteFuncArg *arg, PowerPCCPU *cpu) memset(vsxregset, 0, sizeof(*vsxregset)); for (i = 0; i < 32; i++) { - vsxregset->vsr[i] = cpu_to_dump64(s, cpu->env.vsr[i]); + uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); + vsxregset->vsr[i] = cpu_to_dump64(s, *vsrl); } } diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index d5f99f1fc7..486abaf99b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -218,7 +218,6 @@ typedef struct opc_handler_t opc_handler_t; /* Types used to describe some PowerPC registers etc. */ typedef struct DisasContext DisasContext; typedef struct ppc_spr_t ppc_spr_t; -typedef union ppc_avr_t ppc_avr_t; typedef union ppc_tlb_t ppc_tlb_t; typedef struct ppc_hash_pte64 ppc_hash_pte64_t; @@ -242,22 +241,26 @@ struct ppc_spr_t { #endif }; -/* Altivec registers (128 bits) */ -union ppc_avr_t { - float32 f[4]; +/* VSX/Altivec registers (128 bits) */ +typedef union _ppc_vsr_t { uint8_t u8[16]; uint16_t u16[8]; uint32_t u32[4]; + uint64_t u64[2]; int8_t s8[16]; int16_t s16[8]; int32_t s32[4]; - uint64_t u64[2]; int64_t s64[2]; + float32 f32[4]; + float64 f64[2]; + float128 f128; #ifdef CONFIG_INT128 __uint128_t u128; #endif - Int128 s128; -}; + Int128 s128; +} ppc_vsr_t; + +typedef ppc_vsr_t ppc_avr_t; #if !defined(CONFIG_USER_ONLY) /* Software TLB cache */ @@ -1001,8 +1004,6 @@ struct CPUPPCState { /* Floating point execution context */ float_status fp_status; - /* floating point registers */ - float64 fpr[32]; /* floating point status and control register */ target_ulong fpscr; @@ -1052,11 +1053,10 @@ struct CPUPPCState { /* Special purpose registers */ target_ulong spr[1024]; ppc_spr_t spr_cb[1024]; - /* Altivec registers */ - ppc_avr_t avr[32]; + /* Vector status and control register */ uint32_t vscr; - /* VSX registers */ - uint64_t vsr[32]; + /* VSX registers (including FP and AVR) */ + ppc_vsr_t vsr[64] QEMU_ALIGNED(16); /* SPE registers */ uint64_t spe_acc; uint32_t spe_fscr; @@ -1177,6 +1177,8 @@ do { \ typedef struct PPCVirtualHypervisor PPCVirtualHypervisor; typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass; +typedef struct XiveTCTX XiveTCTX; +typedef struct ICPState ICPState; /** * PowerPCCPU: @@ -1195,7 +1197,8 @@ struct PowerPCCPU { int vcpu_id; uint32_t compat_pvr; PPCVirtualHypervisor *vhyp; - Object *intc; + ICPState *icp; + XiveTCTX *tctx; void *machine_data; int32_t node_id; /* NUMA node this CPU belongs to */ PPCHash64Options *hash64_opts; @@ -2537,6 +2540,22 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx) (start + nregs > 32 && (rx >= start || rx < start + nregs - 32)); } +/* Accessors for FP, VMX and VSX registers */ +static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) +{ + return &env->vsr[i].u64[0]; +} + +static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i) +{ + return &env->vsr[i].u64[1]; +} + +static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i) +{ + return &env->vsr[32 + i]; +} + void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env); void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len); diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index b6f6693583..19565b584d 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -126,7 +126,7 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) gdb_get_regl(mem_buf, env->gpr[n]); } else if (n < 64) { /* fprs */ - stfq_p(mem_buf, env->fpr[n-32]); + stfq_p(mem_buf, *cpu_fpr_ptr(env, n - 32)); } else { switch (n) { case 64: @@ -178,7 +178,7 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t *mem_buf, int n) gdb_get_reg64(mem_buf, env->gpr[n]); } else if (n < 64) { /* fprs */ - stfq_p(mem_buf, env->fpr[n-32]); + stfq_p(mem_buf, *cpu_fpr_ptr(env, n - 32)); } else if (n < 96) { /* Altivec */ stq_p(mem_buf, n - 64); @@ -234,7 +234,7 @@ int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->gpr[n] = ldtul_p(mem_buf); } else if (n < 64) { /* fprs */ - env->fpr[n-32] = ldfq_p(mem_buf); + *cpu_fpr_ptr(env, n - 32) = ldfq_p(mem_buf); } else { switch (n) { case 64: @@ -284,7 +284,7 @@ int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n) env->gpr[n] = ldq_p(mem_buf); } else if (n < 64) { /* fprs */ - env->fpr[n-32] = ldfq_p(mem_buf); + *cpu_fpr_ptr(env, n - 32) = ldfq_p(mem_buf); } else { switch (n) { case 64 + 32: diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index fcac90a4a9..598731d47a 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -391,13 +391,9 @@ target_ulong helper_602_mfrom(target_ulong arg) #if defined(HOST_WORDS_BIGENDIAN) #define HI_IDX 0 #define LO_IDX 1 -#define AVRB(i) u8[i] -#define AVRW(i) u32[i] #else #define HI_IDX 1 #define LO_IDX 0 -#define AVRB(i) u8[15-(i)] -#define AVRW(i) u32[3-(i)] #endif #if defined(HOST_WORDS_BIGENDIAN) @@ -548,8 +544,8 @@ VARITH_DO(muluwm, *, u32) { \ int i; \ \ - for (i = 0; i < ARRAY_SIZE(r->f); i++) { \ - r->f[i] = func(a->f[i], b->f[i], &env->vec_status); \ + for (i = 0; i < ARRAY_SIZE(r->f32); i++) { \ + r->f32[i] = func(a->f32[i], b->f32[i], &env->vec_status); \ } \ } VARITHFP(addfp, float32_add) @@ -563,9 +559,9 @@ VARITHFP(maxfp, float32_max) ppc_avr_t *b, ppc_avr_t *c) \ { \ int i; \ - for (i = 0; i < ARRAY_SIZE(r->f); i++) { \ - r->f[i] = float32_muladd(a->f[i], c->f[i], b->f[i], \ - type, &env->vec_status); \ + for (i = 0; i < ARRAY_SIZE(r->f32); i++) { \ + r->f32[i] = float32_muladd(a->f32[i], c->f32[i], b->f32[i], \ + type, &env->vec_status); \ } \ } VARITHFPFMA(maddfp, 0); @@ -670,9 +666,9 @@ VABSDU(w, u32) { \ int i; \ \ - for (i = 0; i < ARRAY_SIZE(r->f); i++) { \ + for (i = 0; i < ARRAY_SIZE(r->f32); i++) { \ float32 t = cvt(b->element[i], &env->vec_status); \ - r->f[i] = float32_scalbn(t, -uim, &env->vec_status); \ + r->f32[i] = float32_scalbn(t, -uim, &env->vec_status); \ } \ } VCF(ux, uint32_to_float32, u32) @@ -782,9 +778,9 @@ VCMPNE(w, u32, uint32_t, 0) uint32_t none = 0; \ int i; \ \ - for (i = 0; i < ARRAY_SIZE(r->f); i++) { \ + for (i = 0; i < ARRAY_SIZE(r->f32); i++) { \ uint32_t result; \ - int rel = float32_compare_quiet(a->f[i], b->f[i], \ + int rel = float32_compare_quiet(a->f32[i], b->f32[i], \ &env->vec_status); \ if (rel == float_relation_unordered) { \ result = 0; \ @@ -816,14 +812,16 @@ static inline void vcmpbfp_internal(CPUPPCState *env, ppc_avr_t *r, int i; int all_in = 0; - for (i = 0; i < ARRAY_SIZE(r->f); i++) { - int le_rel = float32_compare_quiet(a->f[i], b->f[i], &env->vec_status); + for (i = 0; i < ARRAY_SIZE(r->f32); i++) { + int le_rel = float32_compare_quiet(a->f32[i], b->f32[i], + &env->vec_status); if (le_rel == float_relation_unordered) { r->u32[i] = 0xc0000000; all_in = 1; } else { - float32 bneg = float32_chs(b->f[i]); - int ge_rel = float32_compare_quiet(a->f[i], bneg, &env->vec_status); + float32 bneg = float32_chs(b->f32[i]); + int ge_rel = float32_compare_quiet(a->f32[i], bneg, + &env->vec_status); int le = le_rel != float_relation_greater; int ge = ge_rel != float_relation_less; @@ -856,11 +854,11 @@ void helper_vcmpbfp_dot(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, float_status s = env->vec_status; \ \ set_float_rounding_mode(float_round_to_zero, &s); \ - for (i = 0; i < ARRAY_SIZE(r->f); i++) { \ - if (float32_is_any_nan(b->f[i])) { \ + for (i = 0; i < ARRAY_SIZE(r->f32); i++) { \ + if (float32_is_any_nan(b->f32[i])) { \ r->element[i] = 0; \ } else { \ - float64 t = float32_to_float64(b->f[i], &s); \ + float64 t = float32_to_float64(b->f32[i], &s); \ int64_t j; \ \ t = float64_scalbn(t, uim, &s); \ @@ -1661,8 +1659,8 @@ void helper_vrefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b) { int i; - for (i = 0; i < ARRAY_SIZE(r->f); i++) { - r->f[i] = float32_div(float32_one, b->f[i], &env->vec_status); + for (i = 0; i < ARRAY_SIZE(r->f32); i++) { + r->f32[i] = float32_div(float32_one, b->f32[i], &env->vec_status); } } @@ -1674,8 +1672,8 @@ void helper_vrefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b) float_status s = env->vec_status; \ \ set_float_rounding_mode(rounding, &s); \ - for (i = 0; i < ARRAY_SIZE(r->f); i++) { \ - r->f[i] = float32_round_to_int (b->f[i], &s); \ + for (i = 0; i < ARRAY_SIZE(r->f32); i++) { \ + r->f32[i] = float32_round_to_int (b->f32[i], &s); \ } \ } VRFI(n, float_round_nearest_even) @@ -1705,10 +1703,10 @@ void helper_vrsqrtefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b) { int i; - for (i = 0; i < ARRAY_SIZE(r->f); i++) { - float32 t = float32_sqrt(b->f[i], &env->vec_status); + for (i = 0; i < ARRAY_SIZE(r->f32); i++) { + float32 t = float32_sqrt(b->f32[i], &env->vec_status); - r->f[i] = float32_div(float32_one, t, &env->vec_status); + r->f32[i] = float32_div(float32_one, t, &env->vec_status); } } @@ -1751,8 +1749,8 @@ void helper_vexptefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b) { int i; - for (i = 0; i < ARRAY_SIZE(r->f); i++) { - r->f[i] = float32_exp2(b->f[i], &env->vec_status); + for (i = 0; i < ARRAY_SIZE(r->f32); i++) { + r->f32[i] = float32_exp2(b->f32[i], &env->vec_status); } } @@ -1760,8 +1758,8 @@ void helper_vlogefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b) { int i; - for (i = 0; i < ARRAY_SIZE(r->f); i++) { - r->f[i] = float32_log2(b->f[i], &env->vec_status); + for (i = 0; i < ARRAY_SIZE(r->f32); i++) { + r->f32[i] = float32_log2(b->f32[i], &env->vec_status); } } @@ -3275,11 +3273,11 @@ void helper_vcipher(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) int i; VECTOR_FOR_INORDER_I(i, u32) { - result.AVRW(i) = b->AVRW(i) ^ - (AES_Te0[a->AVRB(AES_shifts[4*i + 0])] ^ - AES_Te1[a->AVRB(AES_shifts[4*i + 1])] ^ - AES_Te2[a->AVRB(AES_shifts[4*i + 2])] ^ - AES_Te3[a->AVRB(AES_shifts[4*i + 3])]); + result.VsrW(i) = b->VsrW(i) ^ + (AES_Te0[a->VsrB(AES_shifts[4 * i + 0])] ^ + AES_Te1[a->VsrB(AES_shifts[4 * i + 1])] ^ + AES_Te2[a->VsrB(AES_shifts[4 * i + 2])] ^ + AES_Te3[a->VsrB(AES_shifts[4 * i + 3])]); } *r = result; } @@ -3290,7 +3288,7 @@ void helper_vcipherlast(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) int i; VECTOR_FOR_INORDER_I(i, u8) { - result.AVRB(i) = b->AVRB(i) ^ (AES_sbox[a->AVRB(AES_shifts[i])]); + result.VsrB(i) = b->VsrB(i) ^ (AES_sbox[a->VsrB(AES_shifts[i])]); } *r = result; } @@ -3303,15 +3301,15 @@ void helper_vncipher(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) ppc_avr_t tmp; VECTOR_FOR_INORDER_I(i, u8) { - tmp.AVRB(i) = b->AVRB(i) ^ AES_isbox[a->AVRB(AES_ishifts[i])]; + tmp.VsrB(i) = b->VsrB(i) ^ AES_isbox[a->VsrB(AES_ishifts[i])]; } VECTOR_FOR_INORDER_I(i, u32) { - r->AVRW(i) = - AES_imc[tmp.AVRB(4*i + 0)][0] ^ - AES_imc[tmp.AVRB(4*i + 1)][1] ^ - AES_imc[tmp.AVRB(4*i + 2)][2] ^ - AES_imc[tmp.AVRB(4*i + 3)][3]; + r->VsrW(i) = + AES_imc[tmp.VsrB(4 * i + 0)][0] ^ + AES_imc[tmp.VsrB(4 * i + 1)][1] ^ + AES_imc[tmp.VsrB(4 * i + 2)][2] ^ + AES_imc[tmp.VsrB(4 * i + 3)][3]; } } @@ -3321,7 +3319,7 @@ void helper_vncipherlast(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) int i; VECTOR_FOR_INORDER_I(i, u8) { - result.AVRB(i) = b->AVRB(i) ^ (AES_isbox[a->AVRB(AES_ishifts[i])]); + result.VsrB(i) = b->VsrB(i) ^ (AES_isbox[a->VsrB(AES_ishifts[i])]); } *r = result; } diff --git a/target/ppc/internal.h b/target/ppc/internal.h index a9bcadff42..c7c0f77dd6 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -52,20 +52,20 @@ FUNC_MASK(mask_u64, uint64_t, 64, UINT64_MAX); #define EXTRACT_HELPER(name, shift, nb) \ static inline uint32_t name(uint32_t opcode) \ { \ - return (opcode >> (shift)) & ((1 << (nb)) - 1); \ + return extract32(opcode, shift, nb); \ } #define EXTRACT_SHELPER(name, shift, nb) \ static inline int32_t name(uint32_t opcode) \ { \ - return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ + return sextract32(opcode, shift, nb); \ } #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \ static inline uint32_t name(uint32_t opcode) \ { \ - return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \ - ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \ + return extract32(opcode, shift1, nb1) << nb2 | \ + extract32(opcode, shift2, nb2); \ } #define EXTRACT_HELPER_SPLIT_3(name, \ @@ -124,7 +124,7 @@ EXTRACT_SHELPER(SIMM, 0, 16); /* 16 bits unsigned immediate value */ EXTRACT_HELPER(UIMM, 0, 16); /* 5 bits signed immediate value */ -EXTRACT_HELPER(SIMM5, 16, 5); +EXTRACT_SHELPER(SIMM5, 16, 5); /* 5 bits signed immediate value */ EXTRACT_HELPER(UIMM5, 16, 5); /* 4 bits unsigned immediate value */ @@ -204,17 +204,6 @@ EXTRACT_HELPER(IMM8, 11, 8); EXTRACT_HELPER(DCMX, 16, 7); EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6); -typedef union _ppc_vsr_t { - uint8_t u8[16]; - uint16_t u16[8]; - uint32_t u32[4]; - uint64_t u64[2]; - float32 f32[4]; - float64 f64[2]; - float128 f128; - Int128 s128; -} ppc_vsr_t; - #if defined(HOST_WORDS_BIGENDIAN) #define VsrB(i) u8[i] #define VsrH(i) u16[i] @@ -229,24 +218,14 @@ typedef union _ppc_vsr_t { static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { - if (n < 32) { - vsr->VsrD(0) = env->fpr[n]; - vsr->VsrD(1) = env->vsr[n]; - } else { - vsr->u64[0] = env->avr[n - 32].u64[0]; - vsr->u64[1] = env->avr[n - 32].u64[1]; - } + vsr->VsrD(0) = env->vsr[n].u64[0]; + vsr->VsrD(1) = env->vsr[n].u64[1]; } static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { - if (n < 32) { - env->fpr[n] = vsr->VsrD(0); - env->vsr[n] = vsr->VsrD(1); - } else { - env->avr[n - 32].u64[0] = vsr->u64[0]; - env->avr[n - 32].u64[1] = vsr->u64[1]; - } + env->vsr[n].u64[0] = vsr->VsrD(0); + env->vsr[n].u64[1] = vsr->VsrD(1); } void helper_compute_fprf_float16(CPUPPCState *env, float16 arg); diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index f81327d6cd..ebbb48c42f 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -629,13 +629,15 @@ static int kvm_put_fp(CPUState *cs) for (i = 0; i < 32; i++) { uint64_t vsr[2]; + uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); + uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); #ifdef HOST_WORDS_BIGENDIAN - vsr[0] = float64_val(env->fpr[i]); - vsr[1] = env->vsr[i]; + vsr[0] = float64_val(*fpr); + vsr[1] = *vsrl; #else - vsr[0] = env->vsr[i]; - vsr[1] = float64_val(env->fpr[i]); + vsr[0] = *vsrl; + vsr[1] = float64_val(*fpr); #endif reg.addr = (uintptr_t) &vsr; reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); @@ -660,7 +662,7 @@ static int kvm_put_fp(CPUState *cs) for (i = 0; i < 32; i++) { reg.id = KVM_REG_PPC_VR(i); - reg.addr = (uintptr_t)&env->avr[i]; + reg.addr = (uintptr_t)cpu_avr_ptr(env, i); ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); if (ret < 0) { DPRINTF("Unable to set VR%d to KVM: %s\n", i, strerror(errno)); @@ -696,6 +698,8 @@ static int kvm_get_fp(CPUState *cs) for (i = 0; i < 32; i++) { uint64_t vsr[2]; + uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i); + uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i); reg.addr = (uintptr_t) &vsr; reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); @@ -707,14 +711,14 @@ static int kvm_get_fp(CPUState *cs) return ret; } else { #ifdef HOST_WORDS_BIGENDIAN - env->fpr[i] = vsr[0]; + *fpr = vsr[0]; if (vsx) { - env->vsr[i] = vsr[1]; + *vsrl = vsr[1]; } #else - env->fpr[i] = vsr[1]; + *fpr = vsr[1]; if (vsx) { - env->vsr[i] = vsr[0]; + *vsrl = vsr[0]; } #endif } @@ -732,7 +736,7 @@ static int kvm_get_fp(CPUState *cs) for (i = 0; i < 32; i++) { reg.id = KVM_REG_PPC_VR(i); - reg.addr = (uintptr_t)&env->avr[i]; + reg.addr = (uintptr_t)cpu_avr_ptr(env, i); ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); if (ret < 0) { DPRINTF("Unable to get VR%d from KVM: %s\n", diff --git a/target/ppc/machine.c b/target/ppc/machine.c index e7b3725273..eff30053b0 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -45,7 +45,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) uint64_t l; } u; u.l = qemu_get_be64(f); - env->fpr[i] = u.d; + *cpu_fpr_ptr(env, i) = u.d; } qemu_get_be32s(f, &fpscr); env->fpscr = fpscr; @@ -138,11 +138,73 @@ static const VMStateInfo vmstate_info_avr = { }; #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ - VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t) + VMSTATE_SUB_ARRAY(_f, _s, 32, _n, _v, vmstate_info_avr, ppc_avr_t) #define VMSTATE_AVR_ARRAY(_f, _s, _n) \ VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) +static int get_fpr(QEMUFile *f, void *pv, size_t size, + const VMStateField *field) +{ + ppc_vsr_t *v = pv; + + v->u64[0] = qemu_get_be64(f); + + return 0; +} + +static int put_fpr(QEMUFile *f, void *pv, size_t size, + const VMStateField *field, QJSON *vmdesc) +{ + ppc_vsr_t *v = pv; + + qemu_put_be64(f, v->u64[0]); + return 0; +} + +static const VMStateInfo vmstate_info_fpr = { + .name = "fpr", + .get = get_fpr, + .put = put_fpr, +}; + +#define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \ + VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_fpr, ppc_vsr_t) + +#define VMSTATE_FPR_ARRAY(_f, _s, _n) \ + VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0) + +static int get_vsr(QEMUFile *f, void *pv, size_t size, + const VMStateField *field) +{ + ppc_vsr_t *v = pv; + + v->u64[1] = qemu_get_be64(f); + + return 0; +} + +static int put_vsr(QEMUFile *f, void *pv, size_t size, + const VMStateField *field, QJSON *vmdesc) +{ + ppc_vsr_t *v = pv; + + qemu_put_be64(f, v->u64[1]); + return 0; +} + +static const VMStateInfo vmstate_info_vsr = { + .name = "vsr", + .get = get_vsr, + .put = put_vsr, +}; + +#define VMSTATE_VSR_ARRAY_V(_f, _s, _n, _v) \ + VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_vsr, ppc_vsr_t) + +#define VMSTATE_VSR_ARRAY(_f, _s, _n) \ + VMSTATE_VSR_ARRAY_V(_f, _s, _n, 0) + static bool cpu_pre_2_8_migration(void *opaque, int version_id) { PowerPCCPU *cpu = opaque; @@ -354,7 +416,7 @@ static const VMStateDescription vmstate_fpu = { .minimum_version_id = 1, .needed = fpu_needed, .fields = (VMStateField[]) { - VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32), + VMSTATE_FPR_ARRAY(env.vsr, PowerPCCPU, 32), VMSTATE_UINTTL(env.fpscr, PowerPCCPU), VMSTATE_END_OF_LIST() }, @@ -373,7 +435,7 @@ static const VMStateDescription vmstate_altivec = { .minimum_version_id = 1, .needed = altivec_needed, .fields = (VMStateField[]) { - VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32), + VMSTATE_AVR_ARRAY(env.vsr, PowerPCCPU, 32), VMSTATE_UINT32(env.vscr, PowerPCCPU), VMSTATE_END_OF_LIST() }, @@ -392,7 +454,7 @@ static const VMStateDescription vmstate_vsx = { .minimum_version_id = 1, .needed = vsx_needed, .fields = (VMStateField[]) { - VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32), + VMSTATE_VSR_ARRAY(env.vsr, PowerPCCPU, 32), VMSTATE_END_OF_LIST() }, }; diff --git a/target/ppc/monitor.c b/target/ppc/monitor.c index 14915119fc..04deec8030 100644 --- a/target/ppc/monitor.c +++ b/target/ppc/monitor.c @@ -123,8 +123,8 @@ int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval) /* Floating point registers */ if ((qemu_tolower(name[0]) == 'f') && - ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->fpr), ®num)) { - *pval = env->fpr[regnum]; + ppc_cpu_get_reg_num(name + 1, 32, ®num)) { + *pval = *cpu_fpr_ptr(env, regnum); return 0; } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 96894ab9a8..e169c43643 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -55,15 +55,9 @@ /* global register indexes */ static char cpu_reg_names[10*3 + 22*4 /* GPR */ + 10*4 + 22*5 /* SPE GPRh */ - + 10*4 + 22*5 /* FPR */ - + 2*(10*6 + 22*7) /* AVRh, AVRl */ - + 10*5 + 22*6 /* VSR */ + 8*5 /* CRF */]; static TCGv cpu_gpr[32]; static TCGv cpu_gprh[32]; -static TCGv_i64 cpu_fpr[32]; -static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; -static TCGv_i64 cpu_vsr[32]; static TCGv_i32 cpu_crf[8]; static TCGv cpu_nip; static TCGv cpu_msr; @@ -108,39 +102,6 @@ void ppc_translate_init(void) offsetof(CPUPPCState, gprh[i]), p); p += (i < 10) ? 4 : 5; cpu_reg_names_size -= (i < 10) ? 4 : 5; - - snprintf(p, cpu_reg_names_size, "fp%d", i); - cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, fpr[i]), p); - p += (i < 10) ? 4 : 5; - cpu_reg_names_size -= (i < 10) ? 4 : 5; - - snprintf(p, cpu_reg_names_size, "avr%dH", i); -#ifdef HOST_WORDS_BIGENDIAN - cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, avr[i].u64[0]), p); -#else - cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, avr[i].u64[1]), p); -#endif - p += (i < 10) ? 6 : 7; - cpu_reg_names_size -= (i < 10) ? 6 : 7; - - snprintf(p, cpu_reg_names_size, "avr%dL", i); -#ifdef HOST_WORDS_BIGENDIAN - cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, avr[i].u64[1]), p); -#else - cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, avr[i].u64[0]), p); -#endif - p += (i < 10) ? 6 : 7; - cpu_reg_names_size -= (i < 10) ? 6 : 7; - snprintf(p, cpu_reg_names_size, "vsr%d", i); - cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env, - offsetof(CPUPPCState, vsr[i]), p); - p += (i < 10) ? 5 : 6; - cpu_reg_names_size -= (i < 10) ? 5 : 6; } cpu_nip = tcg_global_mem_new(cpu_env, @@ -6699,6 +6660,38 @@ static inline void gen_##name(DisasContext *ctx) \ GEN_TM_PRIV_NOOP(treclaim); GEN_TM_PRIV_NOOP(trechkpt); +static inline void get_fpr(TCGv_i64 dst, int regno) +{ + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0])); +} + +static inline void set_fpr(int regno, TCGv_i64 src) +{ + tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0])); +} + +static inline void get_avr64(TCGv_i64 dst, int regno, bool high) +{ +#ifdef HOST_WORDS_BIGENDIAN + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, + vsr[32 + regno].u64[(high ? 0 : 1)])); +#else + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, + vsr[32 + regno].u64[(high ? 1 : 0)])); +#endif +} + +static inline void set_avr64(int regno, TCGv_i64 src, bool high) +{ +#ifdef HOST_WORDS_BIGENDIAN + tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, + vsr[32 + regno].u64[(high ? 0 : 1)])); +#else + tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, + vsr[32 + regno].u64[(high ? 1 : 0)])); +#endif +} + #include "translate/fp-impl.inc.c" #include "translate/vmx-impl.inc.c" @@ -7447,7 +7440,7 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, if ((i & (RFPL - 1)) == 0) { cpu_fprintf(f, "FPR%02d", i); } - cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); + cpu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); if ((i & (RFPL - 1)) == (RFPL - 1)) { cpu_fprintf(f, "\n"); } diff --git a/target/ppc/translate/dfp-impl.inc.c b/target/ppc/translate/dfp-impl.inc.c index 634ef73b8a..6c556dc2e1 100644 --- a/target/ppc/translate/dfp-impl.inc.c +++ b/target/ppc/translate/dfp-impl.inc.c @@ -3,7 +3,7 @@ static inline TCGv_ptr gen_fprp_ptr(int reg) { TCGv_ptr r = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg])); + tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[reg].u64[0])); return r; } diff --git a/target/ppc/translate/fp-impl.inc.c b/target/ppc/translate/fp-impl.inc.c index 08770ba9f5..0f21a4e477 100644 --- a/target/ppc/translate/fp-impl.inc.c +++ b/target/ppc/translate/fp-impl.inc.c @@ -34,24 +34,37 @@ static void gen_set_cr1_from_fpscr(DisasContext *ctx) #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ static void gen_f##name(DisasContext *ctx) \ { \ + TCGv_i64 t0; \ + TCGv_i64 t1; \ + TCGv_i64 t2; \ + TCGv_i64 t3; \ if (unlikely(!ctx->fpu_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ + t2 = tcg_temp_new_i64(); \ + t3 = tcg_temp_new_i64(); \ gen_reset_fpstatus(); \ - gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ - cpu_fpr[rA(ctx->opcode)], \ - cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ + get_fpr(t0, rA(ctx->opcode)); \ + get_fpr(t1, rC(ctx->opcode)); \ + get_fpr(t2, rB(ctx->opcode)); \ + gen_helper_f##op(t3, cpu_env, t0, t1, t2); \ if (isfloat) { \ - gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ - cpu_fpr[rD(ctx->opcode)]); \ + gen_helper_frsp(t3, cpu_env, t3); \ } \ + set_fpr(rD(ctx->opcode), t3); \ if (set_fprf) { \ - gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); \ + gen_compute_fprf_float64(t3); \ } \ if (unlikely(Rc(ctx->opcode) != 0)) { \ gen_set_cr1_from_fpscr(ctx); \ } \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ + tcg_temp_free_i64(t2); \ + tcg_temp_free_i64(t3); \ } #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ @@ -61,24 +74,33 @@ _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ static void gen_f##name(DisasContext *ctx) \ { \ + TCGv_i64 t0; \ + TCGv_i64 t1; \ + TCGv_i64 t2; \ if (unlikely(!ctx->fpu_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ + t2 = tcg_temp_new_i64(); \ gen_reset_fpstatus(); \ - gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ - cpu_fpr[rA(ctx->opcode)], \ - cpu_fpr[rB(ctx->opcode)]); \ + get_fpr(t0, rA(ctx->opcode)); \ + get_fpr(t1, rB(ctx->opcode)); \ + gen_helper_f##op(t2, cpu_env, t0, t1); \ if (isfloat) { \ - gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ - cpu_fpr[rD(ctx->opcode)]); \ + gen_helper_frsp(t2, cpu_env, t2); \ } \ + set_fpr(rD(ctx->opcode), t2); \ if (set_fprf) { \ - gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); \ + gen_compute_fprf_float64(t2); \ } \ if (unlikely(Rc(ctx->opcode) != 0)) { \ gen_set_cr1_from_fpscr(ctx); \ } \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ + tcg_temp_free_i64(t2); \ } #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ @@ -87,24 +109,33 @@ _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ static void gen_f##name(DisasContext *ctx) \ { \ + TCGv_i64 t0; \ + TCGv_i64 t1; \ + TCGv_i64 t2; \ if (unlikely(!ctx->fpu_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ + t2 = tcg_temp_new_i64(); \ gen_reset_fpstatus(); \ - gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ - cpu_fpr[rA(ctx->opcode)], \ - cpu_fpr[rC(ctx->opcode)]); \ + get_fpr(t0, rA(ctx->opcode)); \ + get_fpr(t1, rC(ctx->opcode)); \ + gen_helper_f##op(t2, cpu_env, t0, t1); \ if (isfloat) { \ - gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ - cpu_fpr[rD(ctx->opcode)]); \ + gen_helper_frsp(t2, cpu_env, t2); \ } \ + set_fpr(rD(ctx->opcode), t2); \ if (set_fprf) { \ - gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); \ + gen_compute_fprf_float64(t2); \ } \ if (unlikely(Rc(ctx->opcode) != 0)) { \ gen_set_cr1_from_fpscr(ctx); \ } \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ + tcg_temp_free_i64(t2); \ } #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ @@ -113,37 +144,51 @@ _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ static void gen_f##name(DisasContext *ctx) \ { \ + TCGv_i64 t0; \ + TCGv_i64 t1; \ if (unlikely(!ctx->fpu_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ gen_reset_fpstatus(); \ - gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ - cpu_fpr[rB(ctx->opcode)]); \ + get_fpr(t0, rB(ctx->opcode)); \ + gen_helper_f##name(t1, cpu_env, t0); \ + set_fpr(rD(ctx->opcode), t1); \ if (set_fprf) { \ - gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); \ + gen_compute_fprf_float64(t1); \ } \ if (unlikely(Rc(ctx->opcode) != 0)) { \ gen_set_cr1_from_fpscr(ctx); \ } \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ } #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ static void gen_f##name(DisasContext *ctx) \ { \ + TCGv_i64 t0; \ + TCGv_i64 t1; \ if (unlikely(!ctx->fpu_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ gen_reset_fpstatus(); \ - gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ - cpu_fpr[rB(ctx->opcode)]); \ + get_fpr(t0, rB(ctx->opcode)); \ + gen_helper_f##name(t1, cpu_env, t0); \ + set_fpr(rD(ctx->opcode), t1); \ if (set_fprf) { \ - gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); \ + gen_compute_fprf_float64(t1); \ } \ if (unlikely(Rc(ctx->opcode) != 0)) { \ gen_set_cr1_from_fpscr(ctx); \ } \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ } /* fadd - fadds */ @@ -165,19 +210,25 @@ GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); /* frsqrtes */ static void gen_frsqrtes(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); gen_reset_fpstatus(); - gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env, - cpu_fpr[rB(ctx->opcode)]); - gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, - cpu_fpr[rD(ctx->opcode)]); - gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); + get_fpr(t0, rB(ctx->opcode)); + gen_helper_frsqrte(t1, cpu_env, t0); + gen_helper_frsp(t1, cpu_env, t1); + set_fpr(rD(ctx->opcode), t1); + gen_compute_fprf_float64(t1); if (unlikely(Rc(ctx->opcode) != 0)) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } /* fsel */ @@ -189,34 +240,47 @@ GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); /* fsqrt */ static void gen_fsqrt(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); gen_reset_fpstatus(); - gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, - cpu_fpr[rB(ctx->opcode)]); - gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); + get_fpr(t0, rB(ctx->opcode)); + gen_helper_fsqrt(t1, cpu_env, t0); + set_fpr(rD(ctx->opcode), t1); + gen_compute_fprf_float64(t1); if (unlikely(Rc(ctx->opcode) != 0)) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } static void gen_fsqrts(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); gen_reset_fpstatus(); - gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, - cpu_fpr[rB(ctx->opcode)]); - gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, - cpu_fpr[rD(ctx->opcode)]); - gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); + get_fpr(t0, rB(ctx->opcode)); + gen_helper_fsqrt(t1, cpu_env, t0); + gen_helper_frsp(t1, cpu_env, t1); + set_fpr(rD(ctx->opcode), t1); + gen_compute_fprf_float64(t1); if (unlikely(Rc(ctx->opcode) != 0)) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } /*** Floating-Point multiply-and-add ***/ @@ -268,21 +332,32 @@ GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); static void gen_ftdiv(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } - gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], - cpu_fpr[rB(ctx->opcode)]); + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + get_fpr(t0, rA(ctx->opcode)); + get_fpr(t1, rB(ctx->opcode)); + gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], t0, t1); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } static void gen_ftsqrt(DisasContext *ctx) { + TCGv_i64 t0; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } - gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); + t0 = tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], t0); + tcg_temp_free_i64(t0); } @@ -293,32 +368,46 @@ static void gen_ftsqrt(DisasContext *ctx) static void gen_fcmpo(DisasContext *ctx) { TCGv_i32 crf; + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); gen_reset_fpstatus(); crf = tcg_const_i32(crfD(ctx->opcode)); - gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)], - cpu_fpr[rB(ctx->opcode)], crf); + get_fpr(t0, rA(ctx->opcode)); + get_fpr(t1, rB(ctx->opcode)); + gen_helper_fcmpo(cpu_env, t0, t1, crf); tcg_temp_free_i32(crf); gen_helper_float_check_status(cpu_env); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } /* fcmpu */ static void gen_fcmpu(DisasContext *ctx) { TCGv_i32 crf; + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); gen_reset_fpstatus(); crf = tcg_const_i32(crfD(ctx->opcode)); - gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)], - cpu_fpr[rB(ctx->opcode)], crf); + get_fpr(t0, rA(ctx->opcode)); + get_fpr(t1, rB(ctx->opcode)); + gen_helper_fcmpu(cpu_env, t0, t1, crf); tcg_temp_free_i32(crf); gen_helper_float_check_status(cpu_env); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } /*** Floating-point move ***/ @@ -326,100 +415,153 @@ static void gen_fcmpu(DisasContext *ctx) /* XXX: beware that fabs never checks for NaNs nor update FPSCR */ static void gen_fabs(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } - tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], - ~(1ULL << 63)); + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + tcg_gen_andi_i64(t1, t0, ~(1ULL << 63)); + set_fpr(rD(ctx->opcode), t1); if (unlikely(Rc(ctx->opcode))) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } /* fmr - fmr. */ /* XXX: beware that fmr never checks for NaNs nor update FPSCR */ static void gen_fmr(DisasContext *ctx) { + TCGv_i64 t0; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } - tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); + t0 = tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + set_fpr(rD(ctx->opcode), t0); if (unlikely(Rc(ctx->opcode))) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); } /* fnabs */ /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ static void gen_fnabs(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } - tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], - 1ULL << 63); + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + tcg_gen_ori_i64(t1, t0, 1ULL << 63); + set_fpr(rD(ctx->opcode), t1); if (unlikely(Rc(ctx->opcode))) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } /* fneg */ /* XXX: beware that fneg never checks for NaNs nor update FPSCR */ static void gen_fneg(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } - tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], - 1ULL << 63); + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + tcg_gen_xori_i64(t1, t0, 1ULL << 63); + set_fpr(rD(ctx->opcode), t1); if (unlikely(Rc(ctx->opcode))) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } /* fcpsgn: PowerPC 2.05 specification */ /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */ static void gen_fcpsgn(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; + TCGv_i64 t2; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } - tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], - cpu_fpr[rB(ctx->opcode)], 0, 63); + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + t2 = tcg_temp_new_i64(); + get_fpr(t0, rA(ctx->opcode)); + get_fpr(t1, rB(ctx->opcode)); + tcg_gen_deposit_i64(t2, t0, t1, 0, 63); + set_fpr(rD(ctx->opcode), t2); if (unlikely(Rc(ctx->opcode))) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); } static void gen_fmrgew(DisasContext *ctx) { TCGv_i64 b0; + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } b0 = tcg_temp_new_i64(); - tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32); - tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], - b0, 0, 32); + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + tcg_gen_shri_i64(b0, t0, 32); + get_fpr(t0, rA(ctx->opcode)); + tcg_gen_deposit_i64(t1, t0, b0, 0, 32); + set_fpr(rD(ctx->opcode), t1); tcg_temp_free_i64(b0); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } static void gen_fmrgow(DisasContext *ctx) { + TCGv_i64 t0; + TCGv_i64 t1; + TCGv_i64 t2; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } - tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], - cpu_fpr[rB(ctx->opcode)], - cpu_fpr[rA(ctx->opcode)], - 32, 32); + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + t2 = tcg_temp_new_i64(); + get_fpr(t0, rB(ctx->opcode)); + get_fpr(t1, rA(ctx->opcode)); + tcg_gen_deposit_i64(t2, t0, t1, 32, 32); + set_fpr(rD(ctx->opcode), t2); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); } /*** Floating-Point status & ctrl register ***/ @@ -458,15 +600,19 @@ static void gen_mcrfs(DisasContext *ctx) /* mffs */ static void gen_mffs(DisasContext *ctx) { + TCGv_i64 t0; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } + t0 = tcg_temp_new_i64(); gen_reset_fpstatus(); - tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); + tcg_gen_extu_tl_i64(t0, cpu_fpscr); + set_fpr(rD(ctx->opcode), t0); if (unlikely(Rc(ctx->opcode))) { gen_set_cr1_from_fpscr(ctx); } + tcg_temp_free_i64(t0); } /* mtfsb0 */ @@ -522,6 +668,7 @@ static void gen_mtfsb1(DisasContext *ctx) static void gen_mtfsf(DisasContext *ctx) { TCGv_i32 t0; + TCGv_i64 t1; int flm, l, w; if (unlikely(!ctx->fpu_enabled)) { @@ -541,7 +688,9 @@ static void gen_mtfsf(DisasContext *ctx) } else { t0 = tcg_const_i32(flm << (w * 8)); } - gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0); + t1 = tcg_temp_new_i64(); + get_fpr(t1, rB(ctx->opcode)); + gen_helper_store_fpscr(cpu_env, t1, t0); tcg_temp_free_i32(t0); if (unlikely(Rc(ctx->opcode) != 0)) { tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); @@ -549,6 +698,7 @@ static void gen_mtfsf(DisasContext *ctx) } /* We can raise a differed exception */ gen_helper_float_check_status(cpu_env); + tcg_temp_free_i64(t1); } /* mtfsfi */ @@ -588,21 +738,26 @@ static void gen_mtfsfi(DisasContext *ctx) static void glue(gen_, name)(DisasContext *ctx) \ { \ TCGv EA; \ + TCGv_i64 t0; \ if (unlikely(!ctx->fpu_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ gen_set_access_type(ctx, ACCESS_FLOAT); \ EA = tcg_temp_new(); \ + t0 = tcg_temp_new_i64(); \ gen_addr_imm_index(ctx, EA, 0); \ - gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ + gen_qemu_##ldop(ctx, t0, EA); \ + set_fpr(rD(ctx->opcode), t0); \ tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ } #define GEN_LDUF(name, ldop, opc, type) \ static void glue(gen_, name##u)(DisasContext *ctx) \ { \ TCGv EA; \ + TCGv_i64 t0; \ if (unlikely(!ctx->fpu_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ @@ -613,20 +768,25 @@ static void glue(gen_, name##u)(DisasContext *ctx) } \ gen_set_access_type(ctx, ACCESS_FLOAT); \ EA = tcg_temp_new(); \ + t0 = tcg_temp_new_i64(); \ gen_addr_imm_index(ctx, EA, 0); \ - gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ + gen_qemu_##ldop(ctx, t0, EA); \ + set_fpr(rD(ctx->opcode), t0); \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ } #define GEN_LDUXF(name, ldop, opc, type) \ static void glue(gen_, name##ux)(DisasContext *ctx) \ { \ TCGv EA; \ + TCGv_i64 t0; \ if (unlikely(!ctx->fpu_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ + t0 = tcg_temp_new_i64(); \ if (unlikely(rA(ctx->opcode) == 0)) { \ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ return; \ @@ -634,24 +794,30 @@ static void glue(gen_, name##ux)(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_FLOAT); \ EA = tcg_temp_new(); \ gen_addr_reg_index(ctx, EA); \ - gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ + gen_qemu_##ldop(ctx, t0, EA); \ + set_fpr(rD(ctx->opcode), t0); \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ } #define GEN_LDXF(name, ldop, opc2, opc3, type) \ static void glue(gen_, name##x)(DisasContext *ctx) \ { \ TCGv EA; \ + TCGv_i64 t0; \ if (unlikely(!ctx->fpu_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ gen_set_access_type(ctx, ACCESS_FLOAT); \ EA = tcg_temp_new(); \ + t0 = tcg_temp_new_i64(); \ gen_addr_reg_index(ctx, EA); \ - gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ + gen_qemu_##ldop(ctx, t0, EA); \ + set_fpr(rD(ctx->opcode), t0); \ tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ } #define GEN_LDFS(name, ldop, op, type) \ @@ -677,6 +843,7 @@ GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); static void gen_lfdepx(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; CHK_SV; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); @@ -684,16 +851,19 @@ static void gen_lfdepx(DisasContext *ctx) } gen_set_access_type(ctx, ACCESS_FLOAT); EA = tcg_temp_new(); + t0 = tcg_temp_new_i64(); gen_addr_reg_index(ctx, EA); - tcg_gen_qemu_ld_i64(cpu_fpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, - DEF_MEMOP(MO_Q)); + tcg_gen_qemu_ld_i64(t0, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_Q)); + set_fpr(rD(ctx->opcode), t0); tcg_temp_free(EA); + tcg_temp_free_i64(t0); } /* lfdp */ static void gen_lfdp(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; @@ -701,24 +871,31 @@ static void gen_lfdp(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_FLOAT); EA = tcg_temp_new(); gen_addr_imm_index(ctx, EA, 0); + t0 = tcg_temp_new_i64(); /* We only need to swap high and low halves. gen_qemu_ld64_i64 does necessary 64-bit byteswap already. */ if (unlikely(ctx->le_mode)) { - gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode) + 1, t0); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode), t0); } else { - gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode), t0); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode) + 1, t0); } tcg_temp_free(EA); + tcg_temp_free_i64(t0); } /* lfdpx */ static void gen_lfdpx(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; @@ -726,18 +903,24 @@ static void gen_lfdpx(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_FLOAT); EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); + t0 = tcg_temp_new_i64(); /* We only need to swap high and low halves. gen_qemu_ld64_i64 does necessary 64-bit byteswap already. */ if (unlikely(ctx->le_mode)) { - gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode) + 1, t0); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode), t0); } else { - gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode), t0); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode) + 1, t0); } tcg_temp_free(EA); + tcg_temp_free_i64(t0); } /* lfiwax */ @@ -745,6 +928,7 @@ static void gen_lfiwax(DisasContext *ctx) { TCGv EA; TCGv t0; + TCGv_i64 t1; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; @@ -752,47 +936,59 @@ static void gen_lfiwax(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_FLOAT); EA = tcg_temp_new(); t0 = tcg_temp_new(); + t1 = tcg_temp_new_i64(); gen_addr_reg_index(ctx, EA); gen_qemu_ld32s(ctx, t0, EA); - tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0); + tcg_gen_ext_tl_i64(t1, t0); + set_fpr(rD(ctx->opcode), t1); tcg_temp_free(EA); tcg_temp_free(t0); + tcg_temp_free_i64(t1); } /* lfiwzx */ static void gen_lfiwzx(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } gen_set_access_type(ctx, ACCESS_FLOAT); EA = tcg_temp_new(); + t0 = tcg_temp_new_i64(); gen_addr_reg_index(ctx, EA); - gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + gen_qemu_ld32u_i64(ctx, t0, EA); + set_fpr(rD(ctx->opcode), t0); tcg_temp_free(EA); + tcg_temp_free_i64(t0); } /*** Floating-point store ***/ #define GEN_STF(name, stop, opc, type) \ static void glue(gen_, name)(DisasContext *ctx) \ { \ TCGv EA; \ + TCGv_i64 t0; \ if (unlikely(!ctx->fpu_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ gen_set_access_type(ctx, ACCESS_FLOAT); \ EA = tcg_temp_new(); \ + t0 = tcg_temp_new_i64(); \ gen_addr_imm_index(ctx, EA, 0); \ - gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ + get_fpr(t0, rS(ctx->opcode)); \ + gen_qemu_##stop(ctx, t0, EA); \ tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ } #define GEN_STUF(name, stop, opc, type) \ static void glue(gen_, name##u)(DisasContext *ctx) \ { \ TCGv EA; \ + TCGv_i64 t0; \ if (unlikely(!ctx->fpu_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ @@ -803,16 +999,20 @@ static void glue(gen_, name##u)(DisasContext *ctx) } \ gen_set_access_type(ctx, ACCESS_FLOAT); \ EA = tcg_temp_new(); \ + t0 = tcg_temp_new_i64(); \ gen_addr_imm_index(ctx, EA, 0); \ - gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ + get_fpr(t0, rS(ctx->opcode)); \ + gen_qemu_##stop(ctx, t0, EA); \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ } #define GEN_STUXF(name, stop, opc, type) \ static void glue(gen_, name##ux)(DisasContext *ctx) \ { \ TCGv EA; \ + TCGv_i64 t0; \ if (unlikely(!ctx->fpu_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ @@ -823,25 +1023,32 @@ static void glue(gen_, name##ux)(DisasContext *ctx) } \ gen_set_access_type(ctx, ACCESS_FLOAT); \ EA = tcg_temp_new(); \ + t0 = tcg_temp_new_i64(); \ gen_addr_reg_index(ctx, EA); \ - gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ + get_fpr(t0, rS(ctx->opcode)); \ + gen_qemu_##stop(ctx, t0, EA); \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ } #define GEN_STXF(name, stop, opc2, opc3, type) \ static void glue(gen_, name##x)(DisasContext *ctx) \ { \ TCGv EA; \ + TCGv_i64 t0; \ if (unlikely(!ctx->fpu_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ gen_set_access_type(ctx, ACCESS_FLOAT); \ EA = tcg_temp_new(); \ + t0 = tcg_temp_new_i64(); \ gen_addr_reg_index(ctx, EA); \ - gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ + get_fpr(t0, rS(ctx->opcode)); \ + gen_qemu_##stop(ctx, t0, EA); \ tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ } #define GEN_STFS(name, stop, op, type) \ @@ -867,6 +1074,7 @@ GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); static void gen_stfdepx(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; CHK_SV; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); @@ -874,60 +1082,76 @@ static void gen_stfdepx(DisasContext *ctx) } gen_set_access_type(ctx, ACCESS_FLOAT); EA = tcg_temp_new(); + t0 = tcg_temp_new_i64(); gen_addr_reg_index(ctx, EA); - tcg_gen_qemu_st_i64(cpu_fpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, - DEF_MEMOP(MO_Q)); + get_fpr(t0, rD(ctx->opcode)); + tcg_gen_qemu_st_i64(t0, EA, PPC_TLB_EPID_STORE, DEF_MEMOP(MO_Q)); tcg_temp_free(EA); + tcg_temp_free_i64(t0); } /* stfdp */ static void gen_stfdp(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } gen_set_access_type(ctx, ACCESS_FLOAT); EA = tcg_temp_new(); + t0 = tcg_temp_new_i64(); gen_addr_imm_index(ctx, EA, 0); /* We only need to swap high and low halves. gen_qemu_st64_i64 does necessary 64-bit byteswap already. */ if (unlikely(ctx->le_mode)) { - gen_qemu_st64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); + get_fpr(t0, rD(ctx->opcode) + 1); + gen_qemu_st64_i64(ctx, t0, EA); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_st64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + get_fpr(t0, rD(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); } else { - gen_qemu_st64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + get_fpr(t0, rD(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_st64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); + get_fpr(t0, rD(ctx->opcode) + 1); + gen_qemu_st64_i64(ctx, t0, EA); } tcg_temp_free(EA); + tcg_temp_free_i64(t0); } /* stfdpx */ static void gen_stfdpx(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; if (unlikely(!ctx->fpu_enabled)) { gen_exception(ctx, POWERPC_EXCP_FPU); return; } gen_set_access_type(ctx, ACCESS_FLOAT); EA = tcg_temp_new(); + t0 = tcg_temp_new_i64(); gen_addr_reg_index(ctx, EA); /* We only need to swap high and low halves. gen_qemu_st64_i64 does necessary 64-bit byteswap already. */ if (unlikely(ctx->le_mode)) { - gen_qemu_st64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); + get_fpr(t0, rD(ctx->opcode) + 1); + gen_qemu_st64_i64(ctx, t0, EA); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_st64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + get_fpr(t0, rD(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); } else { - gen_qemu_st64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); + get_fpr(t0, rD(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_st64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); + get_fpr(t0, rD(ctx->opcode) + 1); + gen_qemu_st64_i64(ctx, t0, EA); } tcg_temp_free(EA); + tcg_temp_free_i64(t0); } /* Optional: */ @@ -949,13 +1173,18 @@ static void gen_lfq(DisasContext *ctx) { int rd = rD(ctx->opcode); TCGv t0; + TCGv_i64 t1; gen_set_access_type(ctx, ACCESS_FLOAT); t0 = tcg_temp_new(); + t1 = tcg_temp_new_i64(); gen_addr_imm_index(ctx, t0, 0); - gen_qemu_ld64_i64(ctx, cpu_fpr[rd], t0); + gen_qemu_ld64_i64(ctx, t1, t0); + set_fpr(rd, t1); gen_addr_add(ctx, t0, t0, 8); - gen_qemu_ld64_i64(ctx, cpu_fpr[(rd + 1) % 32], t0); + gen_qemu_ld64_i64(ctx, t1, t0); + set_fpr((rd + 1) % 32, t1); tcg_temp_free(t0); + tcg_temp_free_i64(t1); } /* lfqu */ @@ -964,17 +1193,22 @@ static void gen_lfqu(DisasContext *ctx) int ra = rA(ctx->opcode); int rd = rD(ctx->opcode); TCGv t0, t1; + TCGv_i64 t2; gen_set_access_type(ctx, ACCESS_FLOAT); t0 = tcg_temp_new(); t1 = tcg_temp_new(); + t2 = tcg_temp_new_i64(); gen_addr_imm_index(ctx, t0, 0); - gen_qemu_ld64_i64(ctx, cpu_fpr[rd], t0); + gen_qemu_ld64_i64(ctx, t2, t0); + set_fpr(rd, t2); gen_addr_add(ctx, t1, t0, 8); - gen_qemu_ld64_i64(ctx, cpu_fpr[(rd + 1) % 32], t1); + gen_qemu_ld64_i64(ctx, t2, t1); + set_fpr((rd + 1) % 32, t2); if (ra != 0) tcg_gen_mov_tl(cpu_gpr[ra], t0); tcg_temp_free(t0); tcg_temp_free(t1); + tcg_temp_free_i64(t2); } /* lfqux */ @@ -984,16 +1218,21 @@ static void gen_lfqux(DisasContext *ctx) int rd = rD(ctx->opcode); gen_set_access_type(ctx, ACCESS_FLOAT); TCGv t0, t1; + TCGv_i64 t2; + t2 = tcg_temp_new_i64(); t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_qemu_ld64_i64(ctx, cpu_fpr[rd], t0); + gen_qemu_ld64_i64(ctx, t2, t0); + set_fpr(rd, t2); t1 = tcg_temp_new(); gen_addr_add(ctx, t1, t0, 8); - gen_qemu_ld64_i64(ctx, cpu_fpr[(rd + 1) % 32], t1); + gen_qemu_ld64_i64(ctx, t2, t1); + set_fpr((rd + 1) % 32, t2); tcg_temp_free(t1); if (ra != 0) tcg_gen_mov_tl(cpu_gpr[ra], t0); tcg_temp_free(t0); + tcg_temp_free_i64(t2); } /* lfqx */ @@ -1001,13 +1240,18 @@ static void gen_lfqx(DisasContext *ctx) { int rd = rD(ctx->opcode); TCGv t0; + TCGv_i64 t1; gen_set_access_type(ctx, ACCESS_FLOAT); t0 = tcg_temp_new(); + t1 = tcg_temp_new_i64(); gen_addr_reg_index(ctx, t0); - gen_qemu_ld64_i64(ctx, cpu_fpr[rd], t0); + gen_qemu_ld64_i64(ctx, t1, t0); + set_fpr(rd, t1); gen_addr_add(ctx, t0, t0, 8); - gen_qemu_ld64_i64(ctx, cpu_fpr[(rd + 1) % 32], t0); + gen_qemu_ld64_i64(ctx, t1, t0); + set_fpr((rd + 1) % 32, t1); tcg_temp_free(t0); + tcg_temp_free_i64(t1); } /* stfq */ @@ -1015,13 +1259,18 @@ static void gen_stfq(DisasContext *ctx) { int rd = rD(ctx->opcode); TCGv t0; + TCGv_i64 t1; gen_set_access_type(ctx, ACCESS_FLOAT); t0 = tcg_temp_new(); + t1 = tcg_temp_new_i64(); gen_addr_imm_index(ctx, t0, 0); - gen_qemu_st64_i64(ctx, cpu_fpr[rd], t0); + get_fpr(t1, rd); + gen_qemu_st64_i64(ctx, t1, t0); gen_addr_add(ctx, t0, t0, 8); - gen_qemu_st64_i64(ctx, cpu_fpr[(rd + 1) % 32], t0); + get_fpr(t1, (rd + 1) % 32); + gen_qemu_st64_i64(ctx, t1, t0); tcg_temp_free(t0); + tcg_temp_free_i64(t1); } /* stfqu */ @@ -1030,17 +1279,23 @@ static void gen_stfqu(DisasContext *ctx) int ra = rA(ctx->opcode); int rd = rD(ctx->opcode); TCGv t0, t1; + TCGv_i64 t2; gen_set_access_type(ctx, ACCESS_FLOAT); + t2 = tcg_temp_new_i64(); t0 = tcg_temp_new(); gen_addr_imm_index(ctx, t0, 0); - gen_qemu_st64_i64(ctx, cpu_fpr[rd], t0); + get_fpr(t2, rd); + gen_qemu_st64_i64(ctx, t2, t0); t1 = tcg_temp_new(); gen_addr_add(ctx, t1, t0, 8); - gen_qemu_st64_i64(ctx, cpu_fpr[(rd + 1) % 32], t1); + get_fpr(t2, (rd + 1) % 32); + gen_qemu_st64_i64(ctx, t2, t1); tcg_temp_free(t1); - if (ra != 0) + if (ra != 0) { tcg_gen_mov_tl(cpu_gpr[ra], t0); + } tcg_temp_free(t0); + tcg_temp_free_i64(t2); } /* stfqux */ @@ -1049,17 +1304,23 @@ static void gen_stfqux(DisasContext *ctx) int ra = rA(ctx->opcode); int rd = rD(ctx->opcode); TCGv t0, t1; + TCGv_i64 t2; gen_set_access_type(ctx, ACCESS_FLOAT); + t2 = tcg_temp_new_i64(); t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_qemu_st64_i64(ctx, cpu_fpr[rd], t0); + get_fpr(t2, rd); + gen_qemu_st64_i64(ctx, t2, t0); t1 = tcg_temp_new(); gen_addr_add(ctx, t1, t0, 8); - gen_qemu_st64_i64(ctx, cpu_fpr[(rd + 1) % 32], t1); + get_fpr(t2, (rd + 1) % 32); + gen_qemu_st64_i64(ctx, t2, t1); tcg_temp_free(t1); - if (ra != 0) + if (ra != 0) { tcg_gen_mov_tl(cpu_gpr[ra], t0); + } tcg_temp_free(t0); + tcg_temp_free_i64(t2); } /* stfqx */ @@ -1067,13 +1328,18 @@ static void gen_stfqx(DisasContext *ctx) { int rd = rD(ctx->opcode); TCGv t0; + TCGv_i64 t1; gen_set_access_type(ctx, ACCESS_FLOAT); + t1 = tcg_temp_new_i64(); t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_qemu_st64_i64(ctx, cpu_fpr[rd], t0); + get_fpr(t1, rd); + gen_qemu_st64_i64(ctx, t1, t0); gen_addr_add(ctx, t0, t0, 8); - gen_qemu_st64_i64(ctx, cpu_fpr[(rd + 1) % 32], t0); + get_fpr(t1, (rd + 1) % 32); + gen_qemu_st64_i64(ctx, t1, t0); tcg_temp_free(t0); + tcg_temp_free_i64(t1); } #undef _GEN_FLOAT_ACB diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c index 3cb6fc2926..f99d0284c2 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -10,60 +10,79 @@ static inline TCGv_ptr gen_avr_ptr(int reg) { TCGv_ptr r = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); + tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[32 + reg].u64[0])); return r; } +static inline long avr64_offset(int reg, bool high) +{ + return offsetof(CPUPPCState, vsr[32 + reg].u64[(high ? 0 : 1)]); +} + #define GEN_VR_LDX(name, opc2, opc3) \ static void glue(gen_, name)(DisasContext *ctx) \ { \ TCGv EA; \ + TCGv_i64 avr; \ if (unlikely(!ctx->altivec_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VPU); \ return; \ } \ gen_set_access_type(ctx, ACCESS_INT); \ + avr = tcg_temp_new_i64(); \ EA = tcg_temp_new(); \ gen_addr_reg_index(ctx, EA); \ tcg_gen_andi_tl(EA, EA, ~0xf); \ /* We only need to swap high and low halves. gen_qemu_ld64_i64 does \ necessary 64-bit byteswap already. */ \ if (ctx->le_mode) { \ - gen_qemu_ld64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ + gen_qemu_ld64_i64(ctx, avr, EA); \ + set_avr64(rD(ctx->opcode), avr, false); \ tcg_gen_addi_tl(EA, EA, 8); \ - gen_qemu_ld64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ + gen_qemu_ld64_i64(ctx, avr, EA); \ + set_avr64(rD(ctx->opcode), avr, true); \ } else { \ - gen_qemu_ld64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ + gen_qemu_ld64_i64(ctx, avr, EA); \ + set_avr64(rD(ctx->opcode), avr, true); \ tcg_gen_addi_tl(EA, EA, 8); \ - gen_qemu_ld64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ + gen_qemu_ld64_i64(ctx, avr, EA); \ + set_avr64(rD(ctx->opcode), avr, false); \ } \ tcg_temp_free(EA); \ + tcg_temp_free_i64(avr); \ } #define GEN_VR_STX(name, opc2, opc3) \ static void gen_st##name(DisasContext *ctx) \ { \ TCGv EA; \ + TCGv_i64 avr; \ if (unlikely(!ctx->altivec_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VPU); \ return; \ } \ gen_set_access_type(ctx, ACCESS_INT); \ + avr = tcg_temp_new_i64(); \ EA = tcg_temp_new(); \ gen_addr_reg_index(ctx, EA); \ tcg_gen_andi_tl(EA, EA, ~0xf); \ /* We only need to swap high and low halves. gen_qemu_st64_i64 does \ necessary 64-bit byteswap already. */ \ if (ctx->le_mode) { \ - gen_qemu_st64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ + get_avr64(avr, rD(ctx->opcode), false); \ + gen_qemu_st64_i64(ctx, avr, EA); \ tcg_gen_addi_tl(EA, EA, 8); \ - gen_qemu_st64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ + get_avr64(avr, rD(ctx->opcode), true); \ + gen_qemu_st64_i64(ctx, avr, EA); \ } else { \ - gen_qemu_st64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ + get_avr64(avr, rD(ctx->opcode), true); \ + gen_qemu_st64_i64(ctx, avr, EA); \ tcg_gen_addi_tl(EA, EA, 8); \ - gen_qemu_st64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ + get_avr64(avr, rD(ctx->opcode), false); \ + gen_qemu_st64_i64(ctx, avr, EA); \ } \ tcg_temp_free(EA); \ + tcg_temp_free_i64(avr); \ } #define GEN_VR_LVE(name, opc2, opc3, size) \ @@ -159,15 +178,20 @@ static void gen_lvsr(DisasContext *ctx) static void gen_mfvscr(DisasContext *ctx) { TCGv_i32 t; + TCGv_i64 avr; if (unlikely(!ctx->altivec_enabled)) { gen_exception(ctx, POWERPC_EXCP_VPU); return; } - tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); + avr = tcg_temp_new_i64(); + tcg_gen_movi_i64(avr, 0); + set_avr64(rD(ctx->opcode), avr, true); t = tcg_temp_new_i32(); tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr)); - tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); + tcg_gen_extu_i32_i64(avr, t); + set_avr64(rD(ctx->opcode), avr, false); tcg_temp_free_i32(t); + tcg_temp_free_i64(avr); } static void gen_mtvscr(DisasContext *ctx) @@ -185,9 +209,10 @@ static void gen_mtvscr(DisasContext *ctx) #define GEN_VX_VMUL10(name, add_cin, ret_carry) \ static void glue(gen_, name)(DisasContext *ctx) \ { \ - TCGv_i64 t0 = tcg_temp_new_i64(); \ - TCGv_i64 t1 = tcg_temp_new_i64(); \ - TCGv_i64 t2 = tcg_temp_new_i64(); \ + TCGv_i64 t0; \ + TCGv_i64 t1; \ + TCGv_i64 t2; \ + TCGv_i64 avr; \ TCGv_i64 ten, z; \ \ if (unlikely(!ctx->altivec_enabled)) { \ @@ -195,30 +220,43 @@ static void glue(gen_, name)(DisasContext *ctx) \ return; \ } \ \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ + t2 = tcg_temp_new_i64(); \ + avr = tcg_temp_new_i64(); \ ten = tcg_const_i64(10); \ z = tcg_const_i64(0); \ \ if (add_cin) { \ - tcg_gen_mulu2_i64(t0, t1, cpu_avrl[rA(ctx->opcode)], ten); \ - tcg_gen_andi_i64(t2, cpu_avrl[rB(ctx->opcode)], 0xF); \ - tcg_gen_add2_i64(cpu_avrl[rD(ctx->opcode)], t2, t0, t1, t2, z); \ + get_avr64(avr, rA(ctx->opcode), false); \ + tcg_gen_mulu2_i64(t0, t1, avr, ten); \ + get_avr64(avr, rB(ctx->opcode), false); \ + tcg_gen_andi_i64(t2, avr, 0xF); \ + tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \ + set_avr64(rD(ctx->opcode), avr, false); \ } else { \ - tcg_gen_mulu2_i64(cpu_avrl[rD(ctx->opcode)], t2, \ - cpu_avrl[rA(ctx->opcode)], ten); \ + get_avr64(avr, rA(ctx->opcode), false); \ + tcg_gen_mulu2_i64(avr, t2, avr, ten); \ + set_avr64(rD(ctx->opcode), avr, false); \ } \ \ if (ret_carry) { \ - tcg_gen_mulu2_i64(t0, t1, cpu_avrh[rA(ctx->opcode)], ten); \ - tcg_gen_add2_i64(t0, cpu_avrl[rD(ctx->opcode)], t0, t1, t2, z); \ - tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); \ + get_avr64(avr, rA(ctx->opcode), true); \ + tcg_gen_mulu2_i64(t0, t1, avr, ten); \ + tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \ + set_avr64(rD(ctx->opcode), avr, false); \ + set_avr64(rD(ctx->opcode), z, true); \ } else { \ - tcg_gen_mul_i64(t0, cpu_avrh[rA(ctx->opcode)], ten); \ - tcg_gen_add_i64(cpu_avrh[rD(ctx->opcode)], t0, t2); \ + get_avr64(avr, rA(ctx->opcode), true); \ + tcg_gen_mul_i64(t0, avr, ten); \ + tcg_gen_add_i64(avr, t0, t2); \ + set_avr64(rD(ctx->opcode), avr, true); \ } \ \ tcg_temp_free_i64(t0); \ tcg_temp_free_i64(t1); \ tcg_temp_free_i64(t2); \ + tcg_temp_free_i64(avr); \ tcg_temp_free_i64(ten); \ tcg_temp_free_i64(z); \ } \ @@ -232,12 +270,31 @@ GEN_VX_VMUL10(vmul10ecuq, 1, 1); #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ static void glue(gen_, name)(DisasContext *ctx) \ { \ + TCGv_i64 t0; \ + TCGv_i64 t1; \ + TCGv_i64 avr; \ + \ if (unlikely(!ctx->altivec_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VPU); \ return; \ } \ - tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ - tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ + avr = tcg_temp_new_i64(); \ + \ + get_avr64(t0, rA(ctx->opcode), true); \ + get_avr64(t1, rB(ctx->opcode), true); \ + tcg_op(avr, t0, t1); \ + set_avr64(rD(ctx->opcode), avr, true); \ + \ + get_avr64(t0, rA(ctx->opcode), false); \ + get_avr64(t1, rB(ctx->opcode), false); \ + tcg_op(avr, t0, t1); \ + set_avr64(rD(ctx->opcode), avr, false); \ + \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ + tcg_temp_free_i64(avr); \ } GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); @@ -406,6 +463,7 @@ GEN_VXFORM(vmrglw, 6, 6); static void gen_vmrgew(DisasContext *ctx) { TCGv_i64 tmp; + TCGv_i64 avr; int VT, VA, VB; if (unlikely(!ctx->altivec_enabled)) { gen_exception(ctx, POWERPC_EXCP_VPU); @@ -415,15 +473,28 @@ static void gen_vmrgew(DisasContext *ctx) VA = rA(ctx->opcode); VB = rB(ctx->opcode); tmp = tcg_temp_new_i64(); - tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32); - tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32); - tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32); - tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32); + avr = tcg_temp_new_i64(); + + get_avr64(avr, VB, true); + tcg_gen_shri_i64(tmp, avr, 32); + get_avr64(avr, VA, true); + tcg_gen_deposit_i64(avr, avr, tmp, 0, 32); + set_avr64(VT, avr, true); + + get_avr64(avr, VB, false); + tcg_gen_shri_i64(tmp, avr, 32); + get_avr64(avr, VA, false); + tcg_gen_deposit_i64(avr, avr, tmp, 0, 32); + set_avr64(VT, avr, false); + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(avr); } static void gen_vmrgow(DisasContext *ctx) { + TCGv_i64 t0, t1; + TCGv_i64 avr; int VT, VA, VB; if (unlikely(!ctx->altivec_enabled)) { gen_exception(ctx, POWERPC_EXCP_VPU); @@ -432,9 +503,23 @@ static void gen_vmrgow(DisasContext *ctx) VT = rD(ctx->opcode); VA = rA(ctx->opcode); VB = rB(ctx->opcode); - - tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32); - tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32); + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + avr = tcg_temp_new_i64(); + + get_avr64(t0, VB, true); + get_avr64(t1, VA, true); + tcg_gen_deposit_i64(avr, t0, t1, 32, 32); + set_avr64(VT, avr, true); + + get_avr64(t0, VB, false); + get_avr64(t1, VA, false); + tcg_gen_deposit_i64(avr, t0, t1, 32, 32); + set_avr64(VT, avr, false); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(avr); } GEN_VXFORM(vmuloub, 4, 0); @@ -790,7 +875,7 @@ static void glue(gen_, name)(DisasContext *ctx) \ { \ TCGv_ptr rb, rd; \ uint8_t uimm = UIMM4(ctx->opcode); \ - TCGv_i32 t0 = tcg_temp_new_i32(); \ + TCGv_i32 t0; \ if (unlikely(!ctx->altivec_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VPU); \ return; \ @@ -798,6 +883,7 @@ static void glue(gen_, name)(DisasContext *ctx) \ if (uimm > splat_max) { \ uimm = 0; \ } \ + t0 = tcg_temp_new_i32(); \ tcg_gen_movi_i32(t0, uimm); \ rb = gen_avr_ptr(rB(ctx->opcode)); \ rd = gen_avr_ptr(rD(ctx->opcode)); \ diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 85ed135d44..ed4fdceacf 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1,20 +1,48 @@ /*** VSX extension ***/ -static inline TCGv_i64 cpu_vsrh(int n) +static inline void get_vsr(TCGv_i64 dst, int n) +{ + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[n].u64[1])); +} + +static inline void set_vsr(int n, TCGv_i64 src) +{ + tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[n].u64[1])); +} + +static inline void get_cpu_vsrh(TCGv_i64 dst, int n) +{ + if (n < 32) { + get_fpr(dst, n); + } else { + get_avr64(dst, n - 32, true); + } +} + +static inline void get_cpu_vsrl(TCGv_i64 dst, int n) +{ + if (n < 32) { + get_vsr(dst, n); + } else { + get_avr64(dst, n - 32, false); + } +} + +static inline void set_cpu_vsrh(int n, TCGv_i64 src) { if (n < 32) { - return cpu_fpr[n]; + set_fpr(n, src); } else { - return cpu_avrh[n-32]; + set_avr64(n - 32, src, true); } } -static inline TCGv_i64 cpu_vsrl(int n) +static inline void set_cpu_vsrl(int n, TCGv_i64 src) { if (n < 32) { - return cpu_vsr[n]; + set_vsr(n, src); } else { - return cpu_avrl[n-32]; + set_avr64(n - 32, src, false); } } @@ -22,16 +50,20 @@ static inline TCGv_i64 cpu_vsrl(int n) static void gen_##name(DisasContext *ctx) \ { \ TCGv EA; \ + TCGv_i64 t0; \ if (unlikely(!ctx->vsx_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ } \ + t0 = tcg_temp_new_i64(); \ gen_set_access_type(ctx, ACCESS_INT); \ EA = tcg_temp_new(); \ gen_addr_reg_index(ctx, EA); \ - gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \ + gen_qemu_##operation(ctx, t0, EA); \ + set_cpu_vsrh(xT(ctx->opcode), t0); \ /* NOTE: cpu_vsrl is undefined */ \ tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ } VSX_LOAD_SCALAR(lxsdx, ld64_i64) @@ -44,43 +76,60 @@ VSX_LOAD_SCALAR(lxsspx, ld32fs) static void gen_lxvd2x(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + t0 = tcg_temp_new_i64(); gen_set_access_type(ctx, ACCESS_INT); EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); - gen_qemu_ld64_i64(ctx, cpu_vsrh(xT(ctx->opcode)), EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_cpu_vsrh(xT(ctx->opcode), t0); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_ld64_i64(ctx, cpu_vsrl(xT(ctx->opcode)), EA); + gen_qemu_ld64_i64(ctx, t0, EA); + set_cpu_vsrl(xT(ctx->opcode), t0); tcg_temp_free(EA); + tcg_temp_free_i64(t0); } static void gen_lxvdsx(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; + TCGv_i64 t1; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); gen_set_access_type(ctx, ACCESS_INT); EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); - gen_qemu_ld64_i64(ctx, cpu_vsrh(xT(ctx->opcode)), EA); - tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode))); + gen_qemu_ld64_i64(ctx, t0, EA); + set_cpu_vsrh(xT(ctx->opcode), t0); + tcg_gen_mov_i64(t1, t0); + set_cpu_vsrl(xT(ctx->opcode), t1); tcg_temp_free(EA); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); } static void gen_lxvw4x(DisasContext *ctx) { TCGv EA; - TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); + TCGv_i64 xth; + TCGv_i64 xtl; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + get_cpu_vsrh(xth, xT(ctx->opcode)); + get_cpu_vsrl(xtl, xT(ctx->opcode)); gen_set_access_type(ctx, ACCESS_INT); EA = tcg_temp_new(); @@ -104,6 +153,8 @@ static void gen_lxvw4x(DisasContext *ctx) tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ); } tcg_temp_free(EA); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); } static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl, @@ -151,13 +202,17 @@ static void gen_bswap32x4(TCGv_i64 outh, TCGv_i64 outl, static void gen_lxvh8x(DisasContext *ctx) { TCGv EA; - TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); + TCGv_i64 xth; + TCGv_i64 xtl; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + get_cpu_vsrh(xth, xT(ctx->opcode)); + get_cpu_vsrl(xtl, xT(ctx->opcode)); gen_set_access_type(ctx, ACCESS_INT); EA = tcg_temp_new(); @@ -169,18 +224,24 @@ static void gen_lxvh8x(DisasContext *ctx) gen_bswap16x8(xth, xtl, xth, xtl); } tcg_temp_free(EA); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); } static void gen_lxvb16x(DisasContext *ctx) { TCGv EA; - TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); + TCGv_i64 xth; + TCGv_i64 xtl; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + get_cpu_vsrh(xth, xT(ctx->opcode)); + get_cpu_vsrl(xtl, xT(ctx->opcode)); gen_set_access_type(ctx, ACCESS_INT); EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); @@ -188,6 +249,8 @@ static void gen_lxvb16x(DisasContext *ctx) tcg_gen_addi_tl(EA, EA, 8); tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ); tcg_temp_free(EA); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); } #define VSX_VECTOR_LOAD_STORE(name, op, indexed) \ @@ -195,15 +258,14 @@ static void gen_##name(DisasContext *ctx) \ { \ int xt; \ TCGv EA; \ - TCGv_i64 xth, xtl; \ + TCGv_i64 xth; \ + TCGv_i64 xtl; \ \ if (indexed) { \ xt = xT(ctx->opcode); \ } else { \ xt = DQxT(ctx->opcode); \ } \ - xth = cpu_vsrh(xt); \ - xtl = cpu_vsrl(xt); \ \ if (xt < 32) { \ if (unlikely(!ctx->vsx_enabled)) { \ @@ -216,6 +278,10 @@ static void gen_##name(DisasContext *ctx) \ return; \ } \ } \ + xth = tcg_temp_new_i64(); \ + xtl = tcg_temp_new_i64(); \ + get_cpu_vsrh(xth, xt); \ + get_cpu_vsrl(xtl, xt); \ gen_set_access_type(ctx, ACCESS_INT); \ EA = tcg_temp_new(); \ if (indexed) { \ @@ -225,14 +291,20 @@ static void gen_##name(DisasContext *ctx) \ } \ if (ctx->le_mode) { \ tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \ + set_cpu_vsrl(xt, xtl); \ tcg_gen_addi_tl(EA, EA, 8); \ tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \ + set_cpu_vsrh(xt, xth); \ } else { \ tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \ + set_cpu_vsrh(xt, xth); \ tcg_gen_addi_tl(EA, EA, 8); \ tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \ + set_cpu_vsrl(xt, xtl); \ } \ tcg_temp_free(EA); \ + tcg_temp_free_i64(xth); \ + tcg_temp_free_i64(xtl); \ } VSX_VECTOR_LOAD_STORE(lxv, ld_i64, 0) @@ -276,18 +348,22 @@ VSX_VECTOR_LOAD_STORE_LENGTH(stxvll) static void gen_##name(DisasContext *ctx) \ { \ TCGv EA; \ - TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32); \ + TCGv_i64 xth; \ \ if (unlikely(!ctx->altivec_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VPU); \ return; \ } \ + xth = tcg_temp_new_i64(); \ + get_cpu_vsrh(xth, rD(ctx->opcode) + 32); \ gen_set_access_type(ctx, ACCESS_INT); \ EA = tcg_temp_new(); \ gen_addr_imm_index(ctx, EA, 0x03); \ gen_qemu_##operation(ctx, xth, EA); \ + set_cpu_vsrh(rD(ctx->opcode) + 32, xth); \ /* NOTE: cpu_vsrl is undefined */ \ tcg_temp_free(EA); \ + tcg_temp_free_i64(xth); \ } VSX_LOAD_SCALAR_DS(lxsd, ld64_i64) @@ -297,15 +373,19 @@ VSX_LOAD_SCALAR_DS(lxssp, ld32fs) static void gen_##name(DisasContext *ctx) \ { \ TCGv EA; \ + TCGv_i64 t0; \ if (unlikely(!ctx->vsx_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ } \ + t0 = tcg_temp_new_i64(); \ gen_set_access_type(ctx, ACCESS_INT); \ EA = tcg_temp_new(); \ gen_addr_reg_index(ctx, EA); \ - gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \ + gen_qemu_##operation(ctx, t0, EA); \ + set_cpu_vsrh(xS(ctx->opcode), t0); \ tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ } VSX_STORE_SCALAR(stxsdx, st64_i64) @@ -318,28 +398,38 @@ VSX_STORE_SCALAR(stxsspx, st32fs) static void gen_stxvd2x(DisasContext *ctx) { TCGv EA; + TCGv_i64 t0; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + t0 = tcg_temp_new_i64(); gen_set_access_type(ctx, ACCESS_INT); EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); - gen_qemu_st64_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA); + get_cpu_vsrh(t0, xS(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); tcg_gen_addi_tl(EA, EA, 8); - gen_qemu_st64_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA); + get_cpu_vsrl(t0, xS(ctx->opcode)); + gen_qemu_st64_i64(ctx, t0, EA); tcg_temp_free(EA); + tcg_temp_free_i64(t0); } static void gen_stxvw4x(DisasContext *ctx) { - TCGv_i64 xsh = cpu_vsrh(xS(ctx->opcode)); - TCGv_i64 xsl = cpu_vsrl(xS(ctx->opcode)); TCGv EA; + TCGv_i64 xsh; + TCGv_i64 xsl; + if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xsh = tcg_temp_new_i64(); + xsl = tcg_temp_new_i64(); + get_cpu_vsrh(xsh, xS(ctx->opcode)); + get_cpu_vsrl(xsl, xS(ctx->opcode)); gen_set_access_type(ctx, ACCESS_INT); EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); @@ -362,18 +452,24 @@ static void gen_stxvw4x(DisasContext *ctx) tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); } tcg_temp_free(EA); + tcg_temp_free_i64(xsh); + tcg_temp_free_i64(xsl); } static void gen_stxvh8x(DisasContext *ctx) { - TCGv_i64 xsh = cpu_vsrh(xS(ctx->opcode)); - TCGv_i64 xsl = cpu_vsrl(xS(ctx->opcode)); TCGv EA; + TCGv_i64 xsh; + TCGv_i64 xsl; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xsh = tcg_temp_new_i64(); + xsl = tcg_temp_new_i64(); + get_cpu_vsrh(xsh, xS(ctx->opcode)); + get_cpu_vsrl(xsl, xS(ctx->opcode)); gen_set_access_type(ctx, ACCESS_INT); EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); @@ -393,18 +489,24 @@ static void gen_stxvh8x(DisasContext *ctx) tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); } tcg_temp_free(EA); + tcg_temp_free_i64(xsh); + tcg_temp_free_i64(xsl); } static void gen_stxvb16x(DisasContext *ctx) { - TCGv_i64 xsh = cpu_vsrh(xS(ctx->opcode)); - TCGv_i64 xsl = cpu_vsrl(xS(ctx->opcode)); TCGv EA; + TCGv_i64 xsh; + TCGv_i64 xsl; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xsh = tcg_temp_new_i64(); + xsl = tcg_temp_new_i64(); + get_cpu_vsrh(xsh, xS(ctx->opcode)); + get_cpu_vsrl(xsl, xS(ctx->opcode)); gen_set_access_type(ctx, ACCESS_INT); EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); @@ -412,80 +514,144 @@ static void gen_stxvb16x(DisasContext *ctx) tcg_gen_addi_tl(EA, EA, 8); tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); tcg_temp_free(EA); + tcg_temp_free_i64(xsh); + tcg_temp_free_i64(xsl); } #define VSX_STORE_SCALAR_DS(name, operation) \ static void gen_##name(DisasContext *ctx) \ { \ TCGv EA; \ - TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32); \ + TCGv_i64 xth; \ \ if (unlikely(!ctx->altivec_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VPU); \ return; \ } \ + xth = tcg_temp_new_i64(); \ + get_cpu_vsrh(xth, rD(ctx->opcode) + 32); \ gen_set_access_type(ctx, ACCESS_INT); \ EA = tcg_temp_new(); \ gen_addr_imm_index(ctx, EA, 0x03); \ gen_qemu_##operation(ctx, xth, EA); \ /* NOTE: cpu_vsrl is undefined */ \ tcg_temp_free(EA); \ + tcg_temp_free_i64(xth); \ } VSX_LOAD_SCALAR_DS(stxsd, st64_i64) VSX_LOAD_SCALAR_DS(stxssp, st32fs) -#define MV_VSRW(name, tcgop1, tcgop2, target, source) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - if (xS(ctx->opcode) < 32) { \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - } else { \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - } \ - TCGv_i64 tmp = tcg_temp_new_i64(); \ - tcg_gen_##tcgop1(tmp, source); \ - tcg_gen_##tcgop2(target, tmp); \ - tcg_temp_free_i64(tmp); \ +static void gen_mfvsrwz(DisasContext *ctx) +{ + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + TCGv_i64 tmp = tcg_temp_new_i64(); + TCGv_i64 xsh = tcg_temp_new_i64(); + get_cpu_vsrh(xsh, xS(ctx->opcode)); + tcg_gen_ext32u_i64(tmp, xsh); + tcg_gen_trunc_i64_tl(cpu_gpr[rA(ctx->opcode)], tmp); + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(xsh); } +static void gen_mtvsrwa(DisasContext *ctx) +{ + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + TCGv_i64 tmp = tcg_temp_new_i64(); + TCGv_i64 xsh = tcg_temp_new_i64(); + tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]); + tcg_gen_ext32s_i64(xsh, tmp); + set_cpu_vsrh(xT(ctx->opcode), xsh); + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(xsh); +} -MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \ - cpu_vsrh(xS(ctx->opcode))) -MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \ - cpu_gpr[rA(ctx->opcode)]) -MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \ - cpu_gpr[rA(ctx->opcode)]) +static void gen_mtvsrwz(DisasContext *ctx) +{ + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + TCGv_i64 tmp = tcg_temp_new_i64(); + TCGv_i64 xsh = tcg_temp_new_i64(); + tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]); + tcg_gen_ext32u_i64(xsh, tmp); + set_cpu_vsrh(xT(ctx->opcode), xsh); + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(xsh); +} #if defined(TARGET_PPC64) -#define MV_VSRD(name, target, source) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - if (xS(ctx->opcode) < 32) { \ - if (unlikely(!ctx->fpu_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_FPU); \ - return; \ - } \ - } else { \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - } \ - tcg_gen_mov_i64(target, source); \ +static void gen_mfvsrd(DisasContext *ctx) +{ + TCGv_i64 t0; + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + t0 = tcg_temp_new_i64(); + get_cpu_vsrh(t0, xS(ctx->opcode)); + tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0); + tcg_temp_free_i64(t0); } -MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode))) -MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)]) +static void gen_mtvsrd(DisasContext *ctx) +{ + TCGv_i64 t0; + if (xS(ctx->opcode) < 32) { + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + } else { + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + } + t0 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); + set_cpu_vsrh(xT(ctx->opcode), t0); + tcg_temp_free_i64(t0); +} static void gen_mfvsrld(DisasContext *ctx) { + TCGv_i64 t0; if (xS(ctx->opcode) < 32) { if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); @@ -497,12 +663,15 @@ static void gen_mfvsrld(DisasContext *ctx) return; } } - - tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], cpu_vsrl(xS(ctx->opcode))); + t0 = tcg_temp_new_i64(); + get_cpu_vsrl(t0, xS(ctx->opcode)); + tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0); + tcg_temp_free_i64(t0); } static void gen_mtvsrdd(DisasContext *ctx) { + TCGv_i64 t0; if (xT(ctx->opcode) < 32) { if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); @@ -515,17 +684,22 @@ static void gen_mtvsrdd(DisasContext *ctx) } } + t0 = tcg_temp_new_i64(); if (!rA(ctx->opcode)) { - tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); + tcg_gen_movi_i64(t0, 0); } else { - tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); } + set_cpu_vsrh(xT(ctx->opcode), t0); - tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_gpr[rB(ctx->opcode)]); + tcg_gen_mov_i64(t0, cpu_gpr[rB(ctx->opcode)]); + set_cpu_vsrl(xT(ctx->opcode), t0); + tcg_temp_free_i64(t0); } static void gen_mtvsrws(DisasContext *ctx) { + TCGv_i64 t0; if (xT(ctx->opcode) < 32) { if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); @@ -538,55 +712,61 @@ static void gen_mtvsrws(DisasContext *ctx) } } - tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)], + t0 = tcg_temp_new_i64(); + tcg_gen_deposit_i64(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32, 32); - tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xT(ctx->opcode))); + set_cpu_vsrl(xT(ctx->opcode), t0); + set_cpu_vsrh(xT(ctx->opcode), t0); + tcg_temp_free_i64(t0); } #endif static void gen_xxpermdi(DisasContext *ctx) { + TCGv_i64 xh, xl; + if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xh = tcg_temp_new_i64(); + xl = tcg_temp_new_i64(); + if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) || (xT(ctx->opcode) == xB(ctx->opcode)))) { - TCGv_i64 xh, xl; - - xh = tcg_temp_new_i64(); - xl = tcg_temp_new_i64(); - if ((DM(ctx->opcode) & 2) == 0) { - tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode))); + get_cpu_vsrh(xh, xA(ctx->opcode)); } else { - tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode))); + get_cpu_vsrl(xh, xA(ctx->opcode)); } if ((DM(ctx->opcode) & 1) == 0) { - tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode))); + get_cpu_vsrh(xl, xB(ctx->opcode)); } else { - tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode))); + get_cpu_vsrl(xl, xB(ctx->opcode)); } - tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh); - tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl); - - tcg_temp_free_i64(xh); - tcg_temp_free_i64(xl); + set_cpu_vsrh(xT(ctx->opcode), xh); + set_cpu_vsrl(xT(ctx->opcode), xl); } else { if ((DM(ctx->opcode) & 2) == 0) { - tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode))); + get_cpu_vsrh(xh, xA(ctx->opcode)); + set_cpu_vsrh(xT(ctx->opcode), xh); } else { - tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode))); + get_cpu_vsrl(xh, xA(ctx->opcode)); + set_cpu_vsrh(xT(ctx->opcode), xh); } if ((DM(ctx->opcode) & 1) == 0) { - tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode))); + get_cpu_vsrh(xl, xB(ctx->opcode)); + set_cpu_vsrl(xT(ctx->opcode), xl); } else { - tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode))); + get_cpu_vsrl(xl, xB(ctx->opcode)); + set_cpu_vsrl(xT(ctx->opcode), xl); } } + tcg_temp_free_i64(xh); + tcg_temp_free_i64(xl); } #define OP_ABS 1 @@ -606,7 +786,7 @@ static void glue(gen_, name)(DisasContext * ctx) \ } \ xb = tcg_temp_new_i64(); \ sgm = tcg_temp_new_i64(); \ - tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \ + get_cpu_vsrh(xb, xB(ctx->opcode)); \ tcg_gen_movi_i64(sgm, sgn_mask); \ switch (op) { \ case OP_ABS: { \ @@ -623,7 +803,7 @@ static void glue(gen_, name)(DisasContext * ctx) \ } \ case OP_CPSGN: { \ TCGv_i64 xa = tcg_temp_new_i64(); \ - tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \ + get_cpu_vsrh(xa, xA(ctx->opcode)); \ tcg_gen_and_i64(xa, xa, sgm); \ tcg_gen_andc_i64(xb, xb, sgm); \ tcg_gen_or_i64(xb, xb, xa); \ @@ -631,7 +811,7 @@ static void glue(gen_, name)(DisasContext * ctx) \ break; \ } \ } \ - tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \ + set_cpu_vsrh(xT(ctx->opcode), xb); \ tcg_temp_free_i64(xb); \ tcg_temp_free_i64(sgm); \ } @@ -647,7 +827,7 @@ static void glue(gen_, name)(DisasContext *ctx) \ int xa; \ int xt = rD(ctx->opcode) + 32; \ int xb = rB(ctx->opcode) + 32; \ - TCGv_i64 xah, xbh, xbl, sgm; \ + TCGv_i64 xah, xbh, xbl, sgm, tmp; \ \ if (unlikely(!ctx->vsx_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ @@ -656,8 +836,9 @@ static void glue(gen_, name)(DisasContext *ctx) \ xbh = tcg_temp_new_i64(); \ xbl = tcg_temp_new_i64(); \ sgm = tcg_temp_new_i64(); \ - tcg_gen_mov_i64(xbh, cpu_vsrh(xb)); \ - tcg_gen_mov_i64(xbl, cpu_vsrl(xb)); \ + tmp = tcg_temp_new_i64(); \ + get_cpu_vsrh(xbh, xb); \ + get_cpu_vsrl(xbl, xb); \ tcg_gen_movi_i64(sgm, sgn_mask); \ switch (op) { \ case OP_ABS: \ @@ -672,17 +853,19 @@ static void glue(gen_, name)(DisasContext *ctx) \ case OP_CPSGN: \ xah = tcg_temp_new_i64(); \ xa = rA(ctx->opcode) + 32; \ - tcg_gen_and_i64(xah, cpu_vsrh(xa), sgm); \ + get_cpu_vsrh(tmp, xa); \ + tcg_gen_and_i64(xah, tmp, sgm); \ tcg_gen_andc_i64(xbh, xbh, sgm); \ tcg_gen_or_i64(xbh, xbh, xah); \ tcg_temp_free_i64(xah); \ break; \ } \ - tcg_gen_mov_i64(cpu_vsrh(xt), xbh); \ - tcg_gen_mov_i64(cpu_vsrl(xt), xbl); \ + set_cpu_vsrh(xt, xbh); \ + set_cpu_vsrl(xt, xbl); \ tcg_temp_free_i64(xbl); \ tcg_temp_free_i64(xbh); \ tcg_temp_free_i64(sgm); \ + tcg_temp_free_i64(tmp); \ } VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP) @@ -701,8 +884,8 @@ static void glue(gen_, name)(DisasContext * ctx) \ xbh = tcg_temp_new_i64(); \ xbl = tcg_temp_new_i64(); \ sgm = tcg_temp_new_i64(); \ - tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \ - tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \ + set_cpu_vsrh(xB(ctx->opcode), xbh); \ + set_cpu_vsrl(xB(ctx->opcode), xbl); \ tcg_gen_movi_i64(sgm, sgn_mask); \ switch (op) { \ case OP_ABS: { \ @@ -723,8 +906,8 @@ static void glue(gen_, name)(DisasContext * ctx) \ case OP_CPSGN: { \ TCGv_i64 xah = tcg_temp_new_i64(); \ TCGv_i64 xal = tcg_temp_new_i64(); \ - tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \ - tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \ + get_cpu_vsrh(xah, xA(ctx->opcode)); \ + get_cpu_vsrl(xal, xA(ctx->opcode)); \ tcg_gen_and_i64(xah, xah, sgm); \ tcg_gen_and_i64(xal, xal, sgm); \ tcg_gen_andc_i64(xbh, xbh, sgm); \ @@ -736,8 +919,8 @@ static void glue(gen_, name)(DisasContext * ctx) \ break; \ } \ } \ - tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \ - tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \ + set_cpu_vsrh(xT(ctx->opcode), xbh); \ + set_cpu_vsrl(xT(ctx->opcode), xbl); \ tcg_temp_free_i64(xbh); \ tcg_temp_free_i64(xbl); \ tcg_temp_free_i64(sgm); \ @@ -768,12 +951,19 @@ static void gen_##name(DisasContext * ctx) \ #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ static void gen_##name(DisasContext * ctx) \ { \ + TCGv_i64 t0; \ + TCGv_i64 t1; \ if (unlikely(!ctx->vsx_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ } \ - gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \ - cpu_vsrh(xB(ctx->opcode))); \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ + get_cpu_vsrh(t0, xB(ctx->opcode)); \ + gen_helper_##name(t1, cpu_env, t0); \ + set_cpu_vsrh(xT(ctx->opcode), t1); \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ } GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX) @@ -949,76 +1139,146 @@ GEN_VSX_HELPER_2(xxpermr, 0x08, 0x07, 0, PPC2_ISA300) static void gen_xxbrd(DisasContext *ctx) { - TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode)); + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; + TCGv_i64 xbl; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + tcg_gen_bswap64_i64(xth, xbh); tcg_gen_bswap64_i64(xtl, xbl); + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } static void gen_xxbrh(DisasContext *ctx) { - TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode)); + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; + TCGv_i64 xbl; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + gen_bswap16x8(xth, xtl, xbh, xbl); + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } static void gen_xxbrq(DisasContext *ctx) { - TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode)); - TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; + TCGv_i64 xbl; + TCGv_i64 t0; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + t0 = tcg_temp_new_i64(); + tcg_gen_bswap64_i64(t0, xbl); tcg_gen_bswap64_i64(xtl, xbh); + set_cpu_vsrl(xT(ctx->opcode), xtl); tcg_gen_mov_i64(xth, t0); + set_cpu_vsrl(xT(ctx->opcode), xth); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } static void gen_xxbrw(DisasContext *ctx) { - TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode)); + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; + TCGv_i64 xbl; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + gen_bswap32x4(xth, xtl, xbh, xbl); + set_cpu_vsrl(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } #define VSX_LOGICAL(name, tcg_op) \ static void glue(gen_, name)(DisasContext * ctx) \ { \ + TCGv_i64 t0; \ + TCGv_i64 t1; \ + TCGv_i64 t2; \ if (unlikely(!ctx->vsx_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ } \ - tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \ - cpu_vsrh(xB(ctx->opcode))); \ - tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \ - cpu_vsrl(xB(ctx->opcode))); \ + t0 = tcg_temp_new_i64(); \ + t1 = tcg_temp_new_i64(); \ + t2 = tcg_temp_new_i64(); \ + get_cpu_vsrh(t0, xA(ctx->opcode)); \ + get_cpu_vsrh(t1, xB(ctx->opcode)); \ + tcg_op(t2, t0, t1); \ + set_cpu_vsrh(xT(ctx->opcode), t2); \ + get_cpu_vsrl(t0, xA(ctx->opcode)); \ + get_cpu_vsrl(t1, xB(ctx->opcode)); \ + tcg_op(t2, t0, t1); \ + set_cpu_vsrl(xT(ctx->opcode), t2); \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ + tcg_temp_free_i64(t2); \ } VSX_LOGICAL(xxland, tcg_gen_and_i64) @@ -1033,7 +1293,7 @@ VSX_LOGICAL(xxlorc, tcg_gen_orc_i64) #define VSX_XXMRG(name, high) \ static void glue(gen_, name)(DisasContext * ctx) \ { \ - TCGv_i64 a0, a1, b0, b1; \ + TCGv_i64 a0, a1, b0, b1, tmp; \ if (unlikely(!ctx->vsx_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ @@ -1042,27 +1302,29 @@ static void glue(gen_, name)(DisasContext * ctx) \ a1 = tcg_temp_new_i64(); \ b0 = tcg_temp_new_i64(); \ b1 = tcg_temp_new_i64(); \ + tmp = tcg_temp_new_i64(); \ if (high) { \ - tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \ - tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \ - tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \ - tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \ + get_cpu_vsrh(a0, xA(ctx->opcode)); \ + get_cpu_vsrh(a1, xA(ctx->opcode)); \ + get_cpu_vsrh(b0, xB(ctx->opcode)); \ + get_cpu_vsrh(b1, xB(ctx->opcode)); \ } else { \ - tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \ - tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \ - tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \ - tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \ + get_cpu_vsrl(a0, xA(ctx->opcode)); \ + get_cpu_vsrl(a1, xA(ctx->opcode)); \ + get_cpu_vsrl(b0, xB(ctx->opcode)); \ + get_cpu_vsrl(b1, xB(ctx->opcode)); \ } \ tcg_gen_shri_i64(a0, a0, 32); \ tcg_gen_shri_i64(b0, b0, 32); \ - tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \ - b0, a0, 32, 32); \ - tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \ - b1, a1, 32, 32); \ + tcg_gen_deposit_i64(tmp, b0, a0, 32, 32); \ + set_cpu_vsrh(xT(ctx->opcode), tmp); \ + tcg_gen_deposit_i64(tmp, b1, a1, 32, 32); \ + set_cpu_vsrl(xT(ctx->opcode), tmp); \ tcg_temp_free_i64(a0); \ tcg_temp_free_i64(a1); \ tcg_temp_free_i64(b0); \ tcg_temp_free_i64(b1); \ + tcg_temp_free_i64(tmp); \ } VSX_XXMRG(xxmrghw, 1) @@ -1070,7 +1332,7 @@ VSX_XXMRG(xxmrglw, 0) static void gen_xxsel(DisasContext * ctx) { - TCGv_i64 a, b, c; + TCGv_i64 a, b, c, tmp; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; @@ -1078,40 +1340,49 @@ static void gen_xxsel(DisasContext * ctx) a = tcg_temp_new_i64(); b = tcg_temp_new_i64(); c = tcg_temp_new_i64(); + tmp = tcg_temp_new_i64(); - tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode))); - tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode))); - tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode))); + get_cpu_vsrh(a, xA(ctx->opcode)); + get_cpu_vsrh(b, xB(ctx->opcode)); + get_cpu_vsrh(c, xC(ctx->opcode)); tcg_gen_and_i64(b, b, c); tcg_gen_andc_i64(a, a, c); - tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b); + tcg_gen_or_i64(tmp, a, b); + set_cpu_vsrh(xT(ctx->opcode), tmp); - tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode))); - tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode))); - tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode))); + get_cpu_vsrl(a, xA(ctx->opcode)); + get_cpu_vsrl(b, xB(ctx->opcode)); + get_cpu_vsrl(c, xC(ctx->opcode)); tcg_gen_and_i64(b, b, c); tcg_gen_andc_i64(a, a, c); - tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b); + tcg_gen_or_i64(tmp, a, b); + set_cpu_vsrl(xT(ctx->opcode), tmp); tcg_temp_free_i64(a); tcg_temp_free_i64(b); tcg_temp_free_i64(c); + tcg_temp_free_i64(tmp); } static void gen_xxspltw(DisasContext *ctx) { TCGv_i64 b, b2; - TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ? - cpu_vsrl(xB(ctx->opcode)) : - cpu_vsrh(xB(ctx->opcode)); + TCGv_i64 vsr; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + vsr = tcg_temp_new_i64(); + if (UIM(ctx->opcode) & 2) { + get_cpu_vsrl(vsr, xB(ctx->opcode)); + } else { + get_cpu_vsrh(vsr, xB(ctx->opcode)); + } + b = tcg_temp_new_i64(); b2 = tcg_temp_new_i64(); @@ -1122,9 +1393,11 @@ static void gen_xxspltw(DisasContext *ctx) } tcg_gen_shli_i64(b2, b, 32); - tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2); - tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode))); + tcg_gen_or_i64(vsr, b, b2); + set_cpu_vsrh(xT(ctx->opcode), vsr); + set_cpu_vsrl(xT(ctx->opcode), vsr); + tcg_temp_free_i64(vsr); tcg_temp_free_i64(b); tcg_temp_free_i64(b2); } @@ -1134,6 +1407,7 @@ static void gen_xxspltw(DisasContext *ctx) static void gen_xxspltib(DisasContext *ctx) { unsigned char uim8 = IMM8(ctx->opcode); + TCGv_i64 vsr; if (xS(ctx->opcode) < 32) { if (unlikely(!ctx->altivec_enabled)) { gen_exception(ctx, POWERPC_EXCP_VPU); @@ -1145,8 +1419,11 @@ static void gen_xxspltib(DisasContext *ctx) return; } } - tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), pattern(uim8)); - tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), pattern(uim8)); + vsr = tcg_temp_new_i64(); + tcg_gen_movi_i64(vsr, pattern(uim8)); + set_cpu_vsrh(xT(ctx->opcode), vsr); + set_cpu_vsrl(xT(ctx->opcode), vsr); + tcg_temp_free_i64(vsr); } static void gen_xxsldwi(DisasContext *ctx) @@ -1161,40 +1438,40 @@ static void gen_xxsldwi(DisasContext *ctx) switch (SHW(ctx->opcode)) { case 0: { - tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode))); - tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode))); + get_cpu_vsrh(xth, xA(ctx->opcode)); + get_cpu_vsrl(xtl, xA(ctx->opcode)); break; } case 1: { TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode))); + get_cpu_vsrh(xth, xA(ctx->opcode)); tcg_gen_shli_i64(xth, xth, 32); - tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode))); + get_cpu_vsrl(t0, xA(ctx->opcode)); tcg_gen_shri_i64(t0, t0, 32); tcg_gen_or_i64(xth, xth, t0); - tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode))); + get_cpu_vsrl(xtl, xA(ctx->opcode)); tcg_gen_shli_i64(xtl, xtl, 32); - tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode))); + get_cpu_vsrh(t0, xB(ctx->opcode)); tcg_gen_shri_i64(t0, t0, 32); tcg_gen_or_i64(xtl, xtl, t0); tcg_temp_free_i64(t0); break; } case 2: { - tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode))); - tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode))); + get_cpu_vsrl(xth, xA(ctx->opcode)); + get_cpu_vsrh(xtl, xB(ctx->opcode)); break; } case 3: { TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode))); + get_cpu_vsrl(xth, xA(ctx->opcode)); tcg_gen_shli_i64(xth, xth, 32); - tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode))); + get_cpu_vsrh(t0, xB(ctx->opcode)); tcg_gen_shri_i64(t0, t0, 32); tcg_gen_or_i64(xth, xth, t0); - tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode))); + get_cpu_vsrh(xtl, xB(ctx->opcode)); tcg_gen_shli_i64(xtl, xtl, 32); - tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode))); + get_cpu_vsrl(t0, xB(ctx->opcode)); tcg_gen_shri_i64(t0, t0, 32); tcg_gen_or_i64(xtl, xtl, t0); tcg_temp_free_i64(t0); @@ -1202,8 +1479,8 @@ static void gen_xxsldwi(DisasContext *ctx) } } - tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth); - tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl); + set_cpu_vsrh(xT(ctx->opcode), xth); + set_cpu_vsrl(xT(ctx->opcode), xtl); tcg_temp_free_i64(xth); tcg_temp_free_i64(xtl); @@ -1213,7 +1490,8 @@ static void gen_xxsldwi(DisasContext *ctx) static void gen_##name(DisasContext *ctx) \ { \ TCGv xt, xb; \ - TCGv_i32 t0 = tcg_temp_new_i32(); \ + TCGv_i32 t0; \ + TCGv_i64 t1; \ uint8_t uimm = UIMM4(ctx->opcode); \ \ if (unlikely(!ctx->vsx_enabled)) { \ @@ -1222,12 +1500,15 @@ static void gen_##name(DisasContext *ctx) \ } \ xt = tcg_const_tl(xT(ctx->opcode)); \ xb = tcg_const_tl(xB(ctx->opcode)); \ + t0 = tcg_temp_new_i32(); \ + t1 = tcg_temp_new_i64(); \ /* uimm > 15 out of bound and for \ * uimm > 12 handle as per hardware in helper \ */ \ if (uimm > 15) { \ - tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); \ - tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), 0); \ + tcg_gen_movi_i64(t1, 0); \ + set_cpu_vsrh(xT(ctx->opcode), t1); \ + set_cpu_vsrl(xT(ctx->opcode), t1); \ return; \ } \ tcg_gen_movi_i32(t0, uimm); \ @@ -1235,6 +1516,7 @@ static void gen_##name(DisasContext *ctx) \ tcg_temp_free(xb); \ tcg_temp_free(xt); \ tcg_temp_free_i32(t0); \ + tcg_temp_free_i64(t1); \ } VSX_EXTRACT_INSERT(xxextractuw) @@ -1244,30 +1526,45 @@ VSX_EXTRACT_INSERT(xxinsertw) static void gen_xsxexpdp(DisasContext *ctx) { TCGv rt = cpu_gpr[rD(ctx->opcode)]; + TCGv_i64 t0; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } - tcg_gen_extract_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52, 11); + t0 = tcg_temp_new_i64(); + get_cpu_vsrh(t0, xB(ctx->opcode)); + tcg_gen_extract_i64(rt, t0, 52, 11); + tcg_temp_free_i64(t0); } static void gen_xsxexpqp(DisasContext *ctx) { - TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32); - TCGv_i64 xtl = cpu_vsrl(rD(ctx->opcode) + 32); - TCGv_i64 xbh = cpu_vsrh(rB(ctx->opcode) + 32); + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, rB(ctx->opcode) + 32); + tcg_gen_extract_i64(xth, xbh, 48, 15); + set_cpu_vsrh(rD(ctx->opcode) + 32, xth); tcg_gen_movi_i64(xtl, 0); + set_cpu_vsrl(rD(ctx->opcode) + 32, xtl); + + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); } static void gen_xsiexpdp(DisasContext *ctx) { - TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); + TCGv_i64 xth; TCGv ra = cpu_gpr[rA(ctx->opcode)]; TCGv rb = cpu_gpr[rB(ctx->opcode)]; TCGv_i64 t0; @@ -1277,40 +1574,60 @@ static void gen_xsiexpdp(DisasContext *ctx) return; } t0 = tcg_temp_new_i64(); + xth = tcg_temp_new_i64(); tcg_gen_andi_i64(xth, ra, 0x800FFFFFFFFFFFFF); tcg_gen_andi_i64(t0, rb, 0x7FF); tcg_gen_shli_i64(t0, t0, 52); tcg_gen_or_i64(xth, xth, t0); + set_cpu_vsrh(xT(ctx->opcode), xth); /* dword[1] is undefined */ tcg_temp_free_i64(t0); + tcg_temp_free_i64(xth); } static void gen_xsiexpqp(DisasContext *ctx) { - TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32); - TCGv_i64 xtl = cpu_vsrl(rD(ctx->opcode) + 32); - TCGv_i64 xah = cpu_vsrh(rA(ctx->opcode) + 32); - TCGv_i64 xal = cpu_vsrl(rA(ctx->opcode) + 32); - TCGv_i64 xbh = cpu_vsrh(rB(ctx->opcode) + 32); + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xah; + TCGv_i64 xal; + TCGv_i64 xbh; TCGv_i64 t0; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xah = tcg_temp_new_i64(); + xal = tcg_temp_new_i64(); + get_cpu_vsrh(xah, rA(ctx->opcode) + 32); + get_cpu_vsrl(xal, rA(ctx->opcode) + 32); + xbh = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, rB(ctx->opcode) + 32); t0 = tcg_temp_new_i64(); + tcg_gen_andi_i64(xth, xah, 0x8000FFFFFFFFFFFF); tcg_gen_andi_i64(t0, xbh, 0x7FFF); tcg_gen_shli_i64(t0, t0, 48); tcg_gen_or_i64(xth, xth, t0); + set_cpu_vsrh(rD(ctx->opcode) + 32, xth); tcg_gen_mov_i64(xtl, xal); + set_cpu_vsrl(rD(ctx->opcode) + 32, xtl); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xah); + tcg_temp_free_i64(xal); + tcg_temp_free_i64(xbh); } static void gen_xsxsigdp(DisasContext *ctx) { TCGv rt = cpu_gpr[rD(ctx->opcode)]; - TCGv_i64 t0, zr, nan, exp; + TCGv_i64 t0, t1, zr, nan, exp; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); @@ -1318,17 +1635,21 @@ static void gen_xsxsigdp(DisasContext *ctx) } exp = tcg_temp_new_i64(); t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); zr = tcg_const_i64(0); nan = tcg_const_i64(2047); - tcg_gen_extract_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52, 11); + get_cpu_vsrh(t1, xB(ctx->opcode)); + tcg_gen_extract_i64(exp, t1, 52, 11); tcg_gen_movi_i64(t0, 0x0010000000000000); tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); - tcg_gen_andi_i64(rt, cpu_vsrh(xB(ctx->opcode)), 0x000FFFFFFFFFFFFF); + get_cpu_vsrh(t1, xB(ctx->opcode)); + tcg_gen_andi_i64(rt, t1, 0x000FFFFFFFFFFFFF); tcg_gen_or_i64(rt, rt, t0); tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); tcg_temp_free_i64(exp); tcg_temp_free_i64(zr); tcg_temp_free_i64(nan); @@ -1337,132 +1658,219 @@ static void gen_xsxsigdp(DisasContext *ctx) static void gen_xsxsigqp(DisasContext *ctx) { TCGv_i64 t0, zr, nan, exp; - TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32); - TCGv_i64 xtl = cpu_vsrl(rD(ctx->opcode) + 32); + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; + TCGv_i64 xbl; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, rB(ctx->opcode) + 32); + get_cpu_vsrl(xbl, rB(ctx->opcode) + 32); exp = tcg_temp_new_i64(); t0 = tcg_temp_new_i64(); zr = tcg_const_i64(0); nan = tcg_const_i64(32767); - tcg_gen_extract_i64(exp, cpu_vsrh(rB(ctx->opcode) + 32), 48, 15); + tcg_gen_extract_i64(exp, xbh, 48, 15); tcg_gen_movi_i64(t0, 0x0001000000000000); tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); - tcg_gen_andi_i64(xth, cpu_vsrh(rB(ctx->opcode) + 32), 0x0000FFFFFFFFFFFF); + tcg_gen_andi_i64(xth, xbh, 0x0000FFFFFFFFFFFF); tcg_gen_or_i64(xth, xth, t0); - tcg_gen_mov_i64(xtl, cpu_vsrl(rB(ctx->opcode) + 32)); + set_cpu_vsrh(rD(ctx->opcode) + 32, xth); + tcg_gen_mov_i64(xtl, xbl); + set_cpu_vsrl(rD(ctx->opcode) + 32, xtl); tcg_temp_free_i64(t0); tcg_temp_free_i64(exp); tcg_temp_free_i64(zr); tcg_temp_free_i64(nan); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } #endif static void gen_xviexpsp(DisasContext *ctx) { - TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xah = cpu_vsrh(xA(ctx->opcode)); - TCGv_i64 xal = cpu_vsrl(xA(ctx->opcode)); - TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode)); + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xah; + TCGv_i64 xal; + TCGv_i64 xbh; + TCGv_i64 xbl; TCGv_i64 t0; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xah = tcg_temp_new_i64(); + xal = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xah, xA(ctx->opcode)); + get_cpu_vsrl(xal, xA(ctx->opcode)); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); t0 = tcg_temp_new_i64(); + tcg_gen_andi_i64(xth, xah, 0x807FFFFF807FFFFF); tcg_gen_andi_i64(t0, xbh, 0xFF000000FF); tcg_gen_shli_i64(t0, t0, 23); tcg_gen_or_i64(xth, xth, t0); + set_cpu_vsrh(xT(ctx->opcode), xth); tcg_gen_andi_i64(xtl, xal, 0x807FFFFF807FFFFF); tcg_gen_andi_i64(t0, xbl, 0xFF000000FF); tcg_gen_shli_i64(t0, t0, 23); tcg_gen_or_i64(xtl, xtl, t0); + set_cpu_vsrl(xT(ctx->opcode), xtl); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xah); + tcg_temp_free_i64(xal); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } static void gen_xviexpdp(DisasContext *ctx) { - TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xah = cpu_vsrh(xA(ctx->opcode)); - TCGv_i64 xal = cpu_vsrl(xA(ctx->opcode)); - TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode)); + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xah; + TCGv_i64 xal; + TCGv_i64 xbh; + TCGv_i64 xbl; TCGv_i64 t0; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xah = tcg_temp_new_i64(); + xal = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xah, xA(ctx->opcode)); + get_cpu_vsrl(xal, xA(ctx->opcode)); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); t0 = tcg_temp_new_i64(); + tcg_gen_andi_i64(xth, xah, 0x800FFFFFFFFFFFFF); tcg_gen_andi_i64(t0, xbh, 0x7FF); tcg_gen_shli_i64(t0, t0, 52); tcg_gen_or_i64(xth, xth, t0); + set_cpu_vsrh(xT(ctx->opcode), xth); tcg_gen_andi_i64(xtl, xal, 0x800FFFFFFFFFFFFF); tcg_gen_andi_i64(t0, xbl, 0x7FF); tcg_gen_shli_i64(t0, t0, 52); tcg_gen_or_i64(xtl, xtl, t0); + set_cpu_vsrl(xT(ctx->opcode), xtl); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xah); + tcg_temp_free_i64(xal); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } static void gen_xvxexpsp(DisasContext *ctx) { - TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode)); + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; + TCGv_i64 xbl; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + tcg_gen_shri_i64(xth, xbh, 23); tcg_gen_andi_i64(xth, xth, 0xFF000000FF); + set_cpu_vsrh(xT(ctx->opcode), xth); tcg_gen_shri_i64(xtl, xbl, 23); tcg_gen_andi_i64(xtl, xtl, 0xFF000000FF); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } static void gen_xvxexpdp(DisasContext *ctx) { - TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode)); + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; + TCGv_i64 xbl; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); + tcg_gen_extract_i64(xth, xbh, 52, 11); + set_cpu_vsrh(xT(ctx->opcode), xth); tcg_gen_extract_i64(xtl, xbl, 52, 11); + set_cpu_vsrl(xT(ctx->opcode), xtl); + + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } GEN_VSX_HELPER_2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300) static void gen_xvxsigdp(DisasContext *ctx) { - TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); - TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); - TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode)); - TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode)); - + TCGv_i64 xth; + TCGv_i64 xtl; + TCGv_i64 xbh; + TCGv_i64 xbl; TCGv_i64 t0, zr, nan, exp; if (unlikely(!ctx->vsx_enabled)) { gen_exception(ctx, POWERPC_EXCP_VSXU); return; } + xth = tcg_temp_new_i64(); + xtl = tcg_temp_new_i64(); + xbh = tcg_temp_new_i64(); + xbl = tcg_temp_new_i64(); + get_cpu_vsrh(xbh, xB(ctx->opcode)); + get_cpu_vsrl(xbl, xB(ctx->opcode)); exp = tcg_temp_new_i64(); t0 = tcg_temp_new_i64(); zr = tcg_const_i64(0); @@ -1474,6 +1882,7 @@ static void gen_xvxsigdp(DisasContext *ctx) tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); tcg_gen_andi_i64(xth, xbh, 0x000FFFFFFFFFFFFF); tcg_gen_or_i64(xth, xth, t0); + set_cpu_vsrh(xT(ctx->opcode), xth); tcg_gen_extract_i64(exp, xbl, 52, 11); tcg_gen_movi_i64(t0, 0x0010000000000000); @@ -1481,11 +1890,16 @@ static void gen_xvxsigdp(DisasContext *ctx) tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); tcg_gen_andi_i64(xtl, xbl, 0x000FFFFFFFFFFFFF); tcg_gen_or_i64(xtl, xtl, t0); + set_cpu_vsrl(xT(ctx->opcode), xtl); tcg_temp_free_i64(t0); tcg_temp_free_i64(exp); tcg_temp_free_i64(zr); tcg_temp_free_i64(nan); + tcg_temp_free_i64(xth); + tcg_temp_free_i64(xtl); + tcg_temp_free_i64(xbh); + tcg_temp_free_i64(xbl); } #undef GEN_XX2FORM diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 03f1d34a97..ade06cc773 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -9486,7 +9486,7 @@ static bool avr_need_swap(CPUPPCState *env) static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) { if (n < 32) { - stfq_p(mem_buf, env->fpr[n]); + stfq_p(mem_buf, *cpu_fpr_ptr(env, n)); ppc_maybe_bswap_register(env, mem_buf, 8); return 8; } @@ -9502,7 +9502,7 @@ static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) { if (n < 32) { ppc_maybe_bswap_register(env, mem_buf, 8); - env->fpr[n] = ldfq_p(mem_buf); + *cpu_fpr_ptr(env, n) = ldfq_p(mem_buf); return 8; } if (n == 32) { @@ -9516,12 +9516,13 @@ static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) { if (n < 32) { + ppc_avr_t *avr = cpu_avr_ptr(env, n); if (!avr_need_swap(env)) { - stq_p(mem_buf, env->avr[n].u64[0]); - stq_p(mem_buf+8, env->avr[n].u64[1]); + stq_p(mem_buf, avr->u64[0]); + stq_p(mem_buf + 8, avr->u64[1]); } else { - stq_p(mem_buf, env->avr[n].u64[1]); - stq_p(mem_buf+8, env->avr[n].u64[0]); + stq_p(mem_buf, avr->u64[1]); + stq_p(mem_buf + 8, avr->u64[0]); } ppc_maybe_bswap_register(env, mem_buf, 8); ppc_maybe_bswap_register(env, mem_buf + 8, 8); @@ -9543,14 +9544,15 @@ static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) { if (n < 32) { + ppc_avr_t *avr = cpu_avr_ptr(env, n); ppc_maybe_bswap_register(env, mem_buf, 8); ppc_maybe_bswap_register(env, mem_buf + 8, 8); if (!avr_need_swap(env)) { - env->avr[n].u64[0] = ldq_p(mem_buf); - env->avr[n].u64[1] = ldq_p(mem_buf+8); + avr->u64[0] = ldq_p(mem_buf); + avr->u64[1] = ldq_p(mem_buf + 8); } else { - env->avr[n].u64[1] = ldq_p(mem_buf); - env->avr[n].u64[0] = ldq_p(mem_buf+8); + avr->u64[1] = ldq_p(mem_buf); + avr->u64[0] = ldq_p(mem_buf + 8); } return 16; } @@ -9623,7 +9625,7 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n) { if (n < 32) { - stq_p(mem_buf, env->vsr[n]); + stq_p(mem_buf, *cpu_vsrl_ptr(env, n)); ppc_maybe_bswap_register(env, mem_buf, 8); return 8; } @@ -9634,7 +9636,7 @@ static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n) { if (n < 32) { ppc_maybe_bswap_register(env, mem_buf, 8); - env->vsr[n] = ldq_p(mem_buf); + *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf); return 8; } return 0; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 0f090ece54..4a4445bdf5 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -111,7 +111,6 @@ cpu_add_feat_as_prop(const char *typename, const char *name, const char *val) prop->driver = typename; prop->property = g_strdup(name); prop->value = g_strdup(val); - prop->errp = &error_fatal; qdev_prop_register_global(prop); } diff --git a/tests/Makefile.include b/tests/Makefile.include index 3f5a1d0c30..9c84bbd829 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -277,6 +277,7 @@ check-qtest-sparc64-y += tests/boot-serial-test$(EXESUF) check-qtest-arm-y += tests/tmp105-test$(EXESUF) check-qtest-arm-y += tests/pca9552-test$(EXESUF) check-qtest-arm-y += tests/ds1338-test$(EXESUF) +check-qtest-arm-y += tests/microbit-test$(EXESUF) check-qtest-arm-y += tests/m25p80-test$(EXESUF) check-qtest-arm-y += tests/virtio-blk-test$(EXESUF) check-qtest-arm-y += tests/test-arm-mptimer$(EXESUF) @@ -708,6 +709,7 @@ tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y) tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y) tests/pca9552-test$(EXESUF): tests/pca9552-test.o $(libqos-omap-obj-y) tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y) +tests/microbit-test$(EXESUF): tests/microbit-test.o tests/m25p80-test$(EXESUF): tests/m25p80-test.o tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y) tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y) diff --git a/tests/docker/dockerfiles/debian-sid.docker b/tests/docker/dockerfiles/debian-sid.docker index 9a3d168705..4e4cda0ba5 100644 --- a/tests/docker/dockerfiles/debian-sid.docker +++ b/tests/docker/dockerfiles/debian-sid.docker @@ -13,6 +13,10 @@ FROM debian:sid-slim +# Use a snapshot known to work (see http://snapshot.debian.org/#Usage) +ENV DEBIAN_SNAPSHOT_DATE "20181030" +RUN sed -i "s%^deb \(https\?://\)deb.debian.org/debian/\? \(.*\)%deb [check-valid-until=no] \1snapshot.debian.org/archive/debian/${DEBIAN_SNAPSHOT_DATE} \2%" /etc/apt/sources.list + # Duplicate deb line as deb-src RUN cat /etc/apt/sources.list | sed "s/^deb\ /deb-src /" >> /etc/apt/sources.list diff --git a/tests/libqtest.c b/tests/libqtest.c index 1d75d3c936..55750dd68d 100644 --- a/tests/libqtest.c +++ b/tests/libqtest.c @@ -753,6 +753,16 @@ void qtest_irq_intercept_in(QTestState *s, const char *qom_path) qtest_rsp(s, 0); } +void qtest_set_irq_in(QTestState *s, const char *qom_path, const char *name, + int num, int level) +{ + if (!name) { + name = "unnamed-gpio-in"; + } + qtest_sendf(s, "set_irq_in %s %s %d %d\n", qom_path, name, num, level); + qtest_rsp(s, 0); +} + static void qtest_out(QTestState *s, const char *cmd, uint16_t addr, uint32_t value) { qtest_sendf(s, "%s 0x%x 0x%x\n", cmd, addr, value); diff --git a/tests/libqtest.h b/tests/libqtest.h index 9758c51be6..7ea94139b0 100644 --- a/tests/libqtest.h +++ b/tests/libqtest.h @@ -231,6 +231,19 @@ void qtest_irq_intercept_in(QTestState *s, const char *string); void qtest_irq_intercept_out(QTestState *s, const char *string); /** + * qtest_set_irq_in: + * @s: QTestState instance to operate on. + * @string: QOM path of a device + * @name: IRQ name + * @irq: IRQ number + * @level: IRQ level + * + * Force given device/irq GPIO-in pin to the given level. + */ +void qtest_set_irq_in(QTestState *s, const char *string, const char *name, + int irq, int level); + +/** * qtest_outb: * @s: #QTestState instance to operate on. * @addr: I/O port to write to. diff --git a/tests/microbit-test.c b/tests/microbit-test.c new file mode 100644 index 0000000000..0c125535f6 --- /dev/null +++ b/tests/microbit-test.c @@ -0,0 +1,255 @@ +/* + * QTest testcase for Microbit board using the Nordic Semiconductor nRF51 SoC. + * + * nRF51: + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf + * + * Microbit Board: http://microbit.org/ + * + * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de> + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + + +#include "qemu/osdep.h" +#include "exec/hwaddr.h" +#include "libqtest.h" + +#include "hw/arm/nrf51.h" +#include "hw/gpio/nrf51_gpio.h" +#include "hw/timer/nrf51_timer.h" + +static void test_nrf51_gpio(void) +{ + size_t i; + uint32_t actual, expected; + + struct { + hwaddr addr; + uint32_t expected; + } const reset_state[] = { + {NRF51_GPIO_REG_OUT, 0x00000000}, {NRF51_GPIO_REG_OUTSET, 0x00000000}, + {NRF51_GPIO_REG_OUTCLR, 0x00000000}, {NRF51_GPIO_REG_IN, 0x00000000}, + {NRF51_GPIO_REG_DIR, 0x00000000}, {NRF51_GPIO_REG_DIRSET, 0x00000000}, + {NRF51_GPIO_REG_DIRCLR, 0x00000000} + }; + + /* Check reset state */ + for (i = 0; i < ARRAY_SIZE(reset_state); i++) { + expected = reset_state[i].expected; + actual = readl(NRF51_GPIO_BASE + reset_state[i].addr); + g_assert_cmpuint(actual, ==, expected); + } + + for (i = 0; i < NRF51_GPIO_PINS; i++) { + expected = 0x00000002; + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START + i * 4); + g_assert_cmpuint(actual, ==, expected); + } + + /* Check dir bit consistency between dir and cnf */ + /* Check set via DIRSET */ + expected = 0x80000001; + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIRSET, expected); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); + g_assert_cmpuint(actual, ==, expected); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + + /* Check clear via DIRCLR */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIRCLR, 0x80000001); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); + g_assert_cmpuint(actual, ==, 0x00000000); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) & 0x01; + g_assert_cmpuint(actual, ==, 0x00); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; + g_assert_cmpuint(actual, ==, 0x00); + + /* Check set via DIR */ + expected = 0x80000001; + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR, expected); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); + g_assert_cmpuint(actual, ==, expected); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + + /* Reset DIR */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR, 0x00000000); + + /* Check Input propagates */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x00); + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0, 0); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x00); + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0, 1); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0, -1); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); + + /* Check pull-up working */ + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0, 0); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0000); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x00); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b1110); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); + + /* Check pull-down working */ + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0, 1); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0000); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0110); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x00); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0, -1); + + /* Check Output propagates */ + irq_intercept_out("/machine/nrf51"); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0011); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); + g_assert_true(get_irq(0)); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTCLR, 0x01); + g_assert_false(get_irq(0)); + + /* Check self-stimulation */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x01); + + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTCLR, 0x01); + actual = readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + g_assert_cmpuint(actual, ==, 0x00); + + /* + * Check short-circuit - generates an guest_error which must be checked + * manually as long as qtest can not scan qemu_log messages + */ + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b01); + writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); + qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0, 0); +} + +static void timer_task(hwaddr task) +{ + writel(NRF51_TIMER_BASE + task, NRF51_TRIGGER_TASK); +} + +static void timer_clear_event(hwaddr event) +{ + writel(NRF51_TIMER_BASE + event, NRF51_EVENT_CLEAR); +} + +static void timer_set_bitmode(uint8_t mode) +{ + writel(NRF51_TIMER_BASE + NRF51_TIMER_REG_BITMODE, mode); +} + +static void timer_set_prescaler(uint8_t prescaler) +{ + writel(NRF51_TIMER_BASE + NRF51_TIMER_REG_PRESCALER, prescaler); +} + +static void timer_set_cc(size_t idx, uint32_t value) +{ + writel(NRF51_TIMER_BASE + NRF51_TIMER_REG_CC0 + idx * 4, value); +} + +static void timer_assert_events(uint32_t ev0, uint32_t ev1, uint32_t ev2, + uint32_t ev3) +{ + g_assert(readl(NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_0) == ev0); + g_assert(readl(NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_1) == ev1); + g_assert(readl(NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_2) == ev2); + g_assert(readl(NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_3) == ev3); +} + +static void test_nrf51_timer(void) +{ + uint32_t steps_to_overflow = 408; + + /* Compare Match */ + timer_task(NRF51_TIMER_TASK_STOP); + timer_task(NRF51_TIMER_TASK_CLEAR); + + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_0); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_1); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_2); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_3); + + timer_set_bitmode(NRF51_TIMER_WIDTH_16); /* 16 MHz Timer */ + timer_set_prescaler(0); + /* Swept over in first step */ + timer_set_cc(0, 2); + /* Barely miss on first step */ + timer_set_cc(1, 162); + /* Spot on on third step */ + timer_set_cc(2, 480); + + timer_assert_events(0, 0, 0, 0); + + timer_task(NRF51_TIMER_TASK_START); + clock_step(10000); + timer_assert_events(1, 0, 0, 0); + + /* Swept over on first overflow */ + timer_set_cc(3, 114); + + clock_step(10000); + timer_assert_events(1, 1, 0, 0); + + clock_step(10000); + timer_assert_events(1, 1, 1, 0); + + /* Wrap time until internal counter overflows */ + while (steps_to_overflow--) { + timer_assert_events(1, 1, 1, 0); + clock_step(10000); + } + + timer_assert_events(1, 1, 1, 1); + + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_0); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_1); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_2); + timer_clear_event(NRF51_TIMER_EVENT_COMPARE_3); + timer_assert_events(0, 0, 0, 0); + + timer_task(NRF51_TIMER_TASK_STOP); + + /* Test Proposal: Stop/Shutdown */ + /* Test Proposal: Shortcut Compare -> Clear */ + /* Test Proposal: Shortcut Compare -> Stop */ + /* Test Proposal: Counter Mode */ +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + + global_qtest = qtest_initf("-machine microbit"); + + qtest_add_func("/microbit/nrf51/gpio", test_nrf51_gpio); + qtest_add_func("/microbit/nrf51/timer", test_nrf51_timer); + + ret = g_test_run(); + + qtest_quit(global_qtest); + return ret; +} diff --git a/tests/qemu-iotests/083.out b/tests/qemu-iotests/083.out index f9af8bb691..7419722cd7 100644 --- a/tests/qemu-iotests/083.out +++ b/tests/qemu-iotests/083.out @@ -41,8 +41,6 @@ can't open device nbd+tcp://127.0.0.1:PORT/foo === Check disconnect after neg2 === -Unable to read from socket: Connection reset by peer -Connection closed read failed: Input/output error === Check disconnect 8 neg2 === @@ -55,40 +53,30 @@ can't open device nbd+tcp://127.0.0.1:PORT/foo === Check disconnect before request === -Unable to read from socket: Connection reset by peer -Connection closed read failed: Input/output error === Check disconnect after request === -Connection closed read failed: Input/output error === Check disconnect before reply === -Connection closed read failed: Input/output error === Check disconnect after reply === -Unexpected end-of-file before all bytes were read read failed: Input/output error === Check disconnect 4 reply === -Unexpected end-of-file before all bytes were read -Connection closed read failed: Input/output error === Check disconnect 8 reply === -Unexpected end-of-file before all bytes were read -Connection closed read failed: Input/output error === Check disconnect before data === -Unexpected end-of-file before all bytes were read read failed: Input/output error === Check disconnect after data === @@ -118,8 +106,6 @@ can't open device nbd+tcp://127.0.0.1:PORT/ === Check disconnect after neg-classic === -Unable to read from socket: Connection reset by peer -Connection closed read failed: Input/output error === Check disconnect before neg1 === @@ -164,8 +150,6 @@ can't open device nbd+unix:///foo?socket=TEST_DIR/nbd.sock === Check disconnect after neg2 === -Unable to read from socket: Connection reset by peer -Connection closed read failed: Input/output error === Check disconnect 8 neg2 === @@ -178,40 +162,30 @@ can't open device nbd+unix:///foo?socket=TEST_DIR/nbd.sock === Check disconnect before request === -Unable to read from socket: Connection reset by peer -Connection closed read failed: Input/output error === Check disconnect after request === -Connection closed read failed: Input/output error === Check disconnect before reply === -Connection closed read failed: Input/output error === Check disconnect after reply === -Unexpected end-of-file before all bytes were read read failed: Input/output error === Check disconnect 4 reply === -Unexpected end-of-file before all bytes were read -Connection closed read failed: Input/output error === Check disconnect 8 reply === -Unexpected end-of-file before all bytes were read -Connection closed read failed: Input/output error === Check disconnect before data === -Unexpected end-of-file before all bytes were read read failed: Input/output error === Check disconnect after data === @@ -241,8 +215,6 @@ can't open device nbd+unix:///?socket=TEST_DIR/nbd.sock === Check disconnect after neg-classic === -Unable to read from socket: Connection reset by peer -Connection closed read failed: Input/output error *** done diff --git a/tests/qemu-iotests/233.out b/tests/qemu-iotests/233.out index 94acd9b947..5f416721b0 100644 --- a/tests/qemu-iotests/233.out +++ b/tests/qemu-iotests/233.out @@ -27,7 +27,7 @@ virtual size: 64M (67108864 bytes) disk size: unavailable == check TLS with different CA fails == -option negotiation failed: Verify failed: No certificate was found. +qemu-nbd: option negotiation failed: Verify failed: No certificate was found. qemu-img: Could not open 'driver=nbd,host=127.0.0.1,port=PORT,tls-creds=tls0': The certificate hasn't got a known issuer == perform I/O over TLS == diff --git a/tests/test-qdev-global-props.c b/tests/test-qdev-global-props.c index b1eb505442..60231b1372 100644 --- a/tests/test-qdev-global-props.c +++ b/tests/test-qdev-global-props.c @@ -216,12 +216,12 @@ static void test_dynamic_globalprop_subprocess(void) { MyType *mt; static GlobalProperty props[] = { - { TYPE_DYNAMIC_PROPS, "prop1", "101", true }, - { TYPE_DYNAMIC_PROPS, "prop2", "102", true }, - { TYPE_DYNAMIC_PROPS"-bad", "prop3", "103", true }, - { TYPE_UNUSED_HOTPLUG, "prop4", "104", true }, - { TYPE_UNUSED_NOHOTPLUG, "prop5", "105", true }, - { TYPE_NONDEVICE, "prop6", "106", true }, + { TYPE_DYNAMIC_PROPS, "prop1", "101", }, + { TYPE_DYNAMIC_PROPS, "prop2", "102", }, + { TYPE_DYNAMIC_PROPS"-bad", "prop3", "103", }, + { TYPE_UNUSED_HOTPLUG, "prop4", "104", }, + { TYPE_UNUSED_NOHOTPLUG, "prop5", "105", }, + { TYPE_NONDEVICE, "prop6", "106", }, {} }; int global_error; @@ -256,46 +256,6 @@ static void test_dynamic_globalprop(void) g_test_trap_assert_stdout(""); } -/* Test setting of dynamic properties using user_provided=false properties */ -static void test_dynamic_globalprop_nouser_subprocess(void) -{ - MyType *mt; - static GlobalProperty props[] = { - { TYPE_DYNAMIC_PROPS, "prop1", "101" }, - { TYPE_DYNAMIC_PROPS, "prop2", "102" }, - { TYPE_DYNAMIC_PROPS"-bad", "prop3", "103" }, - { TYPE_UNUSED_HOTPLUG, "prop4", "104" }, - { TYPE_UNUSED_NOHOTPLUG, "prop5", "105" }, - { TYPE_NONDEVICE, "prop6", "106" }, - {} - }; - int global_error; - - register_global_properties(props); - - mt = DYNAMIC_TYPE(object_new(TYPE_DYNAMIC_PROPS)); - qdev_init_nofail(DEVICE(mt)); - - g_assert_cmpuint(mt->prop1, ==, 101); - g_assert_cmpuint(mt->prop2, ==, 102); - global_error = qdev_prop_check_globals(); - g_assert_cmpuint(global_error, ==, 0); - g_assert(props[0].used); - g_assert(props[1].used); - g_assert(!props[2].used); - g_assert(!props[3].used); - g_assert(!props[4].used); - g_assert(!props[5].used); -} - -static void test_dynamic_globalprop_nouser(void) -{ - g_test_trap_subprocess("/qdev/properties/dynamic/global/nouser/subprocess", 0, 0); - g_test_trap_assert_passed(); - g_test_trap_assert_stderr(""); - g_test_trap_assert_stdout(""); -} - /* Test if global props affecting subclasses are applied in the right order */ static void test_subclass_global_props(void) { @@ -345,11 +305,6 @@ int main(int argc, char **argv) g_test_add_func("/qdev/properties/dynamic/global", test_dynamic_globalprop); - g_test_add_func("/qdev/properties/dynamic/global/nouser/subprocess", - test_dynamic_globalprop_nouser_subprocess); - g_test_add_func("/qdev/properties/dynamic/global/nouser", - test_dynamic_globalprop_nouser); - g_test_add_func("/qdev/properties/global/subclass", test_subclass_global_props); diff --git a/ui/cocoa.m b/ui/cocoa.m index ecf12bfc2e..ddc058e76e 100644 --- a/ui/cocoa.m +++ b/ui/cocoa.m @@ -32,7 +32,8 @@ #include "ui/input.h" #include "sysemu/sysemu.h" #include "qapi/error.h" -#include "qapi/qapi-commands.h" +#include "qapi/qapi-commands-block.h" +#include "qapi/qapi-commands-misc.h" #include "sysemu/blockdev.h" #include "qemu-version.h" #include <Carbon/Carbon.h> diff --git a/ui/console.c b/ui/console.c index 3a285bae00..7076becedd 100644 --- a/ui/console.c +++ b/ui/console.c @@ -1385,42 +1385,6 @@ DisplaySurface *qemu_create_displaysurface_pixman(pixman_image_t *image) return surface; } -static void qemu_unmap_displaysurface_guestmem(pixman_image_t *image, - void *unused) -{ - void *data = pixman_image_get_data(image); - uint32_t size = pixman_image_get_stride(image) * - pixman_image_get_height(image); - cpu_physical_memory_unmap(data, size, 0, 0); -} - -DisplaySurface *qemu_create_displaysurface_guestmem(int width, int height, - pixman_format_code_t format, - int linesize, uint64_t addr) -{ - DisplaySurface *surface; - hwaddr size; - void *data; - - if (linesize == 0) { - linesize = width * PIXMAN_FORMAT_BPP(format) / 8; - } - - size = (hwaddr)linesize * height; - data = cpu_physical_memory_map(addr, &size, 0); - if (size != (hwaddr)linesize * height) { - cpu_physical_memory_unmap(data, size, 0, 0); - return NULL; - } - - surface = qemu_create_displaysurface_from - (width, height, format, linesize, data); - pixman_image_set_destroy_function - (surface->image, qemu_unmap_displaysurface_guestmem, NULL); - - return surface; -} - DisplaySurface *qemu_create_message_surface(int w, int h, const char *msg) { diff --git a/ui/egl-headless.c b/ui/egl-headless.c index 4cf3bbc0e4..519e7bad32 100644 --- a/ui/egl-headless.c +++ b/ui/egl-headless.c @@ -38,6 +38,14 @@ static void egl_gfx_switch(DisplayChangeListener *dcl, edpy->ds = new_surface; } +static QEMUGLContext egl_create_context(DisplayChangeListener *dcl, + QEMUGLParams *params) +{ + eglMakeCurrent(qemu_egl_display, EGL_NO_SURFACE, EGL_NO_SURFACE, + qemu_egl_rn_ctx); + return qemu_egl_create_context(dcl, params); +} + static void egl_scanout_disable(DisplayChangeListener *dcl) { egl_dpy *edpy = container_of(dcl, egl_dpy, dcl); @@ -150,7 +158,7 @@ static const DisplayChangeListenerOps egl_ops = { .dpy_gfx_update = egl_gfx_update, .dpy_gfx_switch = egl_gfx_switch, - .dpy_gl_ctx_create = qemu_egl_create_context, + .dpy_gl_ctx_create = egl_create_context, .dpy_gl_ctx_destroy = qemu_egl_destroy_context, .dpy_gl_ctx_make_current = qemu_egl_make_context_current, .dpy_gl_ctx_get_current = qemu_egl_get_current_context, diff --git a/ui/keymaps.c b/ui/keymaps.c index 085889b555..6e44f738ed 100644 --- a/ui/keymaps.c +++ b/ui/keymaps.c @@ -115,10 +115,9 @@ static int parse_keyboard_layout(kbd_layout_t *k, continue; } if (!strncmp(line, "include ", 8)) { - if (parse_keyboard_layout(k, table, line + 8, errp) < 0) { - ret = -1; - goto out; - } + error_setg(errp, "keymap include files are not supported any more"); + ret = -1; + goto out; } else { int offset = 0; while (line[offset] != 0 && diff --git a/ui/spice-core.c b/ui/spice-core.c index ebaae24643..a40fb2c00d 100644 --- a/ui/spice-core.c +++ b/ui/spice-core.c @@ -18,7 +18,6 @@ #include "qemu/osdep.h" #include <spice.h> -#include <netdb.h> #include "sysemu/sysemu.h" #include "ui/qemu-spice.h" @@ -745,13 +744,7 @@ void qemu_spice_init(void) } if (qemu_opt_get_bool(opts, "disable-agent-file-xfer", 0)) { -#if SPICE_SERVER_VERSION >= 0x000c04 spice_server_set_agent_file_xfer(spice_server, false); -#else - error_report("this qemu build does not support the " - "\"disable-agent-file-xfer\" option"); - exit(1); -#endif } compression = SPICE_IMAGE_COMPRESS_AUTO_GLZ; @@ -817,9 +810,7 @@ void qemu_spice_init(void) g_free(x509_cert_file); g_free(x509_cacert_file); -#if SPICE_SERVER_VERSION >= 0x000c02 qemu_spice_register_ports(); -#endif #ifdef HAVE_SPICE_GL if (qemu_opt_get_bool(opts, "gl", 0)) { diff --git a/util/qemu-thread-posix.c b/util/qemu-thread-posix.c index 865e476df5..1bf5e65dea 100644 --- a/util/qemu-thread-posix.c +++ b/util/qemu-thread-posix.c @@ -484,12 +484,16 @@ static void *qemu_thread_start(void *args) void *arg = qemu_thread_args->arg; void *r; -#ifdef CONFIG_PTHREAD_SETNAME_NP +#ifdef CONFIG_THREAD_SETNAME_BYTHREAD /* Attempt to set the threads name; note that this is for debug, so * we're not going to fail if we can't set it. */ if (name_threads && qemu_thread_args->name) { +# if defined(CONFIG_PTHREAD_SETNAME_NP_W_TID) pthread_setname_np(pthread_self(), qemu_thread_args->name); +# elif defined(CONFIG_PTHREAD_SETNAME_NP_WO_TID) + pthread_setname_np(qemu_thread_args->name); +# endif } #endif g_free(qemu_thread_args->name); @@ -520,6 +524,11 @@ void qemu_thread_create(QemuThread *thread, const char *name, /* Leave signal handling to the iothread. */ sigfillset(&set); + /* Blocking the signals can result in undefined behaviour. */ + sigdelset(&set, SIGSEGV); + sigdelset(&set, SIGFPE); + sigdelset(&set, SIGILL); + /* TODO avoid SIGBUS loss on macOS */ pthread_sigmask(SIG_SETMASK, &set, &oldset); qemu_thread_args = g_new0(QemuThreadArgs, 1); @@ -2964,8 +2964,6 @@ static int global_init_func(void *opaque, QemuOpts *opts, Error **errp) g->driver = qemu_opt_get(opts, "driver"); g->property = qemu_opt_get(opts, "property"); g->value = qemu_opt_get(opts, "value"); - g->user_provided = true; - g->errp = &error_fatal; qdev_prop_register_global(g); return 0; } @@ -2996,8 +2994,6 @@ static void user_register_global_props(void) */ static void register_global_properties(MachineState *ms) { - accel_register_compat_props(ms->accelerator); - machine_register_compat_props(ms); user_register_global_props(); } |