summaryrefslogtreecommitdiff
path: root/benchmarks
AgeCommit message (Expand)AuthorFilesLines
2017-05-17gem_wsim: Fix client exit with more than one background workloadTvrtko Ursulin1-4/+5
2017-05-17wsim: Only require execbuf wr ioctl for FENCE_OUTChris Wilson1-2/+1
2017-05-16gem_wsim: Implement sw sync point supportTvrtko Ursulin2-9/+120
2017-05-16gem_wsync: Clearer step metadata handlingTvrtko Ursulin1-13/+20
2017-05-16gem_wsim: Fence supportTvrtko Ursulin2-35/+154
2017-05-16gem_wsim: Simplify batch offset block a bitTvrtko Ursulin1-9/+6
2017-05-16gem_wsim: Add append workloadTvrtko Ursulin1-7/+58
2017-05-16gem_wsim: Two small tidiesTvrtko Ursulin1-2/+3
2017-05-11gem_wsim: Minimize startup gapTvrtko Ursulin1-1/+11
2017-05-11wsim: Set the seqno/time stamp on each batch to every engineChris Wilson1-19/+9
2017-05-10wsim: Use a loop over engines to calculate RTChris Wilson1-59/+36
2017-05-10wsim: Feed qd into ewmaChris Wilson1-26/+50
2017-05-10wsim: Switch off heartbeat by defaultChris Wilson1-2/+7
2017-05-10wsim: Limit the information updated during the heartbeatChris Wilson1-33/+51
2017-05-10wsim: Limit heartbeats to sync pointsChris Wilson1-2/+4
2017-05-10wsim: Cache the heartbeat batch and locationChris Wilson1-29/+25
2017-05-10wsim: Avoid the workload_step being tracked simultaneously on multiple enginesChris Wilson1-0/+8
2017-05-10wsim: Stop treating wrk->status_page as just a single uint32_tChris Wilson1-3/+2
2017-05-10gem_wsim: Refactor balancer selection and help textTvrtko Ursulin1-82/+131
2017-05-10gem_wsim: Fix master workload handling and statsTvrtko Ursulin1-40/+51
2017-05-10benchmarks: Make sure ewma.h and ilog2.h are bundled in distPetri Latvala1-0/+6
2017-05-10Revert "autotools requires headers to be listed"Petri Latvala1-2/+0
2017-05-10autotools requires headers to be listedChris Wilson1-0/+2
2017-05-09wsim: Compact the per-engine heartbeat into a single bufferChris Wilson1-12/+24
2017-05-09wsim: Convert the RT multiple reads to a latched readChris Wilson1-14/+35
2017-05-09wsim: Fixup breaking the read loop after the seqno advances.Chris Wilson1-3/+8
2017-05-09wsim: Loop over the multiple u32 reads from the status pageChris Wilson1-16/+43
2017-05-09wsim: qd throttling now works independently of balancer->get_qdChris Wilson1-7/+1
2017-05-09wsim: Introduce verbosityChris Wilson1-48/+53
2017-05-09wsim: Add rtavg balancerChris Wilson3-20/+288
2017-05-09wsim: Improve rt balancer to use history across sync pointsChris Wilson1-4/+4
2017-05-09wsim: Add a small tolerance to rt balancingChris Wilson1-1/+38
2017-05-09wsim: Send a periodic depth stamp down each queueChris Wilson1-0/+68
2017-05-09wsim: per-engine throttlingChris Wilson1-15/+33
2017-05-09wsim: Per-client prng pool for miscellaneous randomsChris Wilson1-2/+5
2017-05-09gem_wsim: Slightly more robust workload parsingTvrtko Ursulin1-10/+13
2017-05-09gem_wsim: Allow symbolic balancer selectionTvrtko Ursulin1-1/+26
2017-05-09gem_wsim: Seed random numbers per clientTvrtko Ursulin1-2/+8
2017-05-09gem_wsim: Enable initial per-workload round-robin VCS engine assignmentTvrtko Ursulin1-4/+12
2017-05-09gem_wsim: Add RTR balancerTvrtko Ursulin1-3/+32
2017-05-08gem_wsim: More simulated transcoding workloadsTvrtko Ursulin6-0/+69
2017-05-08gem_wsim: Fix implicit sync on last workload stepTvrtko Ursulin1-1/+1
2017-05-08gem_wsim: Support VCS2 remappingTvrtko Ursulin1-16/+31
2017-05-08gem_wsim: Support multiple dependenciesTvrtko Ursulin5-40/+73
2017-05-05gem_wsim: Simplify batch creationTvrtko Ursulin1-15/+12
2017-05-05gem_wsim: Add some generic media workloadsTvrtko Ursulin9-0/+115
2017-05-04benchmarks: Add gem_wsim to .gitignorePetri Latvala1-1/+2
2017-04-25benchmarks/gem_wsim: Fix no reloc handlingTvrtko Ursulin1-1/+1
2017-04-25benchmarks/gem_wsim: Command submission workload simulatorTvrtko Ursulin9-0/+1463
2017-04-19benchmarks/gem_latency: Provide LOCAL defines for old libdrmChris Wilson1-4/+7
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-05 07:49:36 +0000