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2015-06-25c800hack-gk106mben1-0/+24
2015-06-24platform: recognize GM20BAlexandre Courbot1-0/+1
Allow the platform driver to recognize GM20B. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-24device: recognize GM20BAlexandre Courbot1-0/+20
Recognize GM20B and assign the right engines and subdevs. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-24gr: add GM20B supportAlexandre Courbot10-6/+217
Add support for GM20B's graphics engine, based on GK20A. Note that this code alone will not allow the engine to initialize on released devices which require PMU-assisted secure boot. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-24fifo: add GM20B fifoAlexandre Courbot5-1/+41
GM20B has a 512-channels FIFO similar to GK104. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-24gr/gk20a: use same initialization sequence as nvgpuAlexandre Courbot5-30/+421
GK20A's initialization was based on GK104, but differences exist in the way the initial context is built and the initialization process itself. This patch follows the same initialization sequence as nvgpu performs to avoid bad surprises. Since the register bundles initialization also differ considerably from GK104, the register packs are now loaded from firmware files, again similarly to what is done with nvgpu. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-24gr: use NVIDIA-provided external firmwaresAlexandre Courbot1-12/+19
NVIDIA will officially start providing GR firmwares through linux-firmware for GPUs that require it. Change the GR firmware lookup function to use these files. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-23pm/gk104: add compute signals/sourcesSamuel Pitoiset3-1/+93
These signals and sources have been reverse engineered from CUPTI (Linux). Graphics signals exposed by PerfKit (Windows only) will be added later. I need to reverse engineer them and it's a bit painful. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-23pm/gk104: re-use gf100_pm_ctor()Samuel Pitoiset3-56/+14
gk104_pm_ctor() is equal to gf100_pm_ctor(). Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-23pm/nv40: rename pcounter domains to 'pc' instead of 'pm'Samuel Pitoiset1-1/+1
This trivial patch makes thing more consistent since hardware signals names are prefixed by 'pcXX'. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-23pm: expose name of domainsSamuel Pitoiset2-0/+2
This is going to be very useful for GF100+ because each GPC can have its own domain of counters. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-19bios: add proper support for opcode 0x59Ilia Mirkin1-4/+20
More analysis shows that this is identical to 0x79 except that it loads the frequency indirectly from elsewhere in the VBIOS. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91025 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-19bios: add 0x59 and 0x5a opcodesIlia Mirkin1-0/+24
Opcode 0x5a is a register write for data looked up from another part of the VBIOS image. 0x59 is a more complex opcode, but we may as well recognize it. These occur on a single known instance of Riva TNT2 hardware. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91025 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-17drm/nouveau/clk: fix tstate to pstate calculationWei Ni1-1/+1
According to the tstate calculation in nvkm_clk_tstate(), the range of tstate is from -(clk->state_nr - 1) to 0, it mean the tstate is negative value. But in nvkm_pstate_work(), it use (clk->state_nr - 1 - clk->tstate) to limit pstate, it's not correct. This patch fix it to use (clk->state_nr - 1 + clk->tstate) to limit pstate. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-15pm: some fixes related to sourcesSamuel Pitoiset1-5/+16
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-15pm: fix signals/sources for GT200+Samuel Pitoiset2-6/+5
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-15pm/gf100: add compute signals/sourcesSamuel Pitoiset7-5/+282
These signals and sources have been reverse engineered from CUPTI (Linux). Graphics signals exposed by PerfKit (Windows only) will be added later. I need to reverse engineer them and it's a bit painful. This commit also adds a new class for GF108 and GF117. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-15pm/gf100: allow to share GPC, HUB and PART domainsSamuel Pitoiset4-19/+34
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-14pm: stack perfdom class under perfmonBen Skeggs2-21/+43
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-14pm: swap perfmon/perfdom code to avoid forward decl in next commitBen Skeggs1-175/+175
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-14pm/nv50: add compute and graphics signals/sourcesSamuel Pitoiset8-11/+485
These signals and sources have been reverse engineered from NVIDIA PerfKit (Windows) and CUPTI (Linux), they will be used to build complex hardware events from the userspace. This commit also adds a new class for GT200. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-14pm: allow the userspace to configure sourcesSamuel Pitoiset3-10/+95
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-14pm: allow to configure domains instead of simple countersSamuel Pitoiset7-170/+293
Configuring counters from the userspace require the kernel to handle some logic related to performance counters. Basically, it has to find a free slot to assign a counter, to handle extra counting modes like B4/B6 and it must return and error when it can't configure a counter. In my opinion, the kernel should not handle all of that logic but it should only write the configuration sent by the userspace without checking anything. In other words, it should overwrite the configuration even if it's already counting and do not return any errors. This patch allows the userspace to configure a domain instead of separate counters. This has the advantage to move all of the logic to the userspace. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-14pm: allow the userspace to schedule hardware countersSamuel Pitoiset3-25/+48
This adds a new method NVIF_PERFCTR_V0_INIT which starts a batch of hardware counters for sampling. This will allow the userspace to start a monitoring session using the INIT method and to stop it with SAMPLE, for example before and after a frame is rendered. This commit temporarily breaks nv_perfmon but this is going to be fixed with the upcoming patch. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-14pm: implement NVIF_PERFMON_V0_QUERY_SOURCE methodSamuel Pitoiset2-0/+89
This allows to query the ID, the mask and the user-readable name of sources for each signal. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-14pm: allow to query the number of sources for a signalSamuel Pitoiset2-4/+21
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-14pm: add concept of sourcesSamuel Pitoiset3-4/+103
A source (or multiplexer) is a tuple addr+mask+shift which allows to control a block of signals. The maximum number of sources that a signal can define is arbitrary limited to 8 and this should be large enough. This patch allows to define multi-level of sources for a signal. Each different sources are stored to a global list and will be exposed to the userspace through the nvif interface in order to avoid conflicts. Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-14pm: allow to monitor hardware signal index 0x00Samuel Pitoiset3-6/+10
This signal index must be always allowed even if it's not clearly defined in a domain in order to monitor a counter like 0x03020100 because it's the default value of signals. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-14pm: use hardware signals indexes instead of user-readable namesSamuel Pitoiset3-46/+23
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-14pm: change signal iter to u16Samuel Pitoiset4-11/+12
16 bits is large enough to store the maximum number of signals available for one domain (i.e. 256). Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-14pm: allow to query signals by domainSamuel Pitoiset3-74/+150
This will allow to configure performance counters with hardware signal indexes instead of user-readable names in an upcoming patch. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-14pm: implement NVIF_PERFMON_V0_QUERY_DOMAIN methodSamuel Pitoiset2-1/+96
This allows to query the number of available domains, including the number of hardware counter and the number of signals per domain. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-14pm: prevent creating a perfctr object when signals are not foundSamuel Pitoiset1-2/+4
Since a new class has been introduced to query signals, we can now return an error when the userspace wants to monitor unknown signals. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-14pm: reorganize the nvif interfaceSamuel Pitoiset4-24/+57
This commit introduces the NVIF_IOCTL_NEW_V0_PERFMON class which will be used in order to query domains, signals and sources. This separates the querying and the counting interface. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-09disp: Use NULL for pointersThierry Reding1-1/+1
The return type of exec_lookup() is struct nvkm_output *, so it should return NULL rather than 0. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-09pm: remove unused nvkm_perfsig_wrap() functionSamuel Pitoiset2-24/+0
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-09pm: remove pmu signalsSamuel Pitoiset8-151/+1
PDAEMON signals don't have to be exposed by the perfmon engine. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-09pm: fix a potential race condition when creating an engine contextSamuel Pitoiset1-4/+3
There is always the possiblity that the ppm->context pointer would get partially updated and accidentally would equal ctx. This would allow two contexts to co-exist, which is not acceptable. Moving the test to the critical section takes care of this problem. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-09pm: prevent freeing the wrong engine contextSamuel Pitoiset1-2/+5
This fixes a crash when multiple PM engine contexts are created. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-09gr/gf100: wait for GR idle after GO_IDLE bundleAlexandre Courbot2-0/+38
After submitting a GO_IDLE bundle, one must wait for GR to effectively be idle before submitting the next bundle. Failure to do so may result in undefined behavior in some rare cases. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reported-by: Kary Jin <karyj@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-09gr/gf100: wait on bottom half of FE's pipelineAlexandre Courbot1-1/+1
When emitting the ICMD bundle, wait on the bottom half (bit 3 of the GR_STATUS register) instead of upper half (bit 2) to make sure methods are effectively emitted. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-09fifo/gk104: kick channels when deactivating themAlexandre Courbot1-8/+21
Kicking channels is part of their deactivation process. Maxwell chips are particularly sensitive to this, and can start fetching the previous pushbuffer of a recycled channel if this is not done. While we are at it, improve the channel preemption code to only wait for bit 20 of 0x002634 to turn to 0, as it is the bit indicating a preempt is pending. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-09ibus/gk20a: increase SM wait timeoutAlexandre Courbot1-0/+8
Increase clock timeout for SYS, FPB and GPC in order to avoid operation failure at high gpcclk rate. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-09platform: fix compile error if !CONFIG_IOMMUAlexandre Courbot1-0/+16
The lack of IOMMU API support can make nouveau_platform_probe_iommu() fail to compile because struct iommu_ops is then empty. Fix this by skipping IOMMU probe in that case - lack of IOMMU on platform devices is sub-optimal, but is not an error. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-06drm: Do not leak client objectsThierry Reding1-0/+1
The memory allocated for a nouveau_cli object in nouveau_cli_create() is never freed. Free the memory in nouveau_cli_destroy() to plug this leak. kmemleak recorded this after running a couple of nouveau test programs. Note that kmemleak points at drm_open_helper() because for some reason it thinks that skipping the first two stack frames is a good idea. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-03clk/nv50: Enable user reclocking for NVA0Roy Spliet1-1/+2
Tested on a few cards. Probably works quite well for most, given they should all be GDDR3. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-03fb/gddr3: Add a few CL and WR entries observed on GTX260Roy Spliet1-4/+4
Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-03fb/ramnv50: GDDR3 script for NVA0Roy Spliet1-25/+104
This looks surprisingly similar to scripts on earlier cards as well but they don't seem to work just yet. That... and I don't have any, which makes it a tough job to reverse engineer. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-03bios/ramcfg: Separate out RON pull valueRoy Spliet4-3/+9
Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-06-03bios/rammap: Parse perf mode as if it's a rammap entryRoy Spliet4-0/+24
Some of the bits in there are similar to the bits in the gt215 rammap. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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