From 06ebbf7c2c071c8a4f32d3cfac914874fe981054 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Sat, 26 Mar 2011 15:04:04 +0100 Subject: Cleanup gen2 tiling confusion A tile on gen2 has a size of 2kb, stride of 128 bytes and 16 rows. Signed-off-by: Daniel Vetter --- intel/intel_bufmgr_gem.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index f5ab0a6f..4f4de929 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -762,13 +762,12 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name, aligned_y = y; height_alignment = 2; - if (tiling == I915_TILING_X) + if (IS_GEN2(bufmgr_gem) && tiling != I915_TILING_NONE) + height_alignment = 16; + else if (tiling == I915_TILING_X) height_alignment = 8; else if (tiling == I915_TILING_Y) height_alignment = 32; - /* i8xx has a interleaved 2-row tile layout */ - if (IS_GEN2(bufmgr_gem) && tiling != I915_TILING_NONE) - height_alignment *= 2; aligned_y = ALIGN(y, height_alignment); stride = x * cpp; -- cgit v1.2.3