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-rw-r--r--src/gallium/drivers/radeon/r600_pipe_common.c1
-rw-r--r--src/gallium/drivers/radeon/r600_pipe_common.h2
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.c6
3 files changed, 8 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index cc52d6ba39..8c66cc379f 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -730,6 +730,7 @@ void r600_common_context_cleanup(struct r600_common_context *rctx)
static const struct debug_named_value common_debug_options[] = {
/* logging */
{ "tex", DBG_TEX, "Print texture info" },
+ { "nir", DBG_NIR, "Enable experimental NIR shaders" },
{ "compute", DBG_COMPUTE, "Print compute info" },
{ "vm", DBG_VM, "Print virtual addresses when creating resources" },
{ "info", DBG_INFO, "Print driver information" },
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 4e3b42a112..4839c762bc 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -67,7 +67,7 @@
/* Debug flags. */
/* logging */
#define DBG_TEX (1 << 0)
-/* gap - reuse */
+#define DBG_NIR (1 << 1)
#define DBG_COMPUTE (1 << 2)
#define DBG_VM (1 << 3)
/* gap - reuse */
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index d5c21169d2..877c23bcb2 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -556,6 +556,8 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
return 4;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
+ if (sscreen->b.debug_flags & DBG_NIR)
+ return 140; /* no geometry and tessellation shaders yet */
if (si_have_tgsi_compute(sscreen))
return 450;
return 420;
@@ -753,6 +755,10 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
case PIPE_SHADER_CAP_PREFERRED_IR:
+ if (sscreen->b.debug_flags & DBG_NIR &&
+ (shader == PIPE_SHADER_VERTEX ||
+ shader == PIPE_SHADER_FRAGMENT))
+ return PIPE_SHADER_IR_NIR;
return PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
return 3;