/* * Copyright 2010 Francisco Jerez. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #include "nvhw.h" #include "nvreg.h" struct reg pmc_block[] = { { ~0, 0x000, "BOOT_0" }, { ~0, 0x001, "BOOT_1" }, { ~0, 0x100, "INTR_0" }, { ~0, 0x140, "INTR_EN_0" }, { ~0, 0x160, "INTR_READ_0" }, { ~0, 0x200, "ENABLE" }, { ~0, 0x300, "FRAME_PROTECT_MIN" }, { ~0, 0x304, "FRAME_PROTECT_MAX" }, { }, }; struct reg pbus_block[] = { { ~0, 0x1084, "DEBUG_1" }, { ~0, 0x1088, "DEBUG_2" }, { ~0, 0x108c, "DEBUG_3" }, { ~0, 0x1098 }, { ~0, 0x10b8, "DEBUG_CTRIM_2" }, { ~0, 0x10d8 }, { ~0, 0x10e0, "DEBUG_PRIV_ASRC" }, { ~0, 0x10f0, "DEBUG_DUALHEAD_CTL" }, { ~0, 0x1100, "INTR_0" }, { ~0, 0x1140, "INTR_EN_0" }, { ~0, 0x1210 }, { ~0, 0x1214 }, { ~0, 0x1218 }, { ~0, 0x121c }, { ~0, 0x1220 }, { ~0, 0x1224 }, { ~0, 0x1228 }, { ~0, 0x122c }, { ~0, 0x1230 }, { ~0, 0x1234 }, { ~0, 0x1238 }, { ~0, 0x123c }, { ~0, 0x1240 }, { ~0, 0x1244 }, { ~0, 0x1248 }, { ~0, 0x124c }, { ~0, 0x1250 }, { ~0, 0x1518 }, { ~0, 0x1580 }, { ~0, 0x1584, "POWERCTRL_1" }, { ~0, 0x1588, "POWERCTRL_2" }, { ~0, 0x158c }, { ~0, 0x1590, "POWERCTRL_4" }, { ~0, 0x15a0 }, { ~0, 0x1800 }, { ~0, 0x1804 }, { ~0, 0x1808 }, { ~0, 0x180c }, { ~0, 0x1810 }, { ~0, 0x1814 }, { ~0, 0x1818 }, { ~0, 0x182c }, { ~0, 0x1830 }, { ~0, 0x1844 }, { ~0, 0x1848 }, { ~0, 0x184c }, { ~0, 0x1850 }, { ~0, 0x1854 }, { ~0, 0x1860 }, { } }; struct reg pfb_block[] = { { ~0, 0x100000, "BOOT_0" }, { ~0, 0x100080, "DEBUG_0" }, { ~0, 0x1000f0 }, { ~0, 0x100200, "CFG0" }, { ~0, 0x100204, "CFG1" }, { ~0, 0x100208, "FIFO_CTL" }, { ~0, 0x10020c, "FIFO_DATA" }, { ~0, 0x100210, "REFCTRL" }, { ~0, 0x100214, "NVM" }, { ~0, 0x100218, "PIN" }, { ~0, 0x10021c, "PAD" }, { ~0, 0x100220, "TIMING0" }, { ~0, 0x100224, "TIMING1" }, { ~0, 0x100228, "TIMING2" }, { ~0, 0x1002c0, "MRS" }, { ~0, 0x1002c4, "EMRS" }, { ~0, 0x1002c8 }, { ~0, 0x1002cc }, { ~0, 0x1002d0, "REF" }, { ~0, 0x1002d4, "PRE" }, { ~0, 0x100300, "ZCOMP0" }, { ~0, 0x100304, "ZCOMP1" }, { ~0, 0x100308, "ZCOMP2" }, { ~0, 0x10030c, "ZCOMP3" }, { ~0, 0x100310, "ZCOMP4" }, { ~0, 0x100314, "ZCOMP5" }, { ~0, 0x100318, "ZCOMP6" }, { ~0, 0x10031c, "ZCOMP7" }, { ~0, 0x100320, "ZCOMP_MAX_TAG" }, { ~0, 0x100324, "ZCOMP_OFFSET" }, { ~0, 0x100328, "ARB_PREDIVIDER" }, { ~0, 0x10032c, "ARB_TIMEOUT" }, { ~0, 0x100330, "ARB_XFER_SZ" }, { ~0, 0x100334, "CLOSE_PAGE0" }, { ~0, 0x100338, "CLOSE_PAGE1" }, { ~0, 0x100340 }, { ~0, 0x100344 }, { ~0, 0x100348 }, { ~0, 0x10034c }, { ~0, 0x100350 }, { ~0, 0x100360 }, { ~0, 0x10037c }, { ~0, 0x100380 }, { ~0, 0x100384 }, { ~0, 0x100388 }, { ~0, 0x10038c }, { ~0, 0x100390 }, { ~0, 0x100394 }, { ~0, 0x100398 }, { ~0, 0x10039c }, { ~0, 0x1003a0 }, { ~0, 0x1003a4 }, { ~0, 0x1003a8 }, { ~0, 0x1003ac }, { ~0, 0x1003b0 }, { ~0, 0x1003b4 }, { ~0, 0x1003b8 }, { ~0, 0x1003bc }, { ~0, 0x1003c0 }, { ~0, 0x1003c4 }, { ~0, 0x1003c8 }, { ~0, 0x1003d0 }, { } }; struct reg pcrtc_block[] = { { NV04_DISPLAY_CLASS, 0x600100, "INTR_0" }, { NV04_DISPLAY_CLASS, 0x600140, "INTR_EN_0" }, { NV04_DISPLAY_CLASS, 0x600800, "START" }, { NV04_DISPLAY_CLASS, 0x600804, "CONFIG" }, { NV04_DISPLAY_CLASS, 0x600808, "RASTER" }, { NV04_DISPLAY_CLASS, 0x60080C, "CURSOR" }, { NV04_DISPLAY_CLASS, 0x600810, "CURSOR_CONFIG" }, { NV04_DISPLAY_CLASS, 0x600814, "VIP_RASTER" }, { NV04_DISPLAY_CLASS, 0x600818, "GPIO" }, { NV04_DISPLAY_CLASS, 0x60081c, "GPIO_EXT" }, { NV04_DISPLAY_CLASS, 0x600820, "FIFO_CNTRL" }, { NV04_DISPLAY_CLASS, 0x600824, "FIFO_DATA" }, { NV04_DISPLAY_CLASS, 0x600830 }, { NV04_DISPLAY_CLASS, 0x600834 }, { NV04_DISPLAY_CLASS, 0x600850 }, { NV04_DISPLAY_CLASS, 0x600860, "ENGINE_CTRL" }, { } }; struct reg vga_crtc_block[] = { { NV04_DISPLAY_CLASS, 0 }, { NV04_DISPLAY_CLASS, 0x1 }, { NV04_DISPLAY_CLASS, 0x2 }, { NV04_DISPLAY_CLASS, 0x3 }, { NV04_DISPLAY_CLASS, 0x4 }, { NV04_DISPLAY_CLASS, 0x5 }, { NV04_DISPLAY_CLASS, 0x6 }, { NV04_DISPLAY_CLASS, 0x7 }, { NV04_DISPLAY_CLASS, 0x8 }, { NV04_DISPLAY_CLASS, 0x9 }, { NV04_DISPLAY_CLASS, 0xa }, { NV04_DISPLAY_CLASS, 0xb }, { NV04_DISPLAY_CLASS, 0xc }, { NV04_DISPLAY_CLASS, 0xd }, { NV04_DISPLAY_CLASS, 0xe }, { NV04_DISPLAY_CLASS, 0xf }, { NV04_DISPLAY_CLASS, 0x10 }, { NV04_DISPLAY_CLASS, 0x11 }, { NV04_DISPLAY_CLASS, 0x12 }, { NV04_DISPLAY_CLASS, 0x13 }, { NV04_DISPLAY_CLASS, 0x14 }, { NV04_DISPLAY_CLASS, 0x15 }, { NV04_DISPLAY_CLASS, 0x16 }, { NV04_DISPLAY_CLASS, 0x17 }, { NV04_DISPLAY_CLASS, 0x18 }, { NV04_DISPLAY_CLASS, 0x19 }, { NV04_DISPLAY_CLASS, 0x1a, "RPC1" }, { NV04_DISPLAY_CLASS, 0x1b }, { NV04_DISPLAY_CLASS, 0x1c, "ENH" }, { NV04_DISPLAY_CLASS, 0x1d }, { NV04_DISPLAY_CLASS, 0x1e }, { NV04_DISPLAY_CLASS, 0x1f }, { NV04_DISPLAY_CLASS, 0x20 }, { NV04_DISPLAY_CLASS, 0x21 }, { NV04_DISPLAY_CLASS, 0x22 }, { NV04_DISPLAY_CLASS, 0x23 }, { NV04_DISPLAY_CLASS, 0x24 }, { NV04_DISPLAY_CLASS, 0x25 }, { NV04_DISPLAY_CLASS, 0x26 }, { NV04_DISPLAY_CLASS, 0x27 }, { NV04_DISPLAY_CLASS, 0x28, "PIXEL" }, { NV04_DISPLAY_CLASS, 0x29 }, { NV04_DISPLAY_CLASS, 0x2a }, { NV04_DISPLAY_CLASS, 0x2b }, { NV04_DISPLAY_CLASS, 0x2c }, { NV04_DISPLAY_CLASS, 0x2d }, { NV04_DISPLAY_CLASS, 0x2e }, { NV04_DISPLAY_CLASS, 0x2f }, { NV04_DISPLAY_CLASS, 0x30 }, { NV04_DISPLAY_CLASS, 0x31 }, { NV04_DISPLAY_CLASS, 0x32 }, { NV04_DISPLAY_CLASS, 0x33, "LCD" }, { NV04_DISPLAY_CLASS, 0x34 }, { NV04_DISPLAY_CLASS, 0x35 }, { NV04_DISPLAY_CLASS, 0x36 }, { NV04_DISPLAY_CLASS, 0x37 }, { NV04_DISPLAY_CLASS, 0x38 }, { NV04_DISPLAY_CLASS, 0x39 }, { NV04_DISPLAY_CLASS, 0x3a }, { NV04_DISPLAY_CLASS, 0x3b }, { NV04_DISPLAY_CLASS, 0x3c }, { NV04_DISPLAY_CLASS, 0x3d }, { NV04_DISPLAY_CLASS, 0x3e }, { NV04_DISPLAY_CLASS, 0x3f }, { NV04_DISPLAY_CLASS, 0x40 }, { NV04_DISPLAY_CLASS, 0x41 }, { NV04_DISPLAY_CLASS, 0x42 }, { NV04_DISPLAY_CLASS, 0x43 }, { NV04_DISPLAY_CLASS, 0x44 }, { NV04_DISPLAY_CLASS, 0x45 }, { NV04_DISPLAY_CLASS, 0x46 }, { NV04_DISPLAY_CLASS, 0x47 }, { NV04_DISPLAY_CLASS, 0x48 }, { NV04_DISPLAY_CLASS, 0x49 }, { NV04_DISPLAY_CLASS, 0x4a }, { NV04_DISPLAY_CLASS, 0x4b }, { NV04_DISPLAY_CLASS, 0x4c }, { NV04_DISPLAY_CLASS, 0x4d }, { NV04_DISPLAY_CLASS, 0x4e }, { NV04_DISPLAY_CLASS, 0x4f }, { NV04_DISPLAY_CLASS, 0x50 }, { NV04_DISPLAY_CLASS, 0x51 }, { NV04_DISPLAY_CLASS, 0x52 }, { NV04_DISPLAY_CLASS, 0x53, "FP_HTIMING" }, { NV04_DISPLAY_CLASS, 0x54, "FP_VTIMING" }, { NV04_DISPLAY_CLASS, 0x55 }, { NV04_DISPLAY_CLASS, 0x56 }, { NV04_DISPLAY_CLASS, 0x57 }, { NV04_DISPLAY_CLASS, 0x58 }, { NV04_DISPLAY_CLASS, 0x59 }, { NV04_DISPLAY_CLASS, 0x5a }, { NV04_DISPLAY_CLASS, 0x5b }, { NV04_DISPLAY_CLASS, 0x5c }, { NV04_DISPLAY_CLASS, 0x5d }, { NV04_DISPLAY_CLASS, 0x5e }, { NV04_DISPLAY_CLASS, 0x5f }, { NV04_DISPLAY_CLASS, 0x60 }, { NV04_DISPLAY_CLASS, 0x61 }, { NV04_DISPLAY_CLASS, 0x62 }, { NV04_DISPLAY_CLASS, 0x63 }, { NV04_DISPLAY_CLASS, 0x64 }, { NV04_DISPLAY_CLASS, 0x65 }, { NV04_DISPLAY_CLASS, 0x66 }, { NV04_DISPLAY_CLASS, 0x67 }, { NV04_DISPLAY_CLASS, 0x68 }, { NV04_DISPLAY_CLASS, 0x69 }, { NV04_DISPLAY_CLASS, 0x6a }, { NV04_DISPLAY_CLASS, 0x6b }, { NV04_DISPLAY_CLASS, 0x6c }, { NV04_DISPLAY_CLASS, 0x6d }, { NV04_DISPLAY_CLASS, 0x6e }, { NV04_DISPLAY_CLASS, 0x6f }, { NV04_DISPLAY_CLASS, 0x70 }, { NV04_DISPLAY_CLASS, 0x71 }, { NV04_DISPLAY_CLASS, 0x72 }, { NV04_DISPLAY_CLASS, 0x73 }, { NV04_DISPLAY_CLASS, 0x74 }, { NV04_DISPLAY_CLASS, 0x75 }, { NV04_DISPLAY_CLASS, 0x76 }, { NV04_DISPLAY_CLASS, 0x77 }, { NV04_DISPLAY_CLASS, 0x78 }, { NV04_DISPLAY_CLASS, 0x79 }, { NV04_DISPLAY_CLASS, 0x7a }, { NV04_DISPLAY_CLASS, 0x7b }, { NV04_DISPLAY_CLASS, 0x7c }, { NV04_DISPLAY_CLASS, 0x7d }, { NV04_DISPLAY_CLASS, 0x7e }, { NV04_DISPLAY_CLASS, 0x7f }, { NV04_DISPLAY_CLASS, 0x80 }, { NV04_DISPLAY_CLASS, 0x81 }, { NV04_DISPLAY_CLASS, 0x82 }, { NV04_DISPLAY_CLASS, 0x83 }, { NV04_DISPLAY_CLASS, 0x84 }, { NV04_DISPLAY_CLASS, 0x85 }, { NV04_DISPLAY_CLASS, 0x86 }, { NV04_DISPLAY_CLASS, 0x87 }, { NV04_DISPLAY_CLASS, 0x88 }, { NV04_DISPLAY_CLASS, 0x89 }, { NV04_DISPLAY_CLASS, 0x8a }, { NV04_DISPLAY_CLASS, 0x8b }, { NV04_DISPLAY_CLASS, 0x8c }, { NV04_DISPLAY_CLASS, 0x8d }, { NV04_DISPLAY_CLASS, 0x8e }, { NV04_DISPLAY_CLASS, 0x8f }, { NV04_DISPLAY_CLASS, 0x90 }, { NV04_DISPLAY_CLASS, 0x91 }, { NV04_DISPLAY_CLASS, 0x92 }, { NV04_DISPLAY_CLASS, 0x93 }, { NV04_DISPLAY_CLASS, 0x94 }, { NV04_DISPLAY_CLASS, 0x95 }, { NV04_DISPLAY_CLASS, 0x96 }, { NV04_DISPLAY_CLASS, 0x97 }, { NV04_DISPLAY_CLASS, 0x98 }, { NV04_DISPLAY_CLASS, 0x99 }, { NV04_DISPLAY_CLASS, 0x9a }, { NV04_DISPLAY_CLASS, 0x9b }, { NV04_DISPLAY_CLASS, 0x9c }, { NV04_DISPLAY_CLASS, 0x9d }, { NV04_DISPLAY_CLASS, 0x9e }, { NV04_DISPLAY_CLASS, 0x9f }, { } }; struct reg pramdac_block[] = { { NV04_DISPLAY_CLASS, 0x680510, "PLL_SETUP_CONTROL" }, { NV04_DISPLAY_CLASS, 0x680524, "SEL_CLK" }, { NV17_DISPLAY_CLASS, 0x68052c, "DACCLK_A" }, { NV17_DISPLAY_CLASS, 0x680594, "DACCLK_B" }, { NV04_DISPLAY_CLASS, 0x68050c, "PLL_COEFF_SELECT" }, { NV04_DISPLAY_CLASS, 0x680630 }, { NV04_DISPLAY_CLASS, 0x680674 }, { NV04_DISPLAY_CLASS, 0x680700, "TV_SETUP" }, { NV04_DISPLAY_CLASS, 0x680704, "TV_VBLANK_START" }, { NV04_DISPLAY_CLASS, 0x680708, "TV_VBLANK_END" }, { NV04_DISPLAY_CLASS, 0x68070c, "TV_HBLANK_START" }, { NV04_DISPLAY_CLASS, 0x680710, "TV_HBLANK_END" }, { NV04_DISPLAY_CLASS, 0x680714, "TV_BLANK_COLOR" }, { NV04_DISPLAY_CLASS, 0x680720, "TV_VTOTAL" }, { NV04_DISPLAY_CLASS, 0x680724, "TV_VSYNC_START" }, { NV04_DISPLAY_CLASS, 0x680728, "TV_VSYNC_END" }, { NV04_DISPLAY_CLASS, 0x68072c, "TV_HTOTAL" }, { NV04_DISPLAY_CLASS, 0x680730, "TV_HSYNC_START" }, { NV04_DISPLAY_CLASS, 0x680734, "TV_HSYNC_STOP" }, { NV04_DISPLAY_CLASS, 0x680738, "TV_SYNC_DELAY" }, { NV04_DISPLAY_CLASS, 0x680880, "FP_DEBUG_0" }, { NV04_DISPLAY_CLASS, 0x680884, "FP_DEBUG_1" }, { NV04_DISPLAY_CLASS, 0x680888, "FP_DEBUG_2" }, { NV04_DISPLAY_CLASS, 0x680848, "FP_TG_CONTROL" }, { NV04_DISPLAY_CLASS, 0x680824, "FP_HTOTAL" }, { NV04_DISPLAY_CLASS, 0x680834, "FP_HVALID_START" }, { NV04_DISPLAY_CLASS, 0x680838, "FP_HVALID_END" }, { NV04_DISPLAY_CLASS, 0x680820, "FP_HDISPLAY_END" }, { NV04_DISPLAY_CLASS, 0x680828, "FP_HCRTC" }, { NV04_DISPLAY_CLASS, 0x68082c, "FP_HSYNC_START" }, { NV04_DISPLAY_CLASS, 0x680830, "FP_HSYNC_END" }, { NV04_DISPLAY_CLASS, 0x680804, "FP_VTOTAL" }, { NV04_DISPLAY_CLASS, 0x680814, "FP_VVALID_START" }, { NV04_DISPLAY_CLASS, 0x680818, "FP_VVALID_END" }, { NV04_DISPLAY_CLASS, 0x680800, "FP_VDISPLAY_END" }, { NV04_DISPLAY_CLASS, 0x680808, "FP_VCRTC" }, { NV04_DISPLAY_CLASS, 0x68080c, "FP_VSYNC_START" }, { NV04_DISPLAY_CLASS, 0x680810, "FP_VSYNC_END" }, { NV04_DISPLAY_CLASS, 0x68084c }, { NV04_DISPLAY_CLASS, 0x680898 }, { NV04_DISPLAY_CLASS, 0x68089c }, { NV04_DISPLAY_CLASS, 0x6808c0 }, { NV04_DISPLAY_CLASS, 0x680900 }, { NV40_CLASS, 0x680c00 }, { NV40_CLASS, 0x680c04 }, { NV40_CLASS, 0x680c08 }, { NV40_CLASS, 0x680c0c }, { NV40_CLASS, 0x680c10 }, { NV40_CLASS, 0x680c14 }, { NV40_CLASS, 0x680c18 }, { NV40_CLASS, 0x680c1c }, { NV40_CLASS, 0x680c20 }, { NV40_CLASS, 0x680c24 }, { NV40_CLASS, 0x680c28 }, { NV40_CLASS, 0x680c2c }, { NV40_CLASS, 0x680c30 }, { NV40_CLASS, 0x680c34 }, { NV40_CLASS, 0x680c38 }, { NV40_CLASS, 0x680c3c }, { NV40_CLASS, 0x680c40 }, { NV40_CLASS, 0x680c44 }, { NV40_CLASS, 0x680c48 }, { NV40_CLASS, 0x680c4c }, { NV40_CLASS, 0x680c50 }, { NV40_CLASS, 0x680c54 }, { NV40_CLASS, 0x680c58 }, { NV40_CLASS, 0x680c5c }, { NV40_CLASS, 0x680c60 }, { NV40_CLASS, 0x680c64 }, { NV40_CLASS, 0x680c68 }, { NV40_CLASS, 0x680c6c }, { NV40_CLASS, 0x680c70 }, { NV40_CLASS, 0x680c74 }, { NV40_CLASS, 0x680c78 }, { NV40_CLASS, 0x680c7c }, { NV40_CLASS, 0x680c80 }, { NV40_CLASS, 0x680c84 }, { NV40_CLASS, 0x680c88 }, { NV40_CLASS, 0x680c8c }, { NV40_CLASS, 0x680c90 }, { NV40_CLASS, 0x680c94 }, { NV40_CLASS, 0x680c98 }, { NV40_CLASS, 0x680c9c }, { NV40_CLASS, 0x680ca0 }, { NV40_CLASS, 0x680ca4 }, { NV40_CLASS, 0x680ca8 }, { NV40_CLASS, 0x680cac }, { NV40_CLASS, 0x680cb0 }, { NV40_CLASS, 0x680cb4 }, { NV40_CLASS, 0x680cb8 }, { NV40_CLASS, 0x680cbc }, { NV40_CLASS, 0x680cc0 }, { NV40_CLASS, 0x680cc4 }, { NV40_CLASS, 0x680cc8 }, { NV40_CLASS, 0x680ccc }, { NV40_CLASS, 0x680cd0 }, { NV40_CLASS, 0x680cd4 }, { NV40_CLASS, 0x680cd8 }, { NV40_CLASS, 0x680cdc }, { NV40_CLASS, 0x680ce0 }, { NV40_CLASS, 0x680ce4 }, { NV40_CLASS, 0x680ce8 }, { NV40_CLASS, 0x680cec }, { NV40_CLASS, 0x680cf0 }, { NV40_CLASS, 0x680cf4 }, { NV40_CLASS, 0x680cf8 }, { NV40_CLASS, 0x680cfc }, { } }; struct reg ptv_block[] = { { NV17_TVOUT_CLASS, 0xd200 }, { NV17_TVOUT_CLASS, 0xd204 }, { NV17_TVOUT_CLASS, 0xd208 }, { NV17_TVOUT_CLASS, 0xd20c }, { NV17_TVOUT_CLASS, 0xd300 }, { NV17_TVOUT_CLASS, 0xd304 }, { NV17_TVOUT_CLASS, 0xd308 }, { NV17_TVOUT_CLASS, 0xd30c }, { NV17_TVOUT_CLASS, 0xd310 }, { NV17_TVOUT_CLASS, 0xd314 }, { NV17_TVOUT_CLASS, 0xd318 }, { NV17_TVOUT_CLASS, 0xd31c }, { NV17_TVOUT_CLASS, 0xd320 }, { NV17_TVOUT_CLASS, 0xd324 }, { NV17_TVOUT_CLASS, 0xd328 }, { NV17_TVOUT_CLASS, 0xd32c }, { NV17_TVOUT_CLASS, 0xd330 }, { NV17_TVOUT_CLASS, 0xd334 }, { NV17_TVOUT_CLASS, 0xd338 }, { NV17_TVOUT_CLASS, 0xd33c }, { NV17_TVOUT_CLASS, 0xd340 }, { NV17_TVOUT_CLASS, 0xd344 }, { NV17_TVOUT_CLASS, 0xd348 }, { NV17_TVOUT_CLASS, 0xd34c }, { NV17_TVOUT_CLASS, 0xd350 }, { NV17_TVOUT_CLASS, 0xd354 }, { NV17_TVOUT_CLASS, 0xd358 }, { NV17_TVOUT_CLASS, 0xd35c }, { NV17_TVOUT_CLASS, 0xd360 }, { NV17_TVOUT_CLASS, 0xd364 }, { NV17_TVOUT_CLASS, 0xd368 }, { NV17_TVOUT_CLASS, 0xd36c }, { NV17_TVOUT_CLASS, 0xd370 }, { NV17_TVOUT_CLASS, 0xd374 }, { NV17_TVOUT_CLASS, 0xd378 }, { NV17_TVOUT_CLASS, 0xd37c }, { NV17_TVOUT_CLASS, 0xd380 }, { NV17_TVOUT_CLASS, 0xd384 }, { NV17_TVOUT_CLASS, 0xd388 }, { NV17_TVOUT_CLASS, 0xd38c }, { NV17_TVOUT_CLASS, 0xd390 }, { NV17_TVOUT_CLASS, 0xd394 }, { NV17_TVOUT_CLASS, 0xd398 }, { NV17_TVOUT_CLASS, 0xd39c }, { NV17_TVOUT_CLASS, 0xd3a0 }, { NV17_TVOUT_CLASS, 0xd3a4 }, { NV17_TVOUT_CLASS, 0xd3a8 }, { NV17_TVOUT_CLASS, 0xd3ac }, { NV17_TVOUT_CLASS, 0xd3b0 }, { NV17_TVOUT_CLASS, 0xd3b4 }, { NV17_TVOUT_CLASS, 0xd3b8 }, { NV17_TVOUT_CLASS, 0xd3bc }, { NV17_TVOUT_CLASS, 0xd3c0 }, { NV17_TVOUT_CLASS, 0xd3c4 }, { NV17_TVOUT_CLASS, 0xd3c8 }, { NV17_TVOUT_CLASS, 0xd3cc }, { NV17_TVOUT_CLASS, 0xd3d0 }, { NV17_TVOUT_CLASS, 0xd3d4 }, { NV17_TVOUT_CLASS, 0xd3d8 }, { NV17_TVOUT_CLASS, 0xd3dc }, { NV17_TVOUT_CLASS, 0xd3e0 }, { NV17_TVOUT_CLASS, 0xd3e4 }, { NV17_TVOUT_CLASS, 0xd3e8 }, { NV17_TVOUT_CLASS, 0xd3ec }, { NV17_TVOUT_CLASS, 0xd3f0 }, { NV17_TVOUT_CLASS, 0xd3f4 }, { NV17_TVOUT_CLASS, 0xd3f8 }, { NV17_TVOUT_CLASS, 0xd3fc }, { NV17_TVOUT_CLASS, 0xd400 }, { NV17_TVOUT_CLASS, 0xd404 }, { NV17_TVOUT_CLASS, 0xd408 }, { NV17_TVOUT_CLASS, 0xd40c }, { NV17_TVOUT_CLASS, 0xd500 }, { NV17_TVOUT_CLASS, 0xd504 }, { NV17_TVOUT_CLASS, 0xd508 }, { NV17_TVOUT_CLASS, 0xd50c }, { NV17_TVOUT_CLASS, 0xd510 }, { NV17_TVOUT_CLASS, 0xd514 }, { NV17_TVOUT_CLASS, 0xd518 }, { NV17_TVOUT_CLASS, 0xd51c }, { NV17_TVOUT_CLASS, 0xd520 }, { NV17_TVOUT_CLASS, 0xd524 }, { NV17_TVOUT_CLASS, 0xd528 }, { NV17_TVOUT_CLASS, 0xd52c }, { NV17_TVOUT_CLASS, 0xd530 }, { NV17_TVOUT_CLASS, 0xd534 }, { NV17_TVOUT_CLASS, 0xd538 }, { NV17_TVOUT_CLASS, 0xd53c }, { NV17_TVOUT_CLASS, 0xd540 }, { NV17_TVOUT_CLASS, 0xd544 }, { NV17_TVOUT_CLASS, 0xd548 }, { NV17_TVOUT_CLASS, 0xd54c }, { NV17_TVOUT_CLASS, 0xd550 }, { NV17_TVOUT_CLASS, 0xd554 }, { NV17_TVOUT_CLASS, 0xd558 }, { NV17_TVOUT_CLASS, 0xd55c }, { NV17_TVOUT_CLASS, 0xd560 }, { NV17_TVOUT_CLASS, 0xd564 }, { NV17_TVOUT_CLASS, 0xd568 }, { NV17_TVOUT_CLASS, 0xd56c }, { NV17_TVOUT_CLASS, 0xd570 }, { NV17_TVOUT_CLASS, 0xd574 }, { NV17_TVOUT_CLASS, 0xd578 }, { NV17_TVOUT_CLASS, 0xd57c }, { NV17_TVOUT_CLASS, 0xd580 }, { NV17_TVOUT_CLASS, 0xd584 }, { NV17_TVOUT_CLASS, 0xd588 }, { NV17_TVOUT_CLASS, 0xd58c }, { NV17_TVOUT_CLASS, 0xd600 }, { NV17_TVOUT_CLASS, 0xd604 }, { NV17_TVOUT_CLASS, 0xd608 }, { NV17_TVOUT_CLASS, 0xd60c }, { NV17_TVOUT_CLASS, 0xd610 }, { NV17_TVOUT_CLASS, 0xd614 }, { NV17_TVOUT_CLASS, 0xd618 }, { NV17_TVOUT_CLASS, 0xd61c }, { } }; struct reg itv_block[] = { { NV17_TVOUT_CLASS, 0x0 }, { NV17_TVOUT_CLASS, 0x1 }, { NV17_TVOUT_CLASS, 0x2 }, { NV17_TVOUT_CLASS, 0x3 }, { NV17_TVOUT_CLASS, 0x4 }, { NV17_TVOUT_CLASS, 0x5 }, { NV17_TVOUT_CLASS, 0x6 }, { NV17_TVOUT_CLASS, 0x7 }, { NV17_TVOUT_CLASS, 0x8 }, { NV17_TVOUT_CLASS, 0x9 }, { NV17_TVOUT_CLASS, 0xa }, { NV17_TVOUT_CLASS, 0xb }, { NV17_TVOUT_CLASS, 0xc }, { NV17_TVOUT_CLASS, 0xd }, { NV17_TVOUT_CLASS, 0xe }, { NV17_TVOUT_CLASS, 0xf }, { NV17_TVOUT_CLASS, 0x10 }, { NV17_TVOUT_CLASS, 0x11 }, { NV17_TVOUT_CLASS, 0x12 }, { NV17_TVOUT_CLASS, 0x13 }, { NV17_TVOUT_CLASS, 0x14 }, { NV17_TVOUT_CLASS, 0x15 }, { NV17_TVOUT_CLASS, 0x16 }, { NV17_TVOUT_CLASS, 0x17 }, { NV17_TVOUT_CLASS, 0x18 }, { NV17_TVOUT_CLASS, 0x19 }, { NV17_TVOUT_CLASS, 0x1a }, { NV17_TVOUT_CLASS, 0x1b }, { NV17_TVOUT_CLASS, 0x1c }, { NV17_TVOUT_CLASS, 0x1d }, { NV17_TVOUT_CLASS, 0x1e }, { NV17_TVOUT_CLASS, 0x1f }, { NV17_TVOUT_CLASS, 0x20 }, { NV17_TVOUT_CLASS, 0x21 }, { NV17_TVOUT_CLASS, 0x22 }, { NV17_TVOUT_CLASS, 0x23 }, { NV17_TVOUT_CLASS, 0x24 }, { NV17_TVOUT_CLASS, 0x25 }, { NV17_TVOUT_CLASS, 0x26 }, { NV17_TVOUT_CLASS, 0x27 }, { NV17_TVOUT_CLASS, 0x28 }, { NV17_TVOUT_CLASS, 0x29 }, { NV17_TVOUT_CLASS, 0x2a }, { NV17_TVOUT_CLASS, 0x2b }, { NV17_TVOUT_CLASS, 0x2c }, { NV17_TVOUT_CLASS, 0x2d }, { NV17_TVOUT_CLASS, 0x2e }, { NV17_TVOUT_CLASS, 0x2f }, { NV17_TVOUT_CLASS, 0x30 }, { NV17_TVOUT_CLASS, 0x31 }, { NV17_TVOUT_CLASS, 0x32 }, { NV17_TVOUT_CLASS, 0x33 }, { NV17_TVOUT_CLASS, 0x34 }, { NV17_TVOUT_CLASS, 0x35 }, { NV17_TVOUT_CLASS, 0x36 }, { NV17_TVOUT_CLASS, 0x37 }, { NV17_TVOUT_CLASS, 0x38 }, { NV17_TVOUT_CLASS, 0x39 }, { NV17_TVOUT_CLASS, 0x3a }, { NV17_TVOUT_CLASS, 0x3b }, { NV17_TVOUT_CLASS, 0x3c }, { NV17_TVOUT_CLASS, 0x3d }, { NV17_TVOUT_CLASS, 0x3e }, { NV17_TVOUT_CLASS, 0x3f }, { } }; struct reg tmds_block[] = { { NV04_DISPLAY_CLASS, 0x0 }, { NV04_DISPLAY_CLASS, 0x1 }, { NV04_DISPLAY_CLASS, 0x2 }, { NV04_DISPLAY_CLASS, 0x3 }, { NV04_DISPLAY_CLASS, 0x4 }, { NV04_DISPLAY_CLASS, 0x5 }, { NV04_DISPLAY_CLASS, 0x6 }, { NV04_DISPLAY_CLASS, 0x7 }, { NV04_DISPLAY_CLASS, 0x8 }, { NV04_DISPLAY_CLASS, 0x9 }, { NV04_DISPLAY_CLASS, 0xa }, { NV04_DISPLAY_CLASS, 0xb }, { NV04_DISPLAY_CLASS, 0xc }, { NV04_DISPLAY_CLASS, 0xd }, { NV04_DISPLAY_CLASS, 0xe }, { NV04_DISPLAY_CLASS, 0xf }, { NV04_DISPLAY_CLASS, 0x10 }, { NV04_DISPLAY_CLASS, 0x11 }, { NV04_DISPLAY_CLASS, 0x12 }, { NV04_DISPLAY_CLASS, 0x13 }, { NV04_DISPLAY_CLASS, 0x14 }, { NV04_DISPLAY_CLASS, 0x15 }, { NV04_DISPLAY_CLASS, 0x16 }, { NV04_DISPLAY_CLASS, 0x17 }, { NV04_DISPLAY_CLASS, 0x18 }, { NV04_DISPLAY_CLASS, 0x19 }, { NV04_DISPLAY_CLASS, 0x1a }, { NV04_DISPLAY_CLASS, 0x1b }, { NV04_DISPLAY_CLASS, 0x1c }, { NV04_DISPLAY_CLASS, 0x1d }, { NV04_DISPLAY_CLASS, 0x1e }, { NV04_DISPLAY_CLASS, 0x1f }, { NV04_DISPLAY_CLASS, 0x20 }, { NV04_DISPLAY_CLASS, 0x21 }, { NV04_DISPLAY_CLASS, 0x22 }, { NV04_DISPLAY_CLASS, 0x23 }, { NV04_DISPLAY_CLASS, 0x24 }, { NV04_DISPLAY_CLASS, 0x25 }, { NV04_DISPLAY_CLASS, 0x26 }, { NV04_DISPLAY_CLASS, 0x27 }, { NV04_DISPLAY_CLASS, 0x28 }, { NV04_DISPLAY_CLASS, 0x29 }, { NV04_DISPLAY_CLASS, 0x2a }, { NV04_DISPLAY_CLASS, 0x2b }, { NV04_DISPLAY_CLASS, 0x2c }, { NV04_DISPLAY_CLASS, 0x2d }, { NV04_DISPLAY_CLASS, 0x2e }, { NV04_DISPLAY_CLASS, 0x2f }, { NV04_DISPLAY_CLASS, 0x30 }, { NV04_DISPLAY_CLASS, 0x31 }, { NV04_DISPLAY_CLASS, 0x32 }, { NV04_DISPLAY_CLASS, 0x33 }, { NV04_DISPLAY_CLASS, 0x34 }, { NV04_DISPLAY_CLASS, 0x35 }, { NV04_DISPLAY_CLASS, 0x36 }, { NV04_DISPLAY_CLASS, 0x37 }, { NV04_DISPLAY_CLASS, 0x38 }, { NV04_DISPLAY_CLASS, 0x39 }, { NV04_DISPLAY_CLASS, 0x3a }, { NV04_DISPLAY_CLASS, 0x3b }, { NV04_DISPLAY_CLASS, 0x3c }, { NV04_DISPLAY_CLASS, 0x3d }, { NV04_DISPLAY_CLASS, 0x3e }, { NV04_DISPLAY_CLASS, 0x3f }, { } }; struct reg pvideo_block[] = { { NV04_OVERLAY_CLASS, 0x8080, "DEBUG_0" }, { NV04_OVERLAY_CLASS, 0x8084, "DEBUG_1" }, { NV04_OVERLAY_CLASS, 0x8088, "DEBUG_2" }, { NV04_OVERLAY_CLASS, 0x808c, "DEBUG_3" }, { NV04_OVERLAY_CLASS, 0x8090, "DEBUG_4" }, { NV04_OVERLAY_CLASS, 0x8094, "DEBUG_5" }, { NV04_OVERLAY_CLASS, 0x8098, "DEBUG_6" }, { NV04_OVERLAY_CLASS, 0x809c, "DEBUG_7" }, { NV04_OVERLAY_CLASS, 0x80a0, "DEBUG_8" }, { NV04_OVERLAY_CLASS, 0x80a4, "DEBUG_9" }, { NV04_OVERLAY_CLASS, 0x80a8, "DEBUG_10" }, { NV04_OVERLAY_CLASS, 0x8100, "INTR" }, { NV04_OVERLAY_CLASS, 0x8104, "INTR_REASON" }, { NV04_OVERLAY_CLASS, 0x8140, "INTR_EN" }, { NV04_OVERLAY_CLASS, 0x8700, "BUFFER" }, { NV04_OVERLAY_CLASS, 0x8704, "STOP" }, { NV04_OVERLAY_CLASS, 0x8900, "BASE" }, { NV04_OVERLAY_CLASS, 0x8908, "LIMIT" }, { NV04_OVERLAY_CLASS, 0x8910, "LUMINANCE" }, { NV04_OVERLAY_CLASS, 0x8918, "CHROMINANCE" }, { NV04_OVERLAY_CLASS, 0x8920, "OFFSET" }, { NV04_OVERLAY_CLASS, 0x8928, "SIZE_IN" }, { NV04_OVERLAY_CLASS, 0x8930, "POINT_IN" }, { NV04_OVERLAY_CLASS, 0x8938, "DS_DX" }, { NV04_OVERLAY_CLASS, 0x8940, "DT_DY" }, { NV04_OVERLAY_CLASS, 0x8948, "POINT_OUT" }, { NV04_OVERLAY_CLASS, 0x8950, "SIZE_OUT" }, { NV04_OVERLAY_CLASS, 0x8958, "FORMAT" }, { NV04_OVERLAY_CLASS, 0x8b00, "COLOR_KEY" }, { NV04_OVERLAY_CLASS, 0x8d00, "TEST" }, { NV04_OVERLAY_CLASS, 0x8d10, "TST_WRITE" }, { NV04_OVERLAY_CLASS, 0x8d40, "TST_READ" }, { } };