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| author | Francisco Jerez <currojerez@riseup.net> | 2020-02-06 20:59:44 -0800 |
|---|---|---|
| committer | Francisco Jerez <currojerez@riseup.net> | 2020-02-06 21:39:21 -0800 |
| commit | 199d1f5edb8c6ca470399d9459a5689543351883 (patch) | |
| tree | ffb2e78167b817a4918ef3624a0a2943c7752527 | |
| parent | 9ca23706847f797a8a9eb9e8a6483405ed348b7c (diff) | |
WIP: iris: Insert buffer-local memory barriers for indirect draw parameters.
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 204c53542ec..5c22a385cf2 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -6333,9 +6333,8 @@ iris_upload_render_state(struct iris_context *ice, unsigned draw_count_offset = draw->indirect->indirect_draw_count_offset; - iris_emit_pipe_control_flush(batch, - "ensure indirect draw buffer is flushed", - PIPE_CONTROL_FLUSH_ENABLE); + iris_emit_buffer_barrier_for(batch, draw_count_bo, + IRIS_DOMAIN_OTHER_READ); if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) { struct gen_mi_builder b; @@ -6386,6 +6385,8 @@ iris_upload_render_state(struct iris_context *ice, struct iris_bo *bo = iris_resource_bo(draw->indirect->buffer); assert(bo); + iris_emit_buffer_barrier_for(batch, bo, IRIS_DOMAIN_OTHER_READ); + iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { lrm.RegisterAddress = _3DPRIM_VERTEX_COUNT; lrm.MemoryAddress = ro_bo(bo, draw->indirect->offset + 0); |