Revert "intel/fs: Add an UNDEF instruction to avoid excess live ranges"

This reverts commit f4ef34f207d15bcade7aed644328035dd0f2cc16.

6 files changed, 5 insertions, 35 deletions

diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
index 1d4c0b83c87..b33ea6deee1 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -325,14 +325,6 @@ enum opcode {
    SHADER_OPCODE_SEND,
 
    /**
-    * An "undefined" write which does nothing but indicates to liveness that
-    * we don't care about any values in the register which predate this
-    * instruction.  Used to prevent partial writes from causing issues with
-    * live ranges.
-    */
-   SHADER_OPCODE_UNDEF,
-
-   /**
     * Texture sampling opcodes.
     *
     * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h
index 0c1b6f5d6c7..70f6e795e70 100644
--- a/src/intel/compiler/brw_fs_builder.h
+++ b/src/intel/compiler/brw_fs_builder.h
@@ -712,17 +712,6 @@ namespace brw {
          return inst;
       }
 
-      instruction *
-      UNDEF(const dst_reg &dst) const
-      {
-         assert(dst.file == VGRF);
-         instruction *inst = emit(SHADER_OPCODE_UNDEF,
-                                  retype(dst, BRW_REGISTER_TYPE_UD));
-         inst->size_written = shader->alloc.sizes[dst.nr] * REG_SIZE;
-
-         return inst;
-      }
-
       backend_shader *shader;
 
       /**
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index f230f50d58a..c2c3bcdc95b 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1679,9 +1679,6 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
    struct disasm_info *disasm_info = disasm_initialize(devinfo, cfg);
 
    foreach_block_and_inst (block, fs_inst, inst, cfg) {
-      if (inst->opcode == SHADER_OPCODE_UNDEF)
-         continue;
-
       struct brw_reg src[4], dst;
       unsigned int last_insn_offset = p->next_insn_offset;
       bool multiple_instructions_emitted = false;
diff --git a/src/intel/compiler/brw_fs_lower_regioning.cpp b/src/intel/compiler/brw_fs_lower_regioning.cpp
index 98699c38d84..a76fd262a10 100644
--- a/src/intel/compiler/brw_fs_lower_regioning.cpp
+++ b/src/intel/compiler/brw_fs_lower_regioning.cpp
@@ -288,9 +288,7 @@ namespace {
       const unsigned stride =
          type_sz(inst->dst.type) * inst->dst.stride <= type_sz(type) ? 1 :
          type_sz(inst->dst.type) * inst->dst.stride / type_sz(type);
-      fs_reg tmp = ibld.vgrf(type, stride);
-      ibld.UNDEF(tmp);
-      tmp = horiz_stride(tmp, stride);
+      const fs_reg tmp = horiz_stride(ibld.vgrf(type, stride), stride);
 
       /* Emit a MOV taking care of all the destination modifiers. */
       fs_inst *mov = ibld.at(block, inst->next).MOV(inst->dst, tmp);
@@ -331,9 +329,8 @@ namespace {
       const unsigned stride = type_sz(inst->dst.type) * inst->dst.stride /
                               type_sz(inst->src[i].type);
       assert(stride > 0);
-      fs_reg tmp = ibld.vgrf(inst->src[i].type, stride);
-      ibld.UNDEF(tmp);
-      tmp = horiz_stride(tmp, stride);
+      const fs_reg tmp = horiz_stride(ibld.vgrf(inst->src[i].type, stride),
+                                      stride);
 
       /* Emit a series of 32-bit integer copies with any source modifiers
        * cleaned up (because their semantics are dependent on the type).
@@ -380,9 +377,8 @@ namespace {
       const unsigned stride = required_dst_byte_stride(inst) /
                               type_sz(inst->dst.type);
       assert(stride > 0);
-      fs_reg tmp = ibld.vgrf(inst->dst.type, stride);
-      ibld.UNDEF(tmp);
-      tmp = horiz_stride(tmp, stride);
+      const fs_reg tmp = horiz_stride(ibld.vgrf(inst->dst.type, stride),
+                                      stride);
 
       /* Emit a series of 32-bit integer copies from the temporary into the
        * original destination.
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 0f8fc26d04d..0d17e908b43 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1932,7 +1932,6 @@ fs_visitor::get_nir_dest(const nir_dest &dest)
                                     BRW_REGISTER_TYPE_F);
       nir_ssa_values[dest.ssa.index] =
          bld.vgrf(reg_type, dest.ssa.num_components);
-      bld.UNDEF(nir_ssa_values[dest.ssa.index]);
       return nir_ssa_values[dest.ssa.index];
    } else {
       /* We don't handle indirects on locals */
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index 630a51aaf3f..e6f6f827c44 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -217,9 +217,6 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
    case SHADER_OPCODE_SEND:
       return "send";
 
-   case SHADER_OPCODE_UNDEF:
-      return "undef";
-
    case SHADER_OPCODE_TEX:
       return "tex";
    case SHADER_OPCODE_TEX_LOGICAL: