diff options
| author | Ben Widawsky <benjamin.widawsky@intel.com> | 2016-01-03 13:21:32 -0800 |
|---|---|---|
| committer | Ben Widawsky <ben@bwidawsk.net> | 2017-03-29 16:27:36 -0700 |
| commit | f94c21fc7ea49fd0ce41e0015483cf52f6242e87 (patch) | |
| tree | 1806c7f80cb4e8aa0f711ef9af20c902b8a3cf5c | |
| parent | e0b43e56180f833da144e861d1662f04c2a1cdc0 (diff) | |
i965/cnl/PO: implement temporary CNL A0 RO invalidate w/a
We could use the revision ID check and turn this into a proper patch, but this
shouldn't get upstreamed as A0 will not see the light of day.
Project GEN10:BUG:1940507 [CNL]
In A-step, Read-Only Invalidate does not flush HDC L1 Cache. Workaround is to
also set PIPE_CONTROL DC_FLUSH. Fixed in B-step.
Not-Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_pipe_control.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index 7cfeffbdaf..b74a1e4de1 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -373,7 +373,8 @@ brw_emit_mi_flush(struct brw_context *brw) PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | - PIPE_CONTROL_CS_STALL; + PIPE_CONTROL_CS_STALL | + PIPE_CONTROL_DATA_CACHE_FLUSH; } brw_emit_pipe_control_flush(brw, flags); } |