diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2011-09-22 17:12:50 -0700 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2012-03-30 14:39:02 -0700 |
| commit | 1b3a199097190a0bf857eb17c12949fa2b456d9b (patch) | |
| tree | 593268629f2979aaa7e1f286221457381c11a9d1 | |
| parent | 1ba8c6ad03a3f03ecc6b66e1c0e10a4d6010122f (diff) | |
i965: Update max VS/PS threads shift offsets for Haswell.
These now start at bit 23 instead of bit 24/25.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_hiz.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_vs_state.c | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_state.c | 4 |
4 files changed, 10 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 38ce5d7611..41534b645f 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1047,6 +1047,7 @@ enum brw_message_target { # define GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT 4 /* DW5 */ # define GEN6_VS_MAX_THREADS_SHIFT 25 +# define HSW_VS_MAX_THREADS_SHIFT 23 # define GEN6_VS_STATISTICS_ENABLE (1 << 10) # define GEN6_VS_CACHE_DISABLE (1 << 1) # define GEN6_VS_ENABLE (1 << 0) @@ -1390,7 +1391,8 @@ enum brw_wm_barycentric_interp_mode { # define GEN7_PS_FLOATING_POINT_MODE_ALT (1 << 16) /* DW3: scratch space */ /* DW4 */ -# define GEN7_PS_MAX_THREADS_SHIFT 24 +# define IVB_PS_MAX_THREADS_SHIFT 24 +# define HSW_PS_MAX_THREADS_SHIFT 23 # define GEN7_PS_PUSH_CONSTANT_ENABLE (1 << 11) # define GEN7_PS_ATTRIBUTE_ENABLE (1 << 10) # define GEN7_PS_OMASK_TO_RENDER_TARGET (1 << 9) diff --git a/src/mesa/drivers/dri/i965/gen7_hiz.c b/src/mesa/drivers/dri/i965/gen7_hiz.c index 50c265ece9..18c178eb04 100644 --- a/src/mesa/drivers/dri/i965/gen7_hiz.c +++ b/src/mesa/drivers/dri/i965/gen7_hiz.c @@ -314,7 +314,7 @@ gen7_hiz_exec(struct intel_context *intel, OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); - OUT_BATCH(((brw->max_wm_threads - 1) << GEN7_PS_MAX_THREADS_SHIFT) | + OUT_BATCH(((brw->max_wm_threads - 1) << IVB_PS_MAX_THREADS_SHIFT) | GEN7_PS_32_DISPATCH_ENABLE); OUT_BATCH(0); OUT_BATCH(0); diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c index 73822e3350..e8be4f2882 100644 --- a/src/mesa/drivers/dri/i965/gen7_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c @@ -34,6 +34,8 @@ upload_vs_state(struct brw_context *brw) { struct intel_context *intel = &brw->intel; uint32_t floating_point_mode = 0; + const int max_threads_shift = brw->intel.is_haswell ? + HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT; gen7_emit_vs_workaround_flush(intel); @@ -99,7 +101,7 @@ upload_vs_state(struct brw_context *brw) (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) | (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT)); - OUT_BATCH(((brw->max_vs_threads - 1) << GEN6_VS_MAX_THREADS_SHIFT) | + OUT_BATCH(((brw->max_vs_threads - 1) << max_threads_shift) | GEN6_VS_STATISTICS_ENABLE | GEN6_VS_ENABLE); ADVANCE_BATCH(); diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index 265ca49109..773598f2c4 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -98,6 +98,8 @@ upload_ps_state(struct brw_context *brw) { struct intel_context *intel = &brw->intel; uint32_t dw2, dw4, dw5; + const int max_threads_shift = brw->intel.is_haswell ? + HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT; /* BRW_NEW_PS_BINDING_TABLE */ BEGIN_BATCH(2); @@ -153,7 +155,7 @@ upload_ps_state(struct brw_context *brw) if (intel->ctx.Shader.CurrentFragmentProgram == NULL) dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT; - dw4 |= (brw->max_wm_threads - 1) << GEN7_PS_MAX_THREADS_SHIFT; + dw4 |= (brw->max_wm_threads - 1) << max_threads_shift; /* CACHE_NEW_WM_PROG */ if (brw->wm.prog_data->nr_params > 0) |