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authorEric Anholt <eric@anholt.net>2011-12-08 16:09:01 -0800
committerEric Anholt <eric@anholt.net>2011-12-08 16:11:04 -0800
commit9ca59f1da39a8203c0dd9815a9c45b6932eff107 (patch)
tree8dbb3a00ecfc61184aba065c2335b7424744a1fd
parent2e2d694aff3df5ba0631991cac25c66e930ef1b6 (diff)
drm/i915: Correct the length of MI_FLUSH_DW.
This command takes (cmd, addr, low, high). When we had the length wrong before, the hardware took the qwhigh value from the next dword, which was always our MI_NOOP value, and wasn't used anyway because our MI_FLUSH_DW commands didn't do post-sync stores.
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h2
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bd0f5099839..226e7ea7cf6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -182,7 +182,7 @@
* address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
*/
#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
-#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
+#define MI_FLUSH_DW MI_INSTR(0x26, 2) /* for GEN6 */
#define MI_INVALIDATE_TLB (1<<18)
#define MI_INVALIDATE_BSD (1<<7)
#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 0a1930ff3c8..b6357b11507 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1254,7 +1254,7 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
intel_ring_emit(ring, cmd);
intel_ring_emit(ring, 0);
intel_ring_emit(ring, 0);
- intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(ring, 0);
intel_ring_advance(ring);
return 0;
}
@@ -1430,7 +1430,7 @@ static int blt_ring_flush(struct intel_ring_buffer *ring,
intel_ring_emit(ring, cmd);
intel_ring_emit(ring, 0);
intel_ring_emit(ring, 0);
- intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(ring, 0);
intel_ring_advance(ring);
return 0;
}