Add some initial definitions for Sandybridge.

2 files changed, 18 insertions, 8 deletions

diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 9197ff6e..3545657e 100755
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -70,6 +70,8 @@
 #define PCI_CHIP_ILD_G                  0x0042
 #define PCI_CHIP_ILM_G                  0x0046
 
+#define PCI_CHIP_SANDYBRIDGE		0x0102
+
 #define IS_MOBILE(devid)	(devid == PCI_CHIP_I855_GM || \
 				 devid == PCI_CHIP_I915_GM || \
 				 devid == PCI_CHIP_I945_GM || \
@@ -100,15 +102,23 @@
 				 devid == PCI_CHIP_Q33_G || \
 				 devid == PCI_CHIP_Q35_G || IS_IGD(devid))
 
-#define IS_965(devid)		(devid == PCI_CHIP_I965_G || \
+#define IS_GEN4(devid)		(devid == PCI_CHIP_I965_G || \
 				 devid == PCI_CHIP_I965_Q || \
 				 devid == PCI_CHIP_I965_G_1 || \
 				 devid == PCI_CHIP_I965_GM || \
 				 devid == PCI_CHIP_I965_GME || \
 				 devid == PCI_CHIP_I946_GZ || \
-				 IS_G4X(devid) || \
-				 IS_IRONLAKE(devid))
+				 IS_G4X(devid))
+
+#define IS_965(devid)		(IS_GEN4(devid) || \
+				 IS_IRONLAKE(devid) || \
+				 IS_GEN6(devid))
+
+#define IS_GEN6(devid)		(devid == PCI_CHIP_SANDYBRIDGE)
 
 #define IS_9XX(devid)		(IS_915(devid) || \
 				 IS_945(devid) || \
 				 IS_965(devid))
+
+#define HAS_PCH_SPLIT(devid)	(IS_IRONLAKE(devid) ||	\
+				 IS_GEN6(devid))
diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
index d21e6763..125434ba 100644
--- a/tools/intel_reg_dumper.c
+++ b/tools/intel_reg_dumper.c
@@ -131,7 +131,7 @@ DEBUGSTRING(i830_debug_dspcntr)
 {
 	char *enabled = val & DISPLAY_PLANE_ENABLE ? "enabled" : "disabled";
 	char plane = val & DISPPLANE_SEL_PIPE_B ? 'B' : 'A';
-	if (IS_IRONLAKE(devid))
+	if (HAS_PCH_SPLIT(devid))
 		asprintf(result, "%s", enabled);
 	else
 		asprintf(result, "%s, pipe %c", enabled, plane);
@@ -149,7 +149,7 @@ DEBUGSTRING(i830_debug_pipeconf)
 		bit30 =
 		    val & PIPEACONF_DOUBLE_WIDE ? "double-wide" : "single-wide";
 
-	if (IS_IRONLAKE(devid)) {
+	if (HAS_PCH_SPLIT(devid)) {
 		switch (val & (7 << 5)) {
 		case PIPECONF_8BPP:
 			bpc = "8bpc";
@@ -165,7 +165,7 @@ DEBUGSTRING(i830_debug_pipeconf)
 			break;
 		}
 	}
-	if (IS_IRONLAKE(devid))
+	if (HAS_PCH_SPLIT(devid))
 		asprintf(result, "%s, %s, %s", enabled, bit30, bpc);
 	else
 		asprintf(result, "%s, %s", enabled, bit30);
@@ -447,7 +447,7 @@ DEBUGSTRING(i830_debug_adpa)
 	char hsync = (val & ADPA_HSYNC_ACTIVE_HIGH) ? '+' : '-';
 	char vsync = (val & ADPA_VSYNC_ACTIVE_HIGH) ? '+' : '-';
 
-	if (IS_IRONLAKE(devid))
+	if (HAS_PCH_SPLIT(devid))
 		asprintf(result, "%s, transcoder %c, %chsync, %cvsync",
 				 enable, pipe, hsync, vsync);
 	else
@@ -1655,7 +1655,7 @@ int main(int argc, char** argv)
 {
 	intel_get_mmio();
 
-	if (IS_IRONLAKE(devid))
+	if (HAS_PCH_SPLIT(devid))
 		ironlake_dump_regs();
 	else
 		intel_dump_regs();