amdgpu/cs: add new raw cs submission interface just taking chunks

This switches the other API to use the new lower level api.

Signed-off-by: Dave Airlie <airlied@redhat.com>

2 files changed, 49 insertions, 23 deletions

diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index f3b67e88..f57a782e 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1340,6 +1340,13 @@ int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
 int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
 			      uint32_t syncobj);
 
+struct drm_amdgpu_cs_chunk;
+int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
+			 amdgpu_context_handle *context,
+			 uint32_t bo_list_handle,
+			 int num_chunks,
+			 struct drm_amdgpu_cs_chunk *chunks,
+			 uint64_t *seq_no);
 #ifdef __cplusplus
 }
 #endif
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index fb74acb2..f71f1337 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -232,14 +232,13 @@ static void amdgpu_cs_update_context_seq(amdgpu_context_handle context,
 static int amdgpu_cs_submit_one(amdgpu_context_handle context,
 				struct amdgpu_cs_request *ibs_request)
 {
-	union drm_amdgpu_cs cs;
-	uint64_t *chunk_array;
 	struct drm_amdgpu_cs_chunk *chunks;
 	struct drm_amdgpu_cs_chunk_data *chunk_data;
 	struct drm_amdgpu_cs_chunk_dep *dependencies = NULL;
 	void *to_free = NULL;
 	uint32_t i, size;
 	bool user_fence;
+	uint32_t num_chunks;
 	int r = 0;
 
 	if (ibs_request->ip_type >= AMDGPU_HW_IP_NUM)
@@ -256,23 +255,15 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context,
 
 	size = ibs_request->number_of_ibs + (user_fence ? 2 : 1) + 1;
 
-	chunk_array = alloca(sizeof(uint64_t) * size);
 	chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size);
 
 	size = ibs_request->number_of_ibs + (user_fence ? 1 : 0);
 
 	chunk_data = alloca(sizeof(struct drm_amdgpu_cs_chunk_data) * size);
-
-	memset(&cs, 0, sizeof(cs));
-	cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
-	cs.in.ctx_id = context->id;
-	if (ibs_request->resources)
-		cs.in.bo_list_handle = ibs_request->resources->handle;
-	cs.in.num_chunks = ibs_request->number_of_ibs;
+	num_chunks = ibs_request->number_of_ibs;
 	/* IB chunks */
 	for (i = 0; i < ibs_request->number_of_ibs; i++) {
 		struct amdgpu_cs_ib_info *ib;
-		chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
 		chunks[i].chunk_id = AMDGPU_CHUNK_ID_IB;
 		chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
 		chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
@@ -289,10 +280,9 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context,
 	}
 
 	if (user_fence) {
-		i = cs.in.num_chunks++;
+		i = num_chunks++;
 
 		/* fence chunk */
-		chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
 		chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
 		chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
 		chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
@@ -322,10 +312,9 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context,
 			dep->handle = info->fence;
 		}
 
-		i = cs.in.num_chunks++;
+		i = num_chunks++;
 
 		/* dependencies chunk */
-		chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
 		chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
 		chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4
 			* ibs_request->number_of_dependencies;
@@ -333,21 +322,21 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context,
 	}
 
 	r = amdgpu_cs_allocate_sem_chunk(context,
-					 ibs_request, &chunks[cs.in.num_chunks + 1]);
+					 ibs_request, &chunks[num_chunks + 1]);
 	if (r < 0)
 		goto error_out;
 	if (r > 0) {
-		cs.in.num_chunks++;
-		chunk_array[i] = (uint64_t)(uintptr_t)&chunks[cs.in.num_chunks];
-		to_free = &chunks[cs.in.num_chunks].chunk_data;
+		i = num_chunks++;
+		to_free = &chunks[i].chunk_data;
 	}
 
-	r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CS,
-				&cs, sizeof(cs));
+	r = amdgpu_cs_submit_raw(context->dev, context->id,
+				 ibs_request->resources ? ibs_request->resources->handle : 0,
+				 num_chunks,
+				 chunks,
+				 &ibs_request->seq_no);
 	if (r)
 		goto error_out;
-
-	ibs_request->seq_no = cs.out.handle;
 	amdgpu_cs_update_context_seq(context, ibs_request);
 error_out:
 	free(dependencies);
@@ -670,3 +659,33 @@ int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
 
 	return drmSyncobjFDToHandle(dev->fd, shared_fd, handle);
 }
+
+int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
+			 amdgpu_context_handle *context,
+			 uint32_t bo_list_handle,
+			 int num_chunks,
+			 struct drm_amdgpu_cs_chunk *chunks,
+			 uint64_t *seq_no)
+{
+	union drm_amdgpu_cs cs = {0};
+	uint64_t *chunk_array;
+	int i, r;
+	if (num_chunks == 0)
+		return -EINVAL;
+
+	chunk_array = alloca(sizeof(uint64_t) * num_chunks);
+	for (i = 0; i < num_chunks; i++)
+		chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
+	cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
+	cs.in.ctx_id = context->ctx_id;
+	cs.in.bo_list_handle = bo_list_handle;
+	cs.in.num_chunks = num_chunks;
+	r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS,
+				&cs, sizeof(cs));
+	if (r)
+		return r;
+
+	if (seq_no)
+		*seq_no = cs.out.handle;
+	return 0;
+}