/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.12 2001/09/25 14:58:50 alanh Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and * VA Linux Systems Inc., Fremont, California. * * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation on the rights to use, copy, modify, merge, * publish, distribute, sublicense, and/or sell copies of the Software, * and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ /* * Authors: * Kevin E. Martin * Rickard E. Faith * Alan Hourihane * * References: * * !!!! FIXME !!!! * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April * 1999. * * !!!! FIXME !!!! * RAGE 128 Software Development Manual (Technical Reference Manual P/N * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. * */ /* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ #ifndef _RADEON_REG_H_ #define _RADEON_REG_H_ /* Atomic updates of PLL clock don't seem to always work and stick, thus * the bit never resets. Here - we use our own check by reading back the * register we've just wrote to make sure it's got the Right! value */ #define RADEON_ATOMIC_UPDATE 0 /* Use PLL Atomic updates (seems broken) */ /* Memory mapped register access macros */ #define INREG8(addr) MMIO_IN8(RADEONMMIO, addr) #define INREG16(addr) MMIO_IN16(RADEONMMIO, addr) #define INREG(addr) MMIO_IN32(RADEONMMIO, addr) #define OUTREG8(addr, val) MMIO_OUT8(RADEONMMIO, addr, val) #define OUTREG16(addr, val) MMIO_OUT16(RADEONMMIO, addr, val) #define OUTREG(addr, val) MMIO_OUT32(RADEONMMIO, addr, val) #define ADDRREG(addr) ((volatile CARD32 *)(pointer)(RADEONMMIO + (addr))) #define OUTREGP(addr, val, mask) \ do { \ CARD32 tmp = INREG(addr); \ tmp &= (mask); \ tmp |= (val); \ OUTREG(addr, tmp); \ } while (0) #define INPLL(pScrn, addr) RADEONINPLL(pScrn, addr) #define OUTPLL(addr, val) \ do { \ OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | \ RADEON_PLL_WR_EN)); \ OUTREG(RADEON_CLOCK_CNTL_DATA, val); \ } while (0) #define OUTPLLP(pScrn, addr, val, mask) \ do { \ CARD32 tmp = INPLL(pScrn, addr); \ tmp &= (mask); \ tmp |= (val); \ OUTPLL(addr, tmp); \ } while (0) #define OUTPAL_START(idx) \ do { \ OUTREG8(RADEON_PALETTE_INDEX, (idx)); \ } while (0) #define OUTPAL_NEXT(r, g, b) \ do { \ OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \ } while (0) #define OUTPAL_NEXT_CARD32(v) \ do { \ OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff)); \ } while (0) #define OUTPAL(idx, r, g, b) \ do { \ OUTPAL_START((idx)); \ OUTPAL_NEXT((r), (g), (b)); \ } while (0) #define INPAL_START(idx) \ do { \ OUTREG(RADEON_PALETTE_INDEX, (idx) << 16); \ } while (0) #define INPAL_NEXT() INREG(RADEON_PALETTE_DATA) #define PAL_SELECT(idx) \ do { \ if (!idx) { \ OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \ (CARD32)~RADEON_DAC2_PALETTE_ACC_CTL); \ } else { \ OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \ RADEON_DAC2_PALETTE_ACC_CTL); \ } \ } while (0) #define RADEON_ADAPTER_ID 0x0f2c /* PCI */ #define RADEON_FW_CNTL 0x118 #define RADEON_FW_STATUS 0x11c #define RADEON_AGP_BASE 0x0170 #define RADEON_AGP_CNTL 0x0174 # define RADEON_AGP_APER_SIZE_256MB (0x00 << 0) # define RADEON_AGP_APER_SIZE_128MB (0x20 << 0) # define RADEON_AGP_APER_SIZE_64MB (0x30 << 0) # define RADEON_AGP_APER_SIZE_32MB (0x38 << 0) # define RADEON_AGP_APER_SIZE_16MB (0x3c << 0) # define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) # define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) # define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) #define RADEON_STATUS_PCI_CONFIG 0x06 # define RADEON_CAP_LIST 0x100000 #define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/ # define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */ # define RADEON_CAP_ID_NULL 0x00 /* End of capability list */ # define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */ # define RADEON_CAP_ID_EXP 0x10 /* PCI Express */ #define RADEON_AGP_COMMAND 0x0f60 /* PCI */ #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ # define RADEON_AGP_ENABLE (1<<8) #define RADEON_AGP_PLL_CNTL 0x000b /* PLL */ #define RADEON_AGP_STATUS 0x0f5c /* PCI */ # define RADEON_AGP_1X_MODE 0x01 # define RADEON_AGP_2X_MODE 0x02 # define RADEON_AGP_4X_MODE 0x04 # define RADEON_AGP_MODE_MASK 0x07 #define RADEON_AMCGPIO_A_REG 0x01a0 #define RADEON_AMCGPIO_EN_REG 0x01a8 #define RADEON_AMCGPIO_MASK 0x0194 #define RADEON_AMCGPIO_Y_REG 0x01a4 #define RADEON_ATTRDR 0x03c1 /* VGA */ #define RADEON_ATTRDW 0x03c0 /* VGA */ #define RADEON_ATTRX 0x03c0 /* VGA */ #define RADEON_AUX_SC_CNTL 0x1660 # define RADEON_AUX1_SC_EN (1 << 0) # define RADEON_AUX1_SC_MODE_OR (0 << 1) # define RADEON_AUX1_SC_MODE_NAND (1 << 1) # define RADEON_AUX2_SC_EN (1 << 2) # define RADEON_AUX2_SC_MODE_OR (0 << 3) # define RADEON_AUX2_SC_MODE_NAND (1 << 3) # define RADEON_AUX3_SC_EN (1 << 4) # define RADEON_AUX3_SC_MODE_OR (0 << 5) # define RADEON_AUX3_SC_MODE_NAND (1 << 5) #define RADEON_AUX1_SC_BOTTOM 0x1670 #define RADEON_AUX1_SC_LEFT 0x1664 #define RADEON_AUX1_SC_RIGHT 0x1668 #define RADEON_AUX1_SC_TOP 0x166c #define RADEON_AUX2_SC_BOTTOM 0x1680 #define RADEON_AUX2_SC_LEFT 0x1674 #define RADEON_AUX2_SC_RIGHT 0x1678 #define RADEON_AUX2_SC_TOP 0x167c #define RADEON_AUX3_SC_BOTTOM 0x1690 #define RADEON_AUX3_SC_LEFT 0x1684 #define RADEON_AUX3_SC_RIGHT 0x1688 #define RADEON_AUX3_SC_TOP 0x168c #define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8 #define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc #define RADEON_BASE_CODE 0x0f0b #define RADEON_BIOS_0_SCRATCH 0x0010 #define RADEON_BIOS_1_SCRATCH 0x0014 #define RADEON_BIOS_2_SCRATCH 0x0018 #define RADEON_BIOS_3_SCRATCH 0x001c #define RADEON_BIOS_4_SCRATCH 0x0020 #define RADEON_BIOS_5_SCRATCH 0x0024 #define RADEON_BIOS_6_SCRATCH 0x0028 #define RADEON_BIOS_7_SCRATCH 0x002c #define RADEON_BIOS_ROM 0x0f30 /* PCI */ #define RADEON_BIST 0x0f0f /* PCI */ #define RADEON_BRUSH_DATA0 0x1480 #define RADEON_BRUSH_DATA1 0x1484 #define RADEON_BRUSH_DATA10 0x14a8 #define RADEON_BRUSH_DATA11 0x14ac #define RADEON_BRUSH_DATA12 0x14b0 #define RADEON_BRUSH_DATA13 0x14b4 #define RADEON_BRUSH_DATA14 0x14b8 #define RADEON_BRUSH_DATA15 0x14bc #define RADEON_BRUSH_DATA16 0x14c0 #define RADEON_BRUSH_DATA17 0x14c4 #define RADEON_BRUSH_DATA18 0x14c8 #define RADEON_BRUSH_DATA19 0x14cc #define RADEON_BRUSH_DATA2 0x1488 #define RADEON_BRUSH_DATA20 0x14d0 #define RADEON_BRUSH_DATA21 0x14d4 #define RADEON_BRUSH_DATA22 0x14d8 #define RADEON_BRUSH_DATA23 0x14dc #define RADEON_BRUSH_DATA24 0x14e0 #define RADEON_BRUSH_DATA25 0x14e4 #define RADEON_BRUSH_DATA26 0x14e8 #define RADEON_BRUSH_DATA27 0x14ec #define RADEON_BRUSH_DATA28 0x14f0 #define RADEON_BRUSH_DATA29 0x14f4 #define RADEON_BRUSH_DATA3 0x148c #define RADEON_BRUSH_DATA30 0x14f8 #define RADEON_BRUSH_DATA31 0x14fc #define RADEON_BRUSH_DATA32 0x1500 #define RADEON_BRUSH_DATA33 0x1504 #define RADEON_BRUSH_DATA34 0x1508 #define RADEON_BRUSH_DATA35 0x150c #define RADEON_BRUSH_DATA36 0x1510 #define RADEON_BRUSH_DATA37 0x1514 #define RADEON_BRUSH_DATA38 0x1518 #define RADEON_BRUSH_DATA39 0x151c #define RADEON_BRUSH_DATA4 0x1490 #define RADEON_BRUSH_DATA40 0x1520 #define RADEON_BRUSH_DATA41 0x1524 #define RADEON_BRUSH_DATA42 0x1528 #define RADEON_BRUSH_DATA43 0x152c #define RADEON_BRUSH_DATA44 0x1530 #define RADEON_BRUSH_DATA45 0x1534 #define RADEON_BRUSH_DATA46 0x1538 #define RADEON_BRUSH_DATA47 0x153c #define RADEON_BRUSH_DATA48 0x1540 #define RADEON_BRUSH_DATA49 0x1544 #define RADEON_BRUSH_DATA5 0x1494 #define RADEON_BRUSH_DATA50 0x1548 #define RADEON_BRUSH_DATA51 0x154c #define RADEON_BRUSH_DATA52 0x1550 #define RADEON_BRUSH_DATA53 0x1554 #define RADEON_BRUSH_DATA54 0x1558 #define RADEON_BRUSH_DATA55 0x155c #define RADEON_BRUSH_DATA56 0x1560 #define RADEON_BRUSH_DATA57 0x1564 #define RADEON_BRUSH_DATA58 0x1568 #define RADEON_BRUSH_DATA59 0x156c #define RADEON_BRUSH_DATA6 0x1498 #define RADEON_BRUSH_DATA60 0x1570 #define RADEON_BRUSH_DATA61 0x1574 #define RADEON_BRUSH_DATA62 0x1578 #define RADEON_BRUSH_DATA63 0x157c #define RADEON_BRUSH_DATA7 0x149c #define RADEON_BRUSH_DATA8 0x14a0 #define RADEON_BRUSH_DATA9 0x14a4 #define RADEON_BRUSH_SCALE 0x1470 #define RADEON_BRUSH_Y_X 0x1474 #define RADEON_BUS_CNTL 0x0030 # define RADEON_BUS_MASTER_DIS (1 << 6) # define RADEON_BUS_RD_DISCARD_EN (1 << 24) # define RADEON_BUS_RD_ABORT_EN (1 << 25) # define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) # define RADEON_BUS_WRT_BURST (1 << 29) # define RADEON_BUS_READ_BURST (1 << 30) #define RADEON_BUS_CNTL1 0x0034 # define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) #define RADEON_CACHE_CNTL 0x1724 #define RADEON_CACHE_LINE 0x0f0c /* PCI */ #define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ #define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */ #define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ #define RADEON_CLOCK_CNTL_DATA 0x000c #define RADEON_CLOCK_CNTL_INDEX 0x0008 # define RADEON_PLL_WR_EN (1 << 7) # define RADEON_PLL_DIV_SEL (3 << 8) # define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) #define RADEON_CLR_CMP_CLR_3D 0x1a24 #define RADEON_CLR_CMP_CLR_DST 0x15c8 #define RADEON_CLR_CMP_CLR_SRC 0x15c4 #define RADEON_CLR_CMP_CNTL 0x15c0 # define RADEON_SRC_CMP_EQ_COLOR (4 << 0) # define RADEON_SRC_CMP_NEQ_COLOR (5 << 0) # define RADEON_CLR_CMP_SRC_SOURCE (1 << 24) #define RADEON_CLR_CMP_MASK 0x15cc # define RADEON_CLR_CMP_MSK 0xffffffff #define RADEON_CLR_CMP_MASK_3D 0x1A28 #define RADEON_COMMAND 0x0f04 /* PCI */ #define RADEON_COMPOSITE_SHADOW_ID 0x1a0c #define RADEON_CONFIG_APER_0_BASE 0x0100 #define RADEON_CONFIG_APER_1_BASE 0x0104 #define RADEON_CONFIG_APER_SIZE 0x0108 #define RADEON_CONFIG_BONDS 0x00e8 #define RADEON_CONFIG_CNTL 0x00e0 #define RADEON_CONFIG_MEMSIZE 0x00f8 #define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114 #define RADEON_CONFIG_REG_1_BASE 0x010c #define RADEON_CONFIG_REG_APER_SIZE 0x0110 #define RADEON_CONFIG_XSTRAP 0x00e4 #define RADEON_CONSTANT_COLOR_C 0x1d34 # define RADEON_CONSTANT_COLOR_MASK 0x00ffffff # define RADEON_CONSTANT_COLOR_ONE 0x00ffffff # define RADEON_CONSTANT_COLOR_ZERO 0x00000000 #define RADEON_CRC_CMDFIFO_ADDR 0x0740 #define RADEON_CRC_CMDFIFO_DOUT 0x0744 #define RADEON_GRPH_BUFFER_CNTL 0x02f0 # define RADEON_GRPH_START_REQ_MASK (0x7f) # define RADEON_GRPH_START_REQ_SHIFT 0 # define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8) # define RADEON_GRPH_STOP_REQ_SHIFT 8 # define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16) # define RADEON_GRPH_CRITICAL_POINT_SHIFT 16 # define RADEON_GRPH_CRITICAL_CNTL (1<<28) # define RADEON_GRPH_BUFFER_SIZE (1<<29) # define RADEON_GRPH_CRITICAL_AT_SOF (1<<30) # define RADEON_GRPH_STOP_CNTL (1<<31) #define RADEON_GRPH2_BUFFER_CNTL 0x03f0 # define RADEON_GRPH2_START_REQ_MASK (0x7f) # define RADEON_GRPH2_START_REQ_SHIFT 0 # define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8) # define RADEON_GRPH2_STOP_REQ_SHIFT 8 # define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16) # define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16 # define RADEON_GRPH2_CRITICAL_CNTL (1<<28) # define RADEON_GRPH2_BUFFER_SIZE (1<<29) # define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30) # define RADEON_GRPH2_STOP_CNTL (1<<31) #define RADEON_CRTC_CRNT_FRAME 0x0214 #define RADEON_CRTC_DEBUG 0x021c #define RADEON_CRTC_EXT_CNTL 0x0054 # define RADEON_CRTC_VGA_XOVERSCAN (1 << 0) # define RADEON_VGA_ATI_LINEAR (1 << 3) # define RADEON_XCRT_CNT_EN (1 << 6) # define RADEON_CRTC_HSYNC_DIS (1 << 8) # define RADEON_CRTC_VSYNC_DIS (1 << 9) # define RADEON_CRTC_DISPLAY_DIS (1 << 10) # define RADEON_CRTC_SYNC_TRISTAT (1 << 11) # define RADEON_CRTC_CRT_ON (1 << 15) #define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 # define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0) # define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1) # define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2) #define RADEON_CRTC_GEN_CNTL 0x0050 # define RADEON_CRTC_DBL_SCAN_EN (1 << 0) # define RADEON_CRTC_INTERLACE_EN (1 << 1) # define RADEON_CRTC_CSYNC_EN (1 << 4) # define RADEON_CRTC_ICON_EN (1 << 15) # define RADEON_CRTC_CUR_EN (1 << 16) # define RADEON_CRTC_CUR_MODE_MASK (7 << 20) # define RADEON_CRTC_EXT_DISP_EN (1 << 24) # define RADEON_CRTC_EN (1 << 25) # define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) #define RADEON_CRTC2_GEN_CNTL 0x03f8 # define RADEON_CRTC2_DBL_SCAN_EN (1 << 0) # define RADEON_CRTC2_INTERLACE_EN (1 << 1) # define RADEON_CRTC2_SYNC_TRISTAT (1 << 4) # define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5) # define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6) # define RADEON_CRTC2_CRT2_ON (1 << 7) # define RADEON_CRTC2_ICON_EN (1 << 15) # define RADEON_CRTC2_CUR_EN (1 << 16) # define RADEON_CRTC2_CUR_MODE_MASK (7 << 20) # define RADEON_CRTC2_DISP_DIS (1 << 23) # define RADEON_CRTC2_EN (1 << 25) # define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26) # define RADEON_CRTC2_HSYNC_DIS (1 << 28) # define RADEON_CRTC2_VSYNC_DIS (1 << 29) #define RADEON_CRTC_MORE_CNTL 0x27c # define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2) # define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3) # define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) # define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) #define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 #define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 # define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) # define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) # define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 # define RADEON_CRTC_H_SYNC_WID (0x3f << 16) # define RADEON_CRTC_H_SYNC_WID_SHIFT 16 # define RADEON_CRTC_H_SYNC_POL (1 << 23) #define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304 # define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) # define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) # define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 # define RADEON_CRTC2_H_SYNC_WID (0x3f << 16) # define RADEON_CRTC2_H_SYNC_WID_SHIFT 16 # define RADEON_CRTC2_H_SYNC_POL (1 << 23) #define RADEON_CRTC_H_TOTAL_DISP 0x0200 # define RADEON_CRTC_H_TOTAL (0x03ff << 0) # define RADEON_CRTC_H_TOTAL_SHIFT 0 # define RADEON_CRTC_H_DISP (0x01ff << 16) # define RADEON_CRTC_H_DISP_SHIFT 16 #define RADEON_CRTC2_H_TOTAL_DISP 0x0300 # define RADEON_CRTC2_H_TOTAL (0x03ff << 0) # define RADEON_CRTC2_H_TOTAL_SHIFT 0 # define RADEON_CRTC2_H_DISP (0x01ff << 16) # define RADEON_CRTC2_H_DISP_SHIFT 16 #define RADEON_CRTC_OFFSET_RIGHT 0x0220 #define RADEON_CRTC_OFFSET 0x0224 #define RADEON_CRTC2_OFFSET 0x0324 #define RADEON_CRTC_OFFSET_CNTL 0x0228 # define RADEON_CRTC_TILE_LINE_SHIFT 0 # define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4 # define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6) # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7) # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7) # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7) # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7) # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7) # define R300_CRTC_X_Y_MODE_EN (1 << 9) # define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10) # define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10) # define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10) # define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10) # define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10) # define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12) # define R300_CRTC_MICRO_TILE_EN (1 << 13) # define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14) # define R300_CRTC_MACRO_TILE_EN (1 << 15) # define RADEON_CRTC_TILE_EN_RIGHT (1 << 14) # define RADEON_CRTC_TILE_EN (1 << 15) # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) # define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17) #define RADEON_FP_CRTC2_H_TOTAL_DISP 0x0350 #define RADEON_FP_CRTC2_V_TOTAL_DISP 0x0354 #define R300_CRTC_TILE_X0_Y0 0x0350 #define R300_CRTC2_TILE_X0_Y0 0x0358 #define RADEON_CRTC2_OFFSET_CNTL 0x0328 # define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16) # define RADEON_CRTC2_TILE_EN (1 << 15) #define RADEON_CRTC_PITCH 0x022c # define RADEON_CRTC_PITCH__SHIFT 0 # define RADEON_CRTC_PITCH__RIGHT_SHIFT 16 #define RADEON_CRTC2_PITCH 0x032c #define RADEON_CRTC_STATUS 0x005c # define RADEON_CRTC_VBLANK_SAVE (1 << 1) # define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1) #define RADEON_CRTC2_STATUS 0x03fc # define RADEON_CRTC2_VBLANK_SAVE (1 << 1) # define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1) #define RADEON_CRTC_V_SYNC_STRT_WID 0x020c # define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0) # define RADEON_CRTC_V_SYNC_STRT_SHIFT 0 # define RADEON_CRTC_V_SYNC_WID (0x1f << 16) # define RADEON_CRTC_V_SYNC_WID_SHIFT 16 # define RADEON_CRTC_V_SYNC_POL (1 << 23) #define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c # define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0) # define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0 # define RADEON_CRTC2_V_SYNC_WID (0x1f << 16) # define RADEON_CRTC2_V_SYNC_WID_SHIFT 16 # define RADEON_CRTC2_V_SYNC_POL (1 << 23) #define RADEON_CRTC_V_TOTAL_DISP 0x0208 # define RADEON_CRTC_V_TOTAL (0x07ff << 0) # define RADEON_CRTC_V_TOTAL_SHIFT 0 # define RADEON_CRTC_V_DISP (0x07ff << 16) # define RADEON_CRTC_V_DISP_SHIFT 16 #define RADEON_CRTC2_V_TOTAL_DISP 0x0308 # define RADEON_CRTC2_V_TOTAL (0x07ff << 0) # define RADEON_CRTC2_V_TOTAL_SHIFT 0 # define RADEON_CRTC2_V_DISP (0x07ff << 16) # define RADEON_CRTC2_V_DISP_SHIFT 16 #define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210 # define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16) #define RADEON_CRTC2_CRNT_FRAME 0x0314 #define RADEON_CRTC2_DEBUG 0x031c #define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318 #define RADEON_CRTC2_STATUS 0x03fc #define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310 #define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ #define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ #define RADEON_CUR_CLR0 0x026c #define RADEON_CUR_CLR1 0x0270 #define RADEON_CUR_HORZ_VERT_OFF 0x0268 #define RADEON_CUR_HORZ_VERT_POSN 0x0264 #define RADEON_CUR_OFFSET 0x0260 # define RADEON_CUR_LOCK (1 << 31) #define RADEON_CUR2_CLR0 0x036c #define RADEON_CUR2_CLR1 0x0370 #define RADEON_CUR2_HORZ_VERT_OFF 0x0368 #define RADEON_CUR2_HORZ_VERT_POSN 0x0364 #define RADEON_CUR2_OFFSET 0x0360 # define RADEON_CUR2_LOCK (1 << 31) #define RADEON_DAC_CNTL 0x0058 # define RADEON_DAC_RANGE_CNTL (3 << 0) # define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0) # define RADEON_DAC_RANGE_CNTL_MASK 0x03 # define RADEON_DAC_BLANKING (1 << 2) # define RADEON_DAC_CMP_EN (1 << 3) # define RADEON_DAC_CMP_OUTPUT (1 << 7) # define RADEON_DAC_8BIT_EN (1 << 8) # define RADEON_DAC_TVO_EN (1 << 10) # define RADEON_DAC_VGA_ADR_EN (1 << 13) # define RADEON_DAC_PDWN (1 << 15) # define RADEON_DAC_MASK_ALL (0xff << 24) #define RADEON_DAC_CNTL2 0x007c # define RADEON_DAC2_TV_CLK_SEL (0 << 1) # define RADEON_DAC2_DAC_CLK_SEL (1 << 0) # define RADEON_DAC2_DAC2_CLK_SEL (1 << 1) # define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5) # define RADEON_DAC2_CMP_EN (1 << 7) # define RADEON_DAC2_CMP_OUT_R (1 << 8) # define RADEON_DAC2_CMP_OUT_G (1 << 9) # define RADEON_DAC2_CMP_OUT_B (1 << 10) # define RADEON_DAC2_CMP_OUTPUT (1 << 11) #define RADEON_DAC_EXT_CNTL 0x0280 # define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0) # define RADEON_DAC2_FORCE_DATA_EN (1 << 1) # define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4) # define RADEON_DAC_FORCE_DATA_EN (1 << 5) # define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6) # define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6) # define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6) # define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6) # define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6) # define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00 # define RADEON_DAC_FORCE_DATA_SHIFT 8 #define RADEON_DAC_MACRO_CNTL 0x0d04 # define RADEON_DAC_PDWN_R (1 << 16) # define RADEON_DAC_PDWN_G (1 << 17) # define RADEON_DAC_PDWN_B (1 << 18) #define RADEON_TV_DAC_CNTL 0x088c # define RADEON_TV_DAC_NBLANK (1 << 0) # define RADEON_TV_DAC_NHOLD (1 << 1) # define RADEON_TV_DAC_PEDESTAL (1 << 2) # define RADEON_TV_MONITOR_DETECT_EN (1 << 4) # define RADEON_TV_DAC_CMPOUT (1 << 5) # define RADEON_TV_DAC_STD_MASK (3 << 8) # define RADEON_TV_DAC_STD_PAL (0 << 8) # define RADEON_TV_DAC_STD_NTSC (1 << 8) # define RADEON_TV_DAC_STD_PS2 (2 << 8) # define RADEON_TV_DAC_STD_RS343 (3 << 8) # define RADEON_TV_DAC_BGSLEEP (1 << 6) # define RADEON_TV_DAC_BGADJ_MASK (0xf << 16) # define RADEON_TV_DAC_BGADJ_SHIFT 16 # define RADEON_TV_DAC_DACADJ_MASK (0xf << 20) # define RADEON_TV_DAC_DACADJ_SHIFT 20 # define RADEON_TV_DAC_RDACPD (1 << 24) # define RADEON_TV_DAC_GDACPD (1 << 25) # define RADEON_TV_DAC_BDACPD (1 << 26) # define RADEON_TV_DAC_RDACDET (1 << 29) # define RADEON_TV_DAC_GDACDET (1 << 30) # define RADEON_TV_DAC_BDACDET (1 << 31) # define R420_TV_DAC_DACADJ_MASK (0x1f << 20) # define R420_TV_DAC_RDACPD (1 << 25) # define R420_TV_DAC_GDACPD (1 << 26) # define R420_TV_DAC_BDACPD (1 << 27) # define R420_TV_DAC_TVENABLE (1 << 28) #define RADEON_DISP_HW_DEBUG 0x0d14 # define RADEON_CRT2_DISP1_SEL (1 << 5) #define RADEON_DISP_OUTPUT_CNTL 0x0d64 # define RADEON_DISP_DAC_SOURCE_MASK 0x03 # define RADEON_DISP_DAC2_SOURCE_MASK 0x0c # define RADEON_DISP_DAC_SOURCE_CRTC2 0x01 # define RADEON_DISP_DAC_SOURCE_RMX 0x02 # define RADEON_DISP_DAC_SOURCE_LTU 0x03 # define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04 # define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2) # define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0 # define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2) # define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2) # define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2) # define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4) # define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4) # define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4) # define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4) # define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */ # define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */ #define RADEON_DISP_TV_OUT_CNTL 0x0d6c # define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16) # define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16) #define RADEON_DAC_CRC_SIG 0x02cc #define RADEON_DAC_DATA 0x03c9 /* VGA */ #define RADEON_DAC_MASK 0x03c6 /* VGA */ #define RADEON_DAC_R_INDEX 0x03c7 /* VGA */ #define RADEON_DAC_W_INDEX 0x03c8 /* VGA */ #define RADEON_DDA_CONFIG 0x02e0 #define RADEON_DDA_ON_OFF 0x02e4 #define RADEON_DEFAULT_OFFSET 0x16e0 #define RADEON_DEFAULT_PITCH 0x16e4 #define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 # define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) # define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) #define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820 #define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824 #define RADEON_DEVICE_ID 0x0f02 /* PCI */ #define RADEON_DISP_MISC_CNTL 0x0d00 # define RADEON_SOFT_RESET_GRPH_PP (1 << 0) #define RADEON_DISP_MERGE_CNTL 0x0d60 # define RADEON_DISP_ALPHA_MODE_MASK 0x03 # define RADEON_DISP_ALPHA_MODE_KEY 0 # define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1 # define RADEON_DISP_ALPHA_MODE_GLOBAL 2 # define RADEON_DISP_RGB_OFFSET_EN (1 << 8) # define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16) # define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24) # define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9) #define RADEON_DISP2_MERGE_CNTL 0x0d68 # define RADEON_DISP2_RGB_OFFSET_EN (1 << 8) #define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80 #define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84 #define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88 #define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c #define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90 #define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98 #define RADEON_DP_BRUSH_BKGD_CLR 0x1478 #define RADEON_DP_BRUSH_FRGD_CLR 0x147c #define RADEON_DP_CNTL 0x16c0 # define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0) # define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1) # define RADEON_DP_DST_TILE_LINEAR (0 << 3) # define RADEON_DP_DST_TILE_MACRO (1 << 3) # define RADEON_DP_DST_TILE_MICRO (2 << 3) # define RADEON_DP_DST_TILE_BOTH (3 << 3) #define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 # define RADEON_DST_Y_MAJOR (1 << 2) # define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) # define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) #define RADEON_DP_DATATYPE 0x16c4 # define RADEON_HOST_BIG_ENDIAN_EN (1 << 29) #define RADEON_DP_GUI_MASTER_CNTL 0x146c # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) # define RADEON_GMC_SRC_CLIPPING (1 << 2) # define RADEON_GMC_DST_CLIPPING (1 << 3) # define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) # define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) # define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) # define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) # define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) # define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) # define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) # define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) # define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) # define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4) # define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4) # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) # define RADEON_GMC_BRUSH_NONE (15 << 4) # define RADEON_GMC_DST_8BPP_CI (2 << 8) # define RADEON_GMC_DST_15BPP (3 << 8) # define RADEON_GMC_DST_16BPP (4 << 8) # define RADEON_GMC_DST_24BPP (5 << 8) # define RADEON_GMC_DST_32BPP (6 << 8) # define RADEON_GMC_DST_8BPP_RGB (7 << 8) # define RADEON_GMC_DST_Y8 (8 << 8) # define RADEON_GMC_DST_RGB8 (9 << 8) # define RADEON_GMC_DST_VYUY (11 << 8) # define RADEON_GMC_DST_YVYU (12 << 8) # define RADEON_GMC_DST_AYUV444 (14 << 8) # define RADEON_GMC_DST_ARGB4444 (15 << 8) # define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8) # define RADEON_GMC_DST_DATATYPE_SHIFT 8 # define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12) # define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) # define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) # define RADEON_GMC_BYTE_PIX_ORDER (1 << 14) # define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14) # define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14) # define RADEON_GMC_CONVERSION_TEMP (1 << 15) # define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15) # define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15) # define RADEON_GMC_ROP3_MASK (0xff << 16) # define RADEON_DP_SRC_SOURCE_MASK (7 << 24) # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) # define RADEON_GMC_3D_FCN_EN (1 << 27) # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) # define RADEON_GMC_AUX_CLIP_DIS (1 << 29) # define RADEON_GMC_WR_MSK_DIS (1 << 30) # define RADEON_GMC_LD_BRUSH_Y_X (1 << 31) # define RADEON_ROP3_ZERO 0x00000000 # define RADEON_ROP3_DSa 0x00880000 # define RADEON_ROP3_SDna 0x00440000 # define RADEON_ROP3_S 0x00cc0000 # define RADEON_ROP3_DSna 0x00220000 # define RADEON_ROP3_D 0x00aa0000 # define RADEON_ROP3_DSx 0x00660000 # define RADEON_ROP3_DSo 0x00ee0000 # define RADEON_ROP3_DSon 0x00110000 # define RADEON_ROP3_DSxn 0x00990000 # define RADEON_ROP3_Dn 0x00550000 # define RADEON_ROP3_SDno 0x00dd0000 # define RADEON_ROP3_Sn 0x00330000 # define RADEON_ROP3_DSno 0x00bb0000 # define RADEON_ROP3_DSan 0x00770000 # define RADEON_ROP3_ONE 0x00ff0000 # define RADEON_ROP3_DPa 0x00a00000 # define RADEON_ROP3_PDna 0x00500000 # define RADEON_ROP3_P 0x00f00000 # define RADEON_ROP3_DPna 0x000a0000 # define RADEON_ROP3_D 0x00aa0000 # define RADEON_ROP3_DPx 0x005a0000 # define RADEON_ROP3_DPo 0x00fa0000 # define RADEON_ROP3_DPon 0x00050000 # define RADEON_ROP3_PDxn 0x00a50000 # define RADEON_ROP3_PDno 0x00f50000 # define RADEON_ROP3_Pn 0x000f0000 # define RADEON_ROP3_DPno 0x00af0000 # define RADEON_ROP3_DPan 0x005f0000 #define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84 #define RADEON_DP_MIX 0x16c8 #define RADEON_DP_SRC_BKGD_CLR 0x15dc #define RADEON_DP_SRC_FRGD_CLR 0x15d8 #define RADEON_DP_WRITE_MASK 0x16cc #define RADEON_DST_BRES_DEC 0x1630 #define RADEON_DST_BRES_ERR 0x1628 #define RADEON_DST_BRES_INC 0x162c #define RADEON_DST_BRES_LNTH 0x1634 #define RADEON_DST_BRES_LNTH_SUB 0x1638 #define RADEON_DST_HEIGHT 0x1410 #define RADEON_DST_HEIGHT_WIDTH 0x143c #define RADEON_DST_HEIGHT_WIDTH_8 0x158c #define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4 #define RADEON_DST_HEIGHT_Y 0x15a0 #define RADEON_DST_LINE_START 0x1600 #define RADEON_DST_LINE_END 0x1604 #define RADEON_DST_LINE_PATCOUNT 0x1608 #define RADEON_DST_OFFSET 0x1404 #define RADEON_DST_PITCH 0x1408 #define RADEON_DST_PITCH_OFFSET 0x142c #define RADEON_DST_PITCH_OFFSET_C 0x1c80 # define RADEON_PITCH_SHIFT 21 # define RADEON_DST_TILE_LINEAR (0 << 30) # define RADEON_DST_TILE_MACRO (1 << 30) # define RADEON_DST_TILE_MICRO (2 << 30) # define RADEON_DST_TILE_BOTH (3 << 30) #define RADEON_DST_WIDTH 0x140c #define RADEON_DST_WIDTH_HEIGHT 0x1598 #define RADEON_DST_WIDTH_X 0x1588 #define RADEON_DST_WIDTH_X_INCY 0x159c #define RADEON_DST_X 0x141c #define RADEON_DST_X_SUB 0x15a4 #define RADEON_DST_X_Y 0x1594 #define RADEON_DST_Y 0x1420 #define RADEON_DST_Y_SUB 0x15a8 #define RADEON_DST_Y_X 0x1438 #define RADEON_FCP_CNTL 0x0910 # define RADEON_FCP0_SRC_PCICLK 0 # define RADEON_FCP0_SRC_PCLK 1 # define RADEON_FCP0_SRC_PCLKb 2 # define RADEON_FCP0_SRC_HREF 3 # define RADEON_FCP0_SRC_GND 4 # define RADEON_FCP0_SRC_HREFb 5 #define RADEON_FLUSH_1 0x1704 #define RADEON_FLUSH_2 0x1708 #define RADEON_FLUSH_3 0x170c #define RADEON_FLUSH_4 0x1710 #define RADEON_FLUSH_5 0x1714 #define RADEON_FLUSH_6 0x1718 #define RADEON_FLUSH_7 0x171c #define RADEON_FOG_3D_TABLE_START 0x1810 #define RADEON_FOG_3D_TABLE_END 0x1814 #define RADEON_FOG_3D_TABLE_DENSITY 0x181c #define RADEON_FOG_TABLE_INDEX 0x1a14 #define RADEON_FOG_TABLE_DATA 0x1a18 #define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250 #define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254 # define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff # define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000 # define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff # define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000 # define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 # define RADEON_FP_H_SYNC_WID_MASK 0x003f0000 # define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff # define RADEON_FP_V_SYNC_WID_MASK 0x001f0000 # define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000 # define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010 # define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000 # define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010 # define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 # define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010 # define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000 # define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010 #define RADEON_FP_GEN_CNTL 0x0284 # define RADEON_FP_FPON (1 << 0) # define RADEON_FP_BLANK_EN (1 << 1) # define RADEON_FP_TMDS_EN (1 << 2) # define RADEON_FP_PANEL_FORMAT (1 << 3) # define RADEON_FP_EN_TMDS (1 << 7) # define RADEON_FP_DETECT_SENSE (1 << 8) # define R200_FP_SOURCE_SEL_MASK (3 << 10) # define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) # define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) # define R200_FP_SOURCE_SEL_RMX (2 << 10) # define R200_FP_SOURCE_SEL_TRANS (3 << 10) # define RADEON_FP_SEL_CRTC1 (0 << 13) # define RADEON_FP_SEL_CRTC2 (1 << 13) # define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) # define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) # define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) # define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18) # define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20) # define RADEON_FP_DFP_SYNC_SEL (1 << 21) # define RADEON_FP_CRTC_LOCK_8DOT (1 << 22) # define RADEON_FP_CRT_SYNC_SEL (1 << 23) # define RADEON_FP_USE_SHADOW_EN (1 << 24) # define RADEON_FP_CRT_SYNC_ALT (1 << 26) #define RADEON_FP2_GEN_CNTL 0x0288 # define RADEON_FP2_BLANK_EN (1 << 1) # define RADEON_FP2_ON (1 << 2) # define RADEON_FP2_PANEL_FORMAT (1 << 3) # define RADEON_FP2_DETECT_SENSE (1 << 8) # define R200_FP2_SOURCE_SEL_MASK (3 << 10) # define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) # define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) # define R200_FP2_SOURCE_SEL_RMX (2 << 10) # define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10) # define RADEON_FP2_SRC_SEL_MASK (3 << 13) # define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13) # define RADEON_FP2_FP_POL (1 << 16) # define RADEON_FP2_LP_POL (1 << 17) # define RADEON_FP2_SCK_POL (1 << 18) # define RADEON_FP2_LCD_CNTL_MASK (7 << 19) # define RADEON_FP2_PAD_FLOP_EN (1 << 22) # define RADEON_FP2_CRC_EN (1 << 23) # define RADEON_FP2_CRC_READ_EN (1 << 24) # define RADEON_FP2_DVO_EN (1 << 25) # define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26) # define R200_FP2_DVO_RATE_SEL_SDR (1 << 27) # define R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28) # define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29) #define RADEON_FP_H_SYNC_STRT_WID 0x02c4 #define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 #define RADEON_FP_HORZ_STRETCH 0x028c #define RADEON_FP_HORZ2_STRETCH 0x038c # define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff # define RADEON_HORZ_STRETCH_RATIO_MAX 4096 # define RADEON_HORZ_PANEL_SIZE (0x1ff << 16) # define RADEON_HORZ_PANEL_SHIFT 16 # define RADEON_HORZ_STRETCH_PIXREP (0 << 25) # define RADEON_HORZ_STRETCH_BLEND (1 << 26) # define RADEON_HORZ_STRETCH_ENABLE (1 << 25) # define RADEON_HORZ_AUTO_RATIO (1 << 27) # define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28) # define RADEON_HORZ_AUTO_RATIO_INC (1 << 31) #define RADEON_FP_HORZ_VERT_ACTIVE 0x0278 #define RADEON_FP_V_SYNC_STRT_WID 0x02c8 #define RADEON_FP_VERT_STRETCH 0x0290 #define RADEON_FP_V2_SYNC_STRT_WID 0x03c8 #define RADEON_FP_VERT2_STRETCH 0x0390 # define RADEON_VERT_PANEL_SIZE (0xfff << 12) # define RADEON_VERT_PANEL_SHIFT 12 # define RADEON_VERT_STRETCH_RATIO_MASK 0xfff # define RADEON_VERT_STRETCH_RATIO_SHIFT 0 # define RADEON_VERT_STRETCH_RATIO_MAX 4096 # define RADEON_VERT_STRETCH_ENABLE (1 << 25) # define RADEON_VERT_STRETCH_LINEREP (0 << 26) # define RADEON_VERT_STRETCH_BLEND (1 << 26) # define RADEON_VERT_AUTO_RATIO_EN (1 << 27) # define RADEON_VERT_STRETCH_RESERVED 0xf1000000 #define RADEON_GEN_INT_CNTL 0x0040 #define RADEON_GEN_INT_STATUS 0x0044 # define RADEON_VSYNC_INT_AK (1 << 2) # define RADEON_VSYNC_INT (1 << 2) # define RADEON_VSYNC2_INT_AK (1 << 6) # define RADEON_VSYNC2_INT (1 << 6) #define RADEON_GENENB 0x03c3 /* VGA */ #define RADEON_GENFC_RD 0x03ca /* VGA */ #define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */ #define RADEON_GENMO_RD 0x03cc /* VGA */ #define RADEON_GENMO_WT 0x03c2 /* VGA */ #define RADEON_GENS0 0x03c2 /* VGA */ #define RADEON_GENS1 0x03da /* VGA, 0x03ba */ /*DDC interface using I2C*/ #define RADEON_GPIO_MONID 0x0068 #define RADEON_GPIO_MONIDB 0x006c #define RADEON_GPIO_CRT2_DDC 0x006c #define RADEON_GPIO_DVI_DDC 0x0064 #define RADEON_GPIO_VGA_DDC 0x0060 # define RADEON_GPIO_A_0 (1 << 0) # define RADEON_GPIO_A_1 (1 << 1) # define RADEON_GPIO_Y_0 (1 << 8) # define RADEON_GPIO_Y_1 (1 << 9) # define RADEON_GPIO_Y_SHIFT_0 8 # define RADEON_GPIO_Y_SHIFT_1 9 # define RADEON_GPIO_EN_0 (1 << 16) # define RADEON_GPIO_EN_1 (1 << 17) # define RADEON_GPIO_MASK_0 (1 << 24) /*??*/ # define RADEON_GPIO_MASK_1 (1 << 25) /*??*/ #define RADEON_GRPH8_DATA 0x03cf /* VGA */ #define RADEON_GRPH8_IDX 0x03ce /* VGA */ #define RADEON_GUI_DEBUG0 0x16a0 #define RADEON_GUI_DEBUG1 0x16a4 #define RADEON_GUI_DEBUG2 0x16a8 #define RADEON_GUI_DEBUG3 0x16ac #define RADEON_GUI_DEBUG4 0x16b0 #define RADEON_GUI_DEBUG5 0x16b4 #define RADEON_GUI_DEBUG6 0x16b8 #define RADEON_GUI_SCRATCH_REG0 0x15e0 #define RADEON_GUI_SCRATCH_REG1 0x15e4 #define RADEON_GUI_SCRATCH_REG2 0x15e8 #define RADEON_GUI_SCRATCH_REG3 0x15ec #define RADEON_GUI_SCRATCH_REG4 0x15f0 #define RADEON_GUI_SCRATCH_REG5 0x15f4 #define RADEON_HEADER 0x0f0e /* PCI */ #define RADEON_HOST_DATA0 0x17c0 #define RADEON_HOST_DATA1 0x17c4 #define RADEON_HOST_DATA2 0x17c8 #define RADEON_HOST_DATA3 0x17cc #define RADEON_HOST_DATA4 0x17d0 #define RADEON_HOST_DATA5 0x17d4 #define RADEON_HOST_DATA6 0x17d8 #define RADEON_HOST_DATA7 0x17dc #define RADEON_HOST_DATA_LAST 0x17e0 #define RADEON_HOST_PATH_CNTL 0x0130 # define RADEON_HDP_SOFT_RESET (1 << 26) # define RADEON_HDP_APER_CNTL (1 << 23) #define RADEON_HTOTAL_CNTL 0x0009 /* PLL */ # define RADEON_HTOT_CNTL_VGA_EN (1 << 28) #define RADEON_HTOTAL2_CNTL 0x002e /* PLL */ #define RADEON_HW_DEBUG 0x0128 #define RADEON_HW_DEBUG2 0x011c #define RADEON_I2C_CNTL_1 0x0094 /* ? */ #define RADEON_DVI_I2C_CNTL_1 0x02e4 /* ? */ #define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */ #define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */ #define RADEON_IO_BASE 0x0f14 /* PCI */ #define RADEON_LATENCY 0x0f0d /* PCI */ #define RADEON_LEAD_BRES_DEC 0x1608 #define RADEON_LEAD_BRES_LNTH 0x161c #define RADEON_LEAD_BRES_LNTH_SUB 0x1624 #define RADEON_LVDS_GEN_CNTL 0x02d0 # define RADEON_LVDS_ON (1 << 0) # define RADEON_LVDS_DISPLAY_DIS (1 << 1) # define RADEON_LVDS_PANEL_TYPE (1 << 2) # define RADEON_LVDS_PANEL_FORMAT (1 << 3) # define RADEON_LVDS_EN (1 << 7) # define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8 # define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8) # define RADEON_LVDS_BL_MOD_EN (1 << 16) # define RADEON_LVDS_DIGON (1 << 18) # define RADEON_LVDS_BLON (1 << 19) # define RADEON_LVDS_SEL_CRTC2 (1 << 23) #define RADEON_LVDS_PLL_CNTL 0x02d4 # define RADEON_HSYNC_DELAY_SHIFT 28 # define RADEON_HSYNC_DELAY_MASK (0xf << 28) # define RADEON_LVDS_PLL_EN (1 << 16) # define RADEON_LVDS_PLL_RESET (1 << 17) # define R300_LVDS_SRC_SEL_MASK (3 << 18) # define R300_LVDS_SRC_SEL_CRTC1 (0 << 18) # define R300_LVDS_SRC_SEL_CRTC2 (1 << 18) # define R300_LVDS_SRC_SEL_RMX (2 << 18) #define RADEON_MAX_LATENCY 0x0f3f /* PCI */ #define RADEON_MC_AGP_LOCATION 0x014c #define RADEON_MC_FB_LOCATION 0x0148 #define RADEON_DISPLAY_BASE_ADDR 0x23c #define RADEON_DISPLAY2_BASE_ADDR 0x33c #define RADEON_OV0_BASE_ADDR 0x43c #define RADEON_NB_TOM 0x15c #define R300_MC_INIT_MISC_LAT_TIMER 0x180 #define RADEON_MC_STATUS 0x0150 # define RADEON_MC_IDLE (1 << 2) #define RADEON_MCLK_CNTL 0x0012 /* PLL */ # define RADEON_FORCEON_MCLKA (1 << 16) # define RADEON_FORCEON_MCLKB (1 << 17) # define RADEON_FORCEON_YCLKA (1 << 18) # define RADEON_FORCEON_YCLKB (1 << 19) # define RADEON_FORCEON_MC (1 << 20) # define RADEON_FORCEON_AIC (1 << 21) #define RADEON_SCLK_CNTL 0x000d /* PLL */ # define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 # define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 # define RADEON_SCLK_FORCEON_MASK 0xffff8000 #define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */ # define RADEON_SCLK_MORE_FORCEON 0x0700 #define RADEON_MDGPIO_A_REG 0x01ac #define RADEON_MDGPIO_EN_REG 0x01b0 #define RADEON_MDGPIO_MASK 0x0198 #define RADEON_GPIOPAD_A 0x019c #define RADEON_MDGPIO_Y_REG 0x01b4 #define RADEON_MEM_ADDR_CONFIG 0x0148 #define RADEON_MEM_BASE 0x0f10 /* PCI */ #define RADEON_MEM_CNTL 0x0140 # define RADEON_MEM_NUM_CHANNELS_MASK 0x01 # define RADEON_MEM_USE_B_CH_ONLY (1 << 1) # define RV100_HALF_MODE (1 << 3) # define R300_MEM_NUM_CHANNELS_MASK 0x03 # define R300_MEM_USE_CD_CH_ONLY (1 << 2) #define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ #define RADEON_MEM_INIT_LAT_TIMER 0x0154 #define RADEON_MEM_INTF_CNTL 0x014c #define RADEON_MEM_SDRAM_MODE_REG 0x0158 # define RADEON_SDRAM_MODE_MASK 0xffff0000 # define RADEON_B3MEM_RESET_MASK 0x6fffffff #define RADEON_MEM_STR_CNTL 0x0150 # define RADEON_MEM_PWRUP_COMPL_A (1 << 0) # define RADEON_MEM_PWRUP_COMPL_B (1 << 1) # define R300_MEM_PWRUP_COMPL_C (1 << 2) # define R300_MEM_PWRUP_COMPL_D (1 << 3) # define RADEON_MEM_PWRUP_COMPLETE 0x03 # define R300_MEM_PWRUP_COMPLETE 0x0f #define RADEON_MC_STATUS 0x0150 # define RADEON_MC_IDLE (1 << 2) # define R300_MC_IDLE (1 << 4) #define RADEON_MEM_VGA_RP_SEL 0x003c #define RADEON_MEM_VGA_WP_SEL 0x0038 #define RADEON_MIN_GRANT 0x0f3e /* PCI */ #define RADEON_MM_DATA 0x0004 #define RADEON_MM_INDEX 0x0000 #define RADEON_MPLL_CNTL 0x000e /* PLL */ #define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ #define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ #define R300_MC_IND_INDEX 0x01f8 # define R300_MC_IND_ADDR_MASK 0x3f # define R300_MC_IND_WR_EN (1 << 8) #define R300_MC_IND_DATA 0x01fc #define RADEON_MC_CNTL 0x0178 #define R300_MC_READ_CNTL_AB 0x017c # define R300_MEM_RBS_POSITION_A_MASK 0x03 #define R300_MC_READ_CNTL_CD_mcind 0x24 # define R300_MEM_RBS_POSITION_C_MASK 0x03 #define RADEON_N_VIF_COUNT 0x0248 #define RADEON_OV0_AUTO_FLIP_CNTL 0x0470 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 # define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 # define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 # define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 # define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 # define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 # define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 #define RADEON_OV0_COLOUR_CNTL 0x04E0 #define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 #define RADEON_OV0_EXCLUSIVE_HORZ 0x0408 # define RADEON_EXCL_HORZ_START_MASK 0x000000ff # define RADEON_EXCL_HORZ_END_MASK 0x0000ff00 # define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 # define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 #define RADEON_OV0_EXCLUSIVE_VERT 0x040C # define RADEON_EXCL_VERT_START_MASK 0x000003ff # define RADEON_EXCL_VERT_END_MASK 0x03ff0000 #define RADEON_OV0_FILTER_CNTL 0x04A0 # define RADEON_FILTER_PROGRAMMABLE_COEF 0x0 # define RADEON_FILTER_HC_COEF_HORZ_Y 0x1 # define RADEON_FILTER_HC_COEF_HORZ_UV 0x2 # define RADEON_FILTER_HC_COEF_VERT_Y 0x4 # define RADEON_FILTER_HC_COEF_VERT_UV 0x8 # define RADEON_FILTER_HARDCODED_COEF 0xf # define RADEON_FILTER_COEF_MASK 0xf #define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 #define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 #define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 #define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC #define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 #define RADEON_OV0_FLAG_CNTL 0x04DC #define RADEON_OV0_GAMMA_000_00F 0x0d40 #define RADEON_OV0_GAMMA_010_01F 0x0d44 #define RADEON_OV0_GAMMA_020_03F 0x0d48 #define RADEON_OV0_GAMMA_040_07F 0x0d4c #define RADEON_OV0_GAMMA_080_0BF 0x0e00 #define RADEON_OV0_GAMMA_0C0_0FF 0x0e04 #define RADEON_OV0_GAMMA_100_13F 0x0e08 #define RADEON_OV0_GAMMA_140_17F 0x0e0c #define RADEON_OV0_GAMMA_180_1BF 0x0e10 #define RADEON_OV0_GAMMA_1C0_1FF 0x0e14 #define RADEON_OV0_GAMMA_200_23F 0x0e18 #define RADEON_OV0_GAMMA_240_27F 0x0e1c #define RADEON_OV0_GAMMA_280_2BF 0x0e20 #define RADEON_OV0_GAMMA_2C0_2FF 0x0e24 #define RADEON_OV0_GAMMA_300_33F 0x0e28 #define RADEON_OV0_GAMMA_340_37F 0x0e2c #define RADEON_OV0_GAMMA_380_3BF 0x0d50 #define RADEON_OV0_GAMMA_3C0_3FF 0x0d54 #define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC #define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 #define RADEON_OV0_H_INC 0x0480 #define RADEON_OV0_KEY_CNTL 0x04F4 # define RADEON_VIDEO_KEY_FN_MASK 0x00000003L # define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L # define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L # define RADEON_VIDEO_KEY_FN_EQ 0x00000002L # define RADEON_VIDEO_KEY_FN_NE 0x00000003L # define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L # define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L # define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L # define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L # define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L # define RADEON_CMP_MIX_MASK 0x00000100L # define RADEON_CMP_MIX_OR 0x00000000L # define RADEON_CMP_MIX_AND 0x00000100L #define RADEON_OV0_LIN_TRANS_A 0x0d20 #define RADEON_OV0_LIN_TRANS_B 0x0d24 #define RADEON_OV0_LIN_TRANS_C 0x0d28 #define RADEON_OV0_LIN_TRANS_D 0x0d2c #define RADEON_OV0_LIN_TRANS_E 0x0d30 #define RADEON_OV0_LIN_TRANS_F 0x0d34 #define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 # define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL # define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L #define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 #define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 # define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L # define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L #define RADEON_OV0_P1_X_START_END 0x0494 #define RADEON_OV0_P2_X_START_END 0x0498 #define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 # define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL # define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L #define RADEON_OV0_P23_H_ACCUM_INIT 0x048C #define RADEON_OV0_P23_V_ACCUM_INIT 0x042C #define RADEON_OV0_P3_X_START_END 0x049C #define RADEON_OV0_REG_LOAD_CNTL 0x0410 # define RADEON_REG_LD_CTL_LOCK 0x00000001L # define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L # define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L # define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L #define RADEON_OV0_SCALE_CNTL 0x0420 # define RADEON_SCALER_PIX_EXPAND 0x00000001L # define RADEON_SCALER_Y2R_TEMP 0x00000002L # define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000003L # define RADEON_SCALER_VERT_PICK_NEAREST 0x00000004L # define RADEON_SCALER_SIGNED_UV 0x00000010L # define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L # define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L # define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L # define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L # define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L # define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L # define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L # define RADEON_SCALER_SOURCE_15BPP 0x00000300L # define RADEON_SCALER_SOURCE_16BPP 0x00000400L # define RADEON_SCALER_SOURCE_32BPP 0x00000600L # define RADEON_SCALER_SOURCE_YUV9 0x00000900L # define RADEON_SCALER_SOURCE_YUV12 0x00000A00L # define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L # define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L # define RADEON_SCALER_SMART_SWITCH 0x00008000L # define RADEON_SCALER_BURST_PER_PLANE 0x00ff0000L # define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L # define RADEON_SCALER_DIS_LIMIT 0x08000000L # define RADEON_SCALER_PRG_LOAD_START 0x10000000L # define RADEON_SCALER_INT_EMU 0x20000000L # define RADEON_SCALER_ENABLE 0x40000000L # define RADEON_SCALER_SOFT_RESET 0x80000000L #define RADEON_OV0_STEP_BY 0x0484 #define RADEON_OV0_TEST 0x04F8 #define RADEON_OV0_V_INC 0x0424 #define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 #define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 #define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 # define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L # define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L # define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L # define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L #define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 # define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L # define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L # define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L # define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L #define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 # define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L # define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L # define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L # define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L #define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C #define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 #define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 #define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8 #define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4 #define RADEON_OV0_Y_X_START 0x0400 #define RADEON_OV0_Y_X_END 0x0404 #define RADEON_OV1_Y_X_START 0x0600 #define RADEON_OV1_Y_X_END 0x0604 #define RADEON_OVR_CLR 0x0230 #define RADEON_OVR_WID_LEFT_RIGHT 0x0234 #define RADEON_OVR_WID_TOP_BOTTOM 0x0238 /* first capture unit */ #define RADEON_CAP0_BUF0_OFFSET 0x0920 #define RADEON_CAP0_BUF1_OFFSET 0x0924 #define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928 #define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C #define RADEON_CAP0_BUF_PITCH 0x0930 #define RADEON_CAP0_V_WINDOW 0x0934 #define RADEON_CAP0_H_WINDOW 0x0938 #define RADEON_CAP0_VBI0_OFFSET 0x093C #define RADEON_CAP0_VBI1_OFFSET 0x0940 #define RADEON_CAP0_VBI_V_WINDOW 0x0944 #define RADEON_CAP0_VBI_H_WINDOW 0x0948 #define RADEON_CAP0_PORT_MODE_CNTL 0x094C #define RADEON_CAP0_TRIG_CNTL 0x0950 #define RADEON_CAP0_DEBUG 0x0954 #define RADEON_CAP0_CONFIG 0x0958 # define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001 # define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002 # define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004 # define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008 # define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 # define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 # define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 # define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 # define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 # define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200 # define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 # define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 # define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000 # define RADEON_CAP0_CONFIG_VBI_EN 0x00002000 # define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 # define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 # define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 # define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 # define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 # define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 # define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 # define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 # define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 # define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 # define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000 # define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000 # define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000 # define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 # define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 # define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 # define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 # define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 # define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 #define RADEON_CAP0_ANC_ODD_OFFSET 0x095C #define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960 #define RADEON_CAP0_ANC_H_WINDOW 0x0964 #define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968 #define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C #define RADEON_CAP0_BUF_STATUS 0x0970 /* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */ /* #define RADEON_CAP0_XSHARPNESS 0x097C */ #define RADEON_CAP0_VBI2_OFFSET 0x0980 #define RADEON_CAP0_VBI3_OFFSET 0x0984 #define RADEON_CAP0_ANC2_OFFSET 0x0988 #define RADEON_CAP0_ANC3_OFFSET 0x098C #define RADEON_VID_BUFFER_CONTROL 0x0900 /* second capture unit */ #define RADEON_CAP1_BUF0_OFFSET 0x0990 #define RADEON_CAP1_BUF1_OFFSET 0x0994 #define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998 #define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C #define RADEON_CAP1_BUF_PITCH 0x09A0 #define RADEON_CAP1_V_WINDOW 0x09A4 #define RADEON_CAP1_H_WINDOW 0x09A8 #define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC #define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0 #define RADEON_CAP1_VBI_V_WINDOW 0x09B4 #define RADEON_CAP1_VBI_H_WINDOW 0x09B8 #define RADEON_CAP1_PORT_MODE_CNTL 0x09BC #define RADEON_CAP1_TRIG_CNTL 0x09C0 #define RADEON_CAP1_DEBUG 0x09C4 #define RADEON_CAP1_CONFIG 0x09C8 #define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC #define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0 #define RADEON_CAP1_ANC_H_WINDOW 0x09D4 #define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8 #define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC #define RADEON_CAP1_BUF_STATUS 0x09E0 #define RADEON_CAP1_DWNSC_XRATIO 0x09E8 #define RADEON_CAP1_XSHARPNESS 0x09EC /* misc multimedia registers */ #define RADEON_IDCT_RUNS 0x1F80 #define RADEON_IDCT_LEVELS 0x1F84 #define RADEON_IDCT_CONTROL 0x1FBC #define RADEON_IDCT_AUTH_CONTROL 0x1F88 #define RADEON_IDCT_AUTH 0x1F8C #define RADEON_P2PLL_CNTL 0x002a /* P2PLL */ # define RADEON_P2PLL_RESET (1 << 0) # define RADEON_P2PLL_SLEEP (1 << 1) # define RADEON_P2PLL_PVG_MASK (7 << 11) # define RADEON_P2PLL_PVG_SHIFT 11 # define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16) # define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) # define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) #define RADEON_P2PLL_DIV_0 0x002c # define RADEON_P2PLL_FB0_DIV_MASK 0x07ff # define RADEON_P2PLL_POST0_DIV_MASK 0x00070000 #define RADEON_P2PLL_REF_DIV 0x002B /* PLL */ # define RADEON_P2PLL_REF_DIV_MASK 0x03ff # define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ # define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ # define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) # define R300_PPLL_REF_DIV_ACC_SHIFT 18 #define RADEON_PALETTE_DATA 0x00b4 #define RADEON_PALETTE_30_DATA 0x00b8 #define RADEON_PALETTE_INDEX 0x00b0 #define RADEON_PCI_GART_PAGE 0x017c #define RADEON_PIXCLKS_CNTL 0x002d # define RADEON_PIX2CLK_SRC_SEL_MASK 0x03 # define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00 # define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01 # define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02 # define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03 # define RADEON_PIX2CLK_ALWAYS_ONb (1<<6) # define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7) # define RADEON_PIXCLK_TV_SRC_SEL (1 << 8) # define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) # define R300_DVOCLK_ALWAYS_ONb (1 << 10) # define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11) # define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12) # define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13) # define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) # define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) # define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15) # define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) # define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) # define R300_P2G2CLK_ALWAYS_ONb (1 << 18) # define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) # define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) #define RADEON_PLANE_3D_MASK_C 0x1d44 #define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */ # define RADEON_PLL_MASK_READ_B (1 << 9) #define RADEON_PMI_CAP_ID 0x0f5c /* PCI */ #define RADEON_PMI_DATA 0x0f63 /* PCI */ #define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */ #define RADEON_PMI_PMC_REG 0x0f5e /* PCI */ #define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */ #define RADEON_PMI_REGISTER 0x0f5c /* PCI */ #define RADEON_PPLL_CNTL 0x0002 /* PLL */ # define RADEON_PPLL_RESET (1 << 0) # define RADEON_PPLL_SLEEP (1 << 1) # define RADEON_PPLL_PVG_MASK (7 << 11) # define RADEON_PPLL_PVG_SHIFT 11 # define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16) # define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) # define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) #define RADEON_PPLL_DIV_0 0x0004 /* PLL */ #define RADEON_PPLL_DIV_1 0x0005 /* PLL */ #define RADEON_PPLL_DIV_2 0x0006 /* PLL */ #define RADEON_PPLL_DIV_3 0x0007 /* PLL */ # define RADEON_PPLL_FB3_DIV_MASK 0x07ff # define RADEON_PPLL_POST3_DIV_MASK 0x00070000 #define RADEON_PPLL_REF_DIV 0x0003 /* PLL */ # define RADEON_PPLL_REF_DIV_MASK 0x03ff # define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ # define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ #define RADEON_P2PLL_CNTL 0x002a /* P2PLL */ # define RADEON_P2PLL_RESET (1 << 0) # define RADEON_P2PLL_SLEEP (1 << 1) # define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16) # define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) # define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) #define RADEON_P2PLL_DIV_0 0x002c # define RADEON_P2PLL_FB0_DIV_MASK 0x07ff # define RADEON_P2PLL_POST0_DIV_MASK 0x00070000 #define RADEON_P2PLL_REF_DIV 0x002B /* PLL */ # define RADEON_P2PLL_REF_DIV_MASK 0x03ff # define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ # define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ #define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ #define RADEON_RBBM_GUICNTL 0x172c # define RADEON_HOST_DATA_SWAP_NONE (0 << 0) # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) # define RADEON_HOST_DATA_SWAP_HDW (3 << 0) #define RADEON_RBBM_SOFT_RESET 0x00f0 # define RADEON_SOFT_RESET_CP (1 << 0) # define RADEON_SOFT_RESET_HI (1 << 1) # define RADEON_SOFT_RESET_SE (1 << 2) # define RADEON_SOFT_RESET_RE (1 << 3) # define RADEON_SOFT_RESET_PP (1 << 4) # define RADEON_SOFT_RESET_E2 (1 << 5) # define RADEON_SOFT_RESET_RB (1 << 6) # define RADEON_SOFT_RESET_HDP (1 << 7) #define RADEON_RBBM_STATUS 0x0e40 # define RADEON_RBBM_FIFOCNT_MASK 0x007f # define RADEON_RBBM_ACTIVE (1 << 31) #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c # define RADEON_RB2D_DC_FLUSH (3 << 0) # define RADEON_RB2D_DC_FREE (3 << 2) # define RADEON_RB2D_DC_FLUSH_ALL 0xf # define RADEON_RB2D_DC_BUSY (1 << 31) #define RADEON_RB2D_DSTCACHE_MODE 0x3428 #define RADEON_RB3D_ZCACHE_MODE 0x3250 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 #define RADEON_RB3D_DSTCACHE_MODE 0x3258 # define RADEON_RB3D_DC_CACHE_ENABLE (0) # define RADEON_RB3D_DC_2D_CACHE_DISABLE (1) # define RADEON_RB3D_DC_3D_CACHE_DISABLE (2) # define RADEON_RB3D_DC_CACHE_DISABLE (3) # define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2) # define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2) # define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8) # define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8) # define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10) # define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10) # define RADEON_RB3D_DC_FORCE_RMW (1 << 16) # define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24) # define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25) #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C # define RADEON_RB3D_DC_FLUSH (3 << 0) # define RADEON_RB3D_DC_FREE (3 << 2) # define RADEON_RB3D_DC_FLUSH_ALL 0xf # define RADEON_RB3D_DC_BUSY (1 << 31) #define RADEON_REG_BASE 0x0f18 /* PCI */ #define RADEON_REGPROG_INF 0x0f09 /* PCI */ #define RADEON_REVISION_ID 0x0f08 /* PCI */ #define RADEON_DSTCACHE_MODE 0x1710 #define RADEON_RB3D_DSTCACHE_MODE 0x3258 #define RADEON_SC_BOTTOM 0x164c #define RADEON_SC_BOTTOM_RIGHT 0x16f0 #define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c #define RADEON_SC_LEFT 0x1640 #define RADEON_SC_RIGHT 0x1644 #define RADEON_SC_TOP 0x1648 #define RADEON_SC_TOP_LEFT 0x16ec #define RADEON_SC_TOP_LEFT_C 0x1c88 # define RADEON_SC_SIGN_MASK_LO 0x8000 # define RADEON_SC_SIGN_MASK_HI 0x80000000 #define RADEON_SDRAM_MODE_REG 0x0158 #define RADEON_SEQ8_DATA 0x03c5 /* VGA */ #define RADEON_SEQ8_IDX 0x03c4 /* VGA */ #define RADEON_SNAPSHOT_F_COUNT 0x0244 #define RADEON_SNAPSHOT_VH_COUNTS 0x0240 #define RADEON_SNAPSHOT_VIF_COUNT 0x024c #define RADEON_SRC_OFFSET 0x15ac #define RADEON_SRC_PITCH 0x15b0 #define RADEON_SRC_PITCH_OFFSET 0x1428 #define RADEON_SRC_SC_BOTTOM 0x165c #define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4 #define RADEON_SRC_SC_RIGHT 0x1654 #define RADEON_SRC_X 0x1414 #define RADEON_SRC_X_Y 0x1590 #define RADEON_SRC_Y 0x1418 #define RADEON_SRC_Y_X 0x1434 #define RADEON_STATUS 0x0f06 /* PCI */ #define RADEON_SUBPIC_CNTL 0x0540 /* ? */ #define RADEON_SUB_CLASS 0x0f0a /* PCI */ #define RADEON_SURFACE_CNTL 0x0b00 # define RADEON_SURF_TRANSLATION_DIS (1 << 8) # define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) # define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) #define RADEON_SURFACE0_INFO 0x0b0c #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 #define RADEON_SURFACE1_INFO 0x0b1c #define RADEON_SURFACE1_LOWER_BOUND 0x0b14 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18 #define RADEON_SURFACE2_INFO 0x0b2c #define RADEON_SURFACE2_LOWER_BOUND 0x0b24 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28 #define RADEON_SURFACE3_INFO 0x0b3c #define RADEON_SURFACE3_LOWER_BOUND 0x0b34 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38 #define RADEON_SURFACE4_INFO 0x0b4c #define RADEON_SURFACE4_LOWER_BOUND 0x0b44 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48 #define RADEON_SURFACE5_INFO 0x0b5c #define RADEON_SURFACE5_LOWER_BOUND 0x0b54 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58 #define RADEON_SURFACE6_INFO 0x0b6c #define RADEON_SURFACE6_LOWER_BOUND 0x0b64 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68 #define RADEON_SURFACE7_INFO 0x0b7c #define RADEON_SURFACE7_LOWER_BOUND 0x0b74 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78 #define RADEON_SW_SEMAPHORE 0x013c #define RADEON_TEST_DEBUG_CNTL 0x0120 #define RADEON_TEST_DEBUG_MUX 0x0124 #define RADEON_TEST_DEBUG_OUT 0x012c #define RADEON_TMDS_CRC 0x02a0 #define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4 # define RADEON_TMDS_TRANSMITTER_PLLEN 1 # define RADEON_TMDS_TRANSMITTER_PLLRST 2 #define RADEON_TMDS_PLL_CNTL 0x02a8 #define RADEON_TRAIL_BRES_DEC 0x1614 #define RADEON_TRAIL_BRES_ERR 0x160c #define RADEON_TRAIL_BRES_INC 0x1610 #define RADEON_TRAIL_X 0x1618 #define RADEON_TRAIL_X_SUB 0x1620 #define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ # define RADEON_VCLK_SRC_SEL_MASK 0x03 # define RADEON_VCLK_SRC_SEL_CPUCLK 0x00 # define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01 # define RADEON_VCLK_SRC_SEL_BYTECLK 0x02 # define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03 #define RADEON_PIXCLKS_CNTL 0x002d # define RADEON_PIX2CLK_SRC_SEL_MASK 0x03 # define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00 # define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01 # define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02 # define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03 #define RADEON_VENDOR_ID 0x0f00 /* PCI */ #define RADEON_VGA_DDA_CONFIG 0x02e8 #define RADEON_VGA_DDA_ON_OFF 0x02ec #define RADEON_VID_BUFFER_CONTROL 0x0900 #define RADEON_VIDEOMUX_CNTL 0x0190 /* VIP bus */ #define RADEON_VIPH_CH0_DATA 0x0c00 #define RADEON_VIPH_CH1_DATA 0x0c04 #define RADEON_VIPH_CH2_DATA 0x0c08 #define RADEON_VIPH_CH3_DATA 0x0c0c #define RADEON_VIPH_CH0_ADDR 0x0c10 #define RADEON_VIPH_CH1_ADDR 0x0c14 #define RADEON_VIPH_CH2_ADDR 0x0c18 #define RADEON_VIPH_CH3_ADDR 0x0c1c #define RADEON_VIPH_CH0_SBCNT 0x0c20 #define RADEON_VIPH_CH1_SBCNT 0x0c24 #define RADEON_VIPH_CH2_SBCNT 0x0c28 #define RADEON_VIPH_CH3_SBCNT 0x0c2c #define RADEON_VIPH_CH0_ABCNT 0x0c30 #define RADEON_VIPH_CH1_ABCNT 0x0c34 #define RADEON_VIPH_CH2_ABCNT 0x0c38 #define RADEON_VIPH_CH3_ABCNT 0x0c3c #define RADEON_VIPH_CONTROL 0x0c40 # define RADEON_VIP_BUSY 0 # define RADEON_VIP_IDLE 1 # define RADEON_VIP_RESET 2 #define RADEON_VIPH_DV_LAT 0x0c44 #define RADEON_VIPH_BM_CHUNK 0x0c48 #define RADEON_VIPH_DV_INT 0x0c4c #define RADEON_VIPH_TIMEOUT_STAT 0x0c50 #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 #define RADEON_VIPH_REG_DATA 0x0084 #define RADEON_VIPH_REG_ADDR 0x0080 #define RADEON_WAIT_UNTIL 0x1720 # define RADEON_WAIT_CRTC_PFLIP (1 << 0) # define RADEON_WAIT_2D_IDLECLEAN (1 << 16) # define RADEON_WAIT_3D_IDLECLEAN (1 << 17) # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) #define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ #define RADEON_XCLK_CNTL 0x000d /* PLL */ #define RADEON_XDLL_CNTL 0x000c /* PLL */ #define RADEON_XPLL_CNTL 0x000b /* PLL */ /* Registers for 3D/TCL */ #define RADEON_PP_BORDER_COLOR_0 0x1d40 #define RADEON_PP_BORDER_COLOR_1 0x1d44 #define RADEON_PP_BORDER_COLOR_2 0x1d48 #define RADEON_PP_CNTL 0x1c38 # define RADEON_STIPPLE_ENABLE (1 << 0) # define RADEON_SCISSOR_ENABLE (1 << 1) # define RADEON_PATTERN_ENABLE (1 << 2) # define RADEON_SHADOW_ENABLE (1 << 3) # define RADEON_TEX_ENABLE_MASK (0xf << 4) # define RADEON_TEX_0_ENABLE (1 << 4) # define RADEON_TEX_1_ENABLE (1 << 5) # define RADEON_TEX_2_ENABLE (1 << 6) # define RADEON_TEX_3_ENABLE (1 << 7) # define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12) # define RADEON_TEX_BLEND_0_ENABLE (1 << 12) # define RADEON_TEX_BLEND_1_ENABLE (1 << 13) # define RADEON_TEX_BLEND_2_ENABLE (1 << 14) # define RADEON_TEX_BLEND_3_ENABLE (1 << 15) # define RADEON_PLANAR_YUV_ENABLE (1 << 20) # define RADEON_SPECULAR_ENABLE (1 << 21) # define RADEON_FOG_ENABLE (1 << 22) # define RADEON_ALPHA_TEST_ENABLE (1 << 23) # define RADEON_ANTI_ALIAS_NONE (0 << 24) # define RADEON_ANTI_ALIAS_LINE (1 << 24) # define RADEON_ANTI_ALIAS_POLY (2 << 24) # define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24) # define RADEON_BUMP_MAP_ENABLE (1 << 26) # define RADEON_BUMPED_MAP_T0 (0 << 27) # define RADEON_BUMPED_MAP_T1 (1 << 27) # define RADEON_BUMPED_MAP_T2 (2 << 27) # define RADEON_TEX_3D_ENABLE_0 (1 << 29) # define RADEON_TEX_3D_ENABLE_1 (1 << 30) # define RADEON_MC_ENABLE (1 << 31) #define RADEON_PP_FOG_COLOR 0x1c18 # define RADEON_FOG_COLOR_MASK 0x00ffffff # define RADEON_FOG_VERTEX (0 << 24) # define RADEON_FOG_TABLE (1 << 24) # define RADEON_FOG_USE_DEPTH (0 << 25) # define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25) # define RADEON_FOG_USE_SPEC_ALPHA (3 << 25) #define RADEON_PP_LUM_MATRIX 0x1d00 #define RADEON_PP_MISC 0x1c14 # define RADEON_REF_ALPHA_MASK 0x000000ff # define RADEON_ALPHA_TEST_FAIL (0 << 8) # define RADEON_ALPHA_TEST_LESS (1 << 8) # define RADEON_ALPHA_TEST_LEQUAL (2 << 8) # define RADEON_ALPHA_TEST_EQUAL (3 << 8) # define RADEON_ALPHA_TEST_GEQUAL (4 << 8) # define RADEON_ALPHA_TEST_GREATER (5 << 8) # define RADEON_ALPHA_TEST_NEQUAL (6 << 8) # define RADEON_ALPHA_TEST_PASS (7 << 8) # define RADEON_ALPHA_TEST_OP_MASK (7 << 8) # define RADEON_CHROMA_FUNC_FAIL (0 << 16) # define RADEON_CHROMA_FUNC_PASS (1 << 16) # define RADEON_CHROMA_FUNC_NEQUAL (2 << 16) # define RADEON_CHROMA_FUNC_EQUAL (3 << 16) # define RADEON_CHROMA_KEY_NEAREST (0 << 18) # define RADEON_CHROMA_KEY_ZERO (1 << 18) # define RADEON_SHADOW_ID_AUTO_INC (1 << 20) # define RADEON_SHADOW_FUNC_EQUAL (0 << 21) # define RADEON_SHADOW_FUNC_NEQUAL (1 << 21) # define RADEON_SHADOW_PASS_1 (0 << 22) # define RADEON_SHADOW_PASS_2 (1 << 22) # define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24) # define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24) #define RADEON_PP_ROT_MATRIX_0 0x1d58 #define RADEON_PP_ROT_MATRIX_1 0x1d5c #define RADEON_PP_TXFILTER_0 0x1c54 #define RADEON_PP_TXFILTER_1 0x1c6c #define RADEON_PP_TXFILTER_2 0x1c84 # define RADEON_MAG_FILTER_NEAREST (0 << 0) # define RADEON_MAG_FILTER_LINEAR (1 << 0) # define RADEON_MAG_FILTER_MASK (1 << 0) # define RADEON_MIN_FILTER_NEAREST (0 << 1) # define RADEON_MIN_FILTER_LINEAR (1 << 1) # define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) # define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) # define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) # define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) # define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1) # define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1) # define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) # define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) # define RADEON_MIN_FILTER_MASK (15 << 1) # define RADEON_MAX_ANISO_1_TO_1 (0 << 5) # define RADEON_MAX_ANISO_2_TO_1 (1 << 5) # define RADEON_MAX_ANISO_4_TO_1 (2 << 5) # define RADEON_MAX_ANISO_8_TO_1 (3 << 5) # define RADEON_MAX_ANISO_16_TO_1 (4 << 5) # define RADEON_MAX_ANISO_MASK (7 << 5) # define RADEON_LOD_BIAS_MASK (0xff << 8) # define RADEON_LOD_BIAS_SHIFT 8 # define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16) # define RADEON_MAX_MIP_LEVEL_SHIFT 16 # define RADEON_YUV_TO_RGB (1 << 20) # define RADEON_YUV_TEMPERATURE_COOL (0 << 21) # define RADEON_YUV_TEMPERATURE_HOT (1 << 21) # define RADEON_YUV_TEMPERATURE_MASK (1 << 21) # define RADEON_WRAPEN_S (1 << 22) # define RADEON_CLAMP_S_WRAP (0 << 23) # define RADEON_CLAMP_S_MIRROR (1 << 23) # define RADEON_CLAMP_S_CLAMP_LAST (2 << 23) # define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) # define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23) # define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) # define RADEON_CLAMP_S_CLAMP_GL (6 << 23) # define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) # define RADEON_CLAMP_S_MASK (7 << 23) # define RADEON_WRAPEN_T (1 << 26) # define RADEON_CLAMP_T_WRAP (0 << 27) # define RADEON_CLAMP_T_MIRROR (1 << 27) # define RADEON_CLAMP_T_CLAMP_LAST (2 << 27) # define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) # define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27) # define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) # define RADEON_CLAMP_T_CLAMP_GL (6 << 27) # define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) # define RADEON_CLAMP_T_MASK (7 << 27) # define RADEON_BORDER_MODE_OGL (0 << 31) # define RADEON_BORDER_MODE_D3D (1 << 31) #define RADEON_PP_TXFORMAT_0 0x1c58 #define RADEON_PP_TXFORMAT_1 0x1c70 #define RADEON_PP_TXFORMAT_2 0x1c88 # define RADEON_TXFORMAT_I8 (0 << 0) # define RADEON_TXFORMAT_AI88 (1 << 0) # define RADEON_TXFORMAT_RGB332 (2 << 0) # define RADEON_TXFORMAT_ARGB1555 (3 << 0) # define RADEON_TXFORMAT_RGB565 (4 << 0) # define RADEON_TXFORMAT_ARGB4444 (5 << 0) # define RADEON_TXFORMAT_ARGB8888 (6 << 0) # define RADEON_TXFORMAT_RGBA8888 (7 << 0) # define RADEON_TXFORMAT_Y8 (8 << 0) # define RADEON_TXFORMAT_VYUY422 (10 << 0) # define RADEON_TXFORMAT_YVYU422 (11 << 0) # define RADEON_TXFORMAT_DXT1 (12 << 0) # define RADEON_TXFORMAT_DXT23 (14 << 0) # define RADEON_TXFORMAT_DXT45 (15 << 0) # define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) # define RADEON_TXFORMAT_FORMAT_SHIFT 0 # define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) # define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6) # define RADEON_TXFORMAT_NON_POWER2 (1 << 7) # define RADEON_TXFORMAT_WIDTH_MASK (15 << 8) # define RADEON_TXFORMAT_WIDTH_SHIFT 8 # define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12) # define RADEON_TXFORMAT_HEIGHT_SHIFT 12 # define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16) # define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16 # define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20) # define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20 # define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) # define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24) # define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) # define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) # define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26) # define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) # define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) # define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) # define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) # define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) # define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) # define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) #define RADEON_PP_CUBIC_FACES_0 0x1d24 #define RADEON_PP_CUBIC_FACES_1 0x1d28 #define RADEON_PP_CUBIC_FACES_2 0x1d2c # define RADEON_FACE_WIDTH_1_SHIFT 0 # define RADEON_FACE_HEIGHT_1_SHIFT 4 # define RADEON_FACE_WIDTH_1_MASK (0xf << 0) # define RADEON_FACE_HEIGHT_1_MASK (0xf << 4) # define RADEON_FACE_WIDTH_2_SHIFT 8 # define RADEON_FACE_HEIGHT_2_SHIFT 12 # define RADEON_FACE_WIDTH_2_MASK (0xf << 8) # define RADEON_FACE_HEIGHT_2_MASK (0xf << 12) # define RADEON_FACE_WIDTH_3_SHIFT 16 # define RADEON_FACE_HEIGHT_3_SHIFT 20 # define RADEON_FACE_WIDTH_3_MASK (0xf << 16) # define RADEON_FACE_HEIGHT_3_MASK (0xf << 20) # define RADEON_FACE_WIDTH_4_SHIFT 24 # define RADEON_FACE_HEIGHT_4_SHIFT 28 # define RADEON_FACE_WIDTH_4_MASK (0xf << 24) # define RADEON_FACE_HEIGHT_4_MASK (0xf << 28) #define RADEON_PP_TXOFFSET_0 0x1c5c #define RADEON_PP_TXOFFSET_1 0x1c74 #define RADEON_PP_TXOFFSET_2 0x1c8c # define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0) # define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0) # define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0) # define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0) # define RADEON_TXO_MACRO_LINEAR (0 << 2) # define RADEON_TXO_MACRO_TILE (1 << 2) # define RADEON_TXO_MICRO_LINEAR (0 << 3) # define RADEON_TXO_MICRO_TILE_X2 (1 << 3) # define RADEON_TXO_MICRO_TILE_OPT (2 << 3) # define RADEON_TXO_OFFSET_MASK 0xffffffe0 # define RADEON_TXO_OFFSET_SHIFT 5 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ #define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4 #define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8 #define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc #define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 #define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04 #define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08 #define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c #define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 #define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18 #define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c #define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20 #define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ #define RADEON_PP_TEX_SIZE_1 0x1d0c #define RADEON_PP_TEX_SIZE_2 0x1d14 # define RADEON_TEX_USIZE_MASK (0x7ff << 0) # define RADEON_TEX_USIZE_SHIFT 0 # define RADEON_TEX_VSIZE_MASK (0x7ff << 16) # define RADEON_TEX_VSIZE_SHIFT 16 # define RADEON_SIGNED_RGB_MASK (1 << 30) # define RADEON_SIGNED_RGB_SHIFT 30 # define RADEON_SIGNED_ALPHA_MASK (1 << 31) # define RADEON_SIGNED_ALPHA_SHIFT 31 #define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */ #define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */ #define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */ /* note: bits 13-5: 32 byte aligned stride of texture map */ #define RADEON_PP_TXCBLEND_0 0x1c60 #define RADEON_PP_TXCBLEND_1 0x1c78 #define RADEON_PP_TXCBLEND_2 0x1c90 # define RADEON_COLOR_ARG_A_SHIFT 0 # define RADEON_COLOR_ARG_A_MASK (0x1f << 0) # define RADEON_COLOR_ARG_A_ZERO (0 << 0) # define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0) # define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0) # define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) # define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) # define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0) # define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) # define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0) # define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) # define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0) # define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0) # define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0) # define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0) # define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0) # define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0) # define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0) # define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0) # define RADEON_COLOR_ARG_B_SHIFT 5 # define RADEON_COLOR_ARG_B_MASK (0x1f << 5) # define RADEON_COLOR_ARG_B_ZERO (0 << 5) # define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5) # define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5) # define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) # define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) # define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5) # define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) # define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5) # define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) # define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5) # define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5) # define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5) # define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5) # define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5) # define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5) # define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5) # define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5) # define RADEON_COLOR_ARG_C_SHIFT 10 # define RADEON_COLOR_ARG_C_MASK (0x1f << 10) # define RADEON_COLOR_ARG_C_ZERO (0 << 10) # define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10) # define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10) # define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) # define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) # define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10) # define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) # define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10) # define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) # define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10) # define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10) # define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10) # define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10) # define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10) # define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10) # define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10) # define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10) # define RADEON_COMP_ARG_A (1 << 15) # define RADEON_COMP_ARG_A_SHIFT 15 # define RADEON_COMP_ARG_B (1 << 16) # define RADEON_COMP_ARG_B_SHIFT 16 # define RADEON_COMP_ARG_C (1 << 17) # define RADEON_COMP_ARG_C_SHIFT 17 # define RADEON_BLEND_CTL_MASK (7 << 18) # define RADEON_BLEND_CTL_ADD (0 << 18) # define RADEON_BLEND_CTL_SUBTRACT (1 << 18) # define RADEON_BLEND_CTL_ADDSIGNED (2 << 18) # define RADEON_BLEND_CTL_BLEND (3 << 18) # define RADEON_BLEND_CTL_DOT3 (4 << 18) # define RADEON_SCALE_SHIFT 21 # define RADEON_SCALE_MASK (3 << 21) # define RADEON_SCALE_1X (0 << 21) # define RADEON_SCALE_2X (1 << 21) # define RADEON_SCALE_4X (2 << 21) # define RADEON_CLAMP_TX (1 << 23) # define RADEON_T0_EQ_TCUR (1 << 24) # define RADEON_T1_EQ_TCUR (1 << 25) # define RADEON_T2_EQ_TCUR (1 << 26) # define RADEON_T3_EQ_TCUR (1 << 27) # define RADEON_COLOR_ARG_MASK 0x1f # define RADEON_COMP_ARG_SHIFT 15 #define RADEON_PP_TXABLEND_0 0x1c64 #define RADEON_PP_TXABLEND_1 0x1c7c #define RADEON_PP_TXABLEND_2 0x1c94 # define RADEON_ALPHA_ARG_A_SHIFT 0 # define RADEON_ALPHA_ARG_A_MASK (0xf << 0) # define RADEON_ALPHA_ARG_A_ZERO (0 << 0) # define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) # define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) # define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) # define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) # define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0) # define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0) # define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0) # define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0) # define RADEON_ALPHA_ARG_B_SHIFT 4 # define RADEON_ALPHA_ARG_B_MASK (0xf << 4) # define RADEON_ALPHA_ARG_B_ZERO (0 << 4) # define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) # define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) # define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) # define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) # define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4) # define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4) # define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4) # define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4) # define RADEON_ALPHA_ARG_C_SHIFT 8 # define RADEON_ALPHA_ARG_C_MASK (0xf << 8) # define RADEON_ALPHA_ARG_C_ZERO (0 << 8) # define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) # define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) # define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) # define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) # define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8) # define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8) # define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8) # define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8) # define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9) # define RADEON_ALPHA_ARG_MASK 0xf #define RADEON_PP_TFACTOR_0 0x1c68 #define RADEON_PP_TFACTOR_1 0x1c80 #define RADEON_PP_TFACTOR_2 0x1c98 #define RADEON_RB3D_BLENDCNTL 0x1c20 # define RADEON_COMB_FCN_MASK (3 << 12) # define RADEON_COMB_FCN_ADD_CLAMP (0 << 12) # define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12) # define RADEON_COMB_FCN_SUB_CLAMP (2 << 12) # define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12) # define RADEON_SRC_BLEND_GL_ZERO (32 << 16) # define RADEON_SRC_BLEND_GL_ONE (33 << 16) # define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16) # define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) # define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16) # define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) # define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16) # define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) # define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16) # define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) # define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) # define RADEON_SRC_BLEND_MASK (63 << 16) # define RADEON_DST_BLEND_GL_ZERO (32 << 24) # define RADEON_DST_BLEND_GL_ONE (33 << 24) # define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24) # define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) # define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24) # define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) # define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24) # define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) # define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24) # define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) # define RADEON_DST_BLEND_MASK (63 << 24) #define RADEON_RB3D_CNTL 0x1c3c # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) # define RADEON_PLANE_MASK_ENABLE (1 << 1) # define RADEON_DITHER_ENABLE (1 << 2) # define RADEON_ROUND_ENABLE (1 << 3) # define RADEON_SCALE_DITHER_ENABLE (1 << 4) # define RADEON_DITHER_INIT (1 << 5) # define RADEON_ROP_ENABLE (1 << 6) # define RADEON_STENCIL_ENABLE (1 << 7) # define RADEON_Z_ENABLE (1 << 8) # define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) # define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10) # define RADEON_COLOR_FORMAT_RGB565 (4 << 10) # define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10) # define RADEON_COLOR_FORMAT_RGB332 (7 << 10) # define RADEON_COLOR_FORMAT_Y8 (8 << 10) # define RADEON_COLOR_FORMAT_RGB8 (9 << 10) # define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10) # define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10) # define RADEON_COLOR_FORMAT_aYUV444 (14 << 10) # define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10) # define RADEON_CLRCMP_FLIP_ENABLE (1 << 14) # define RADEON_ZBLOCK8 (0 << 15) # define RADEON_ZBLOCK16 (1 << 15) #define RADEON_RB3D_COLOROFFSET 0x1c40 # define RADEON_COLOROFFSET_MASK 0xfffffff0 #define RADEON_RB3D_COLORPITCH 0x1c48 # define RADEON_COLORPITCH_MASK 0x000001ff8 # define RADEON_COLOR_TILE_ENABLE (1 << 16) # define RADEON_COLOR_MICROTILE_ENABLE (1 << 17) # define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18) # define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18) # define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18) #define RADEON_RB3D_DEPTHOFFSET 0x1c24 #define RADEON_RB3D_DEPTHPITCH 0x1c28 # define RADEON_DEPTHPITCH_MASK 0x00001ff8 # define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18) # define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18) # define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) #define RADEON_RB3D_PLANEMASK 0x1d84 #define RADEON_RB3D_ROPCNTL 0x1d80 # define RADEON_ROP_MASK (15 << 8) # define RADEON_ROP_CLEAR (0 << 8) # define RADEON_ROP_NOR (1 << 8) # define RADEON_ROP_AND_INVERTED (2 << 8) # define RADEON_ROP_COPY_INVERTED (3 << 8) # define RADEON_ROP_AND_REVERSE (4 << 8) # define RADEON_ROP_INVERT (5 << 8) # define RADEON_ROP_XOR (6 << 8) # define RADEON_ROP_NAND (7 << 8) # define RADEON_ROP_AND (8 << 8) # define RADEON_ROP_EQUIV (9 << 8) # define RADEON_ROP_NOOP (10 << 8) # define RADEON_ROP_OR_INVERTED (11 << 8) # define RADEON_ROP_COPY (12 << 8) # define RADEON_ROP_OR_REVERSE (13 << 8) # define RADEON_ROP_OR (14 << 8) # define RADEON_ROP_SET (15 << 8) #define RADEON_RB3D_STENCILREFMASK 0x1d7c # define RADEON_STENCIL_REF_SHIFT 0 # define RADEON_STENCIL_REF_MASK (0xff << 0) # define RADEON_STENCIL_MASK_SHIFT 16 # define RADEON_STENCIL_VALUE_MASK (0xff << 16) # define RADEON_STENCIL_WRITEMASK_SHIFT 24 # define RADEON_STENCIL_WRITE_MASK (0xff << 24) #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c # define RADEON_DEPTH_FORMAT_MASK (0xf << 0) # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) # define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) # define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0) # define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) # define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) # define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) # define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) # define RADEON_Z_TEST_NEVER (0 << 4) # define RADEON_Z_TEST_LESS (1 << 4) # define RADEON_Z_TEST_LEQUAL (2 << 4) # define RADEON_Z_TEST_EQUAL (3 << 4) # define RADEON_Z_TEST_GEQUAL (4 << 4) # define RADEON_Z_TEST_GREATER (5 << 4) # define RADEON_Z_TEST_NEQUAL (6 << 4) # define RADEON_Z_TEST_ALWAYS (7 << 4) # define RADEON_Z_TEST_MASK (7 << 4) # define RADEON_HIERARCHICAL_Z_ENABLE (1 << 8) # define RADEON_STENCIL_TEST_NEVER (0 << 12) # define RADEON_STENCIL_TEST_LESS (1 << 12) # define RADEON_STENCIL_TEST_LEQUAL (2 << 12) # define RADEON_STENCIL_TEST_EQUAL (3 << 12) # define RADEON_STENCIL_TEST_GEQUAL (4 << 12) # define RADEON_STENCIL_TEST_GREATER (5 << 12) # define RADEON_STENCIL_TEST_NEQUAL (6 << 12) # define RADEON_STENCIL_TEST_ALWAYS (7 << 12) # define RADEON_STENCIL_S_FAIL_KEEP (0 << 16) # define RADEON_STENCIL_S_FAIL_ZERO (1 << 16) # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) # define RADEON_STENCIL_S_FAIL_INC (3 << 16) # define RADEON_STENCIL_S_FAIL_DEC (4 << 16) # define RADEON_STENCIL_S_FAIL_INVERT (5 << 16) # define RADEON_STENCIL_ZPASS_KEEP (0 << 20) # define RADEON_STENCIL_ZPASS_ZERO (1 << 20) # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) # define RADEON_STENCIL_ZPASS_INC (3 << 20) # define RADEON_STENCIL_ZPASS_DEC (4 << 20) # define RADEON_STENCIL_ZPASS_INVERT (5 << 20) # define RADEON_STENCIL_ZFAIL_KEEP (0 << 20) # define RADEON_STENCIL_ZFAIL_ZERO (1 << 20) # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 20) # define RADEON_STENCIL_ZFAIL_INC (3 << 20) # define RADEON_STENCIL_ZFAIL_DEC (4 << 20) # define RADEON_STENCIL_ZFAIL_INVERT (5 << 20) # define RADEON_Z_COMPRESSION_ENABLE (1 << 28) # define RADEON_FORCE_Z_DIRTY (1 << 29) # define RADEON_Z_WRITE_ENABLE (1 << 30) # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) #define RADEON_RE_LINE_PATTERN 0x1cd0 # define RADEON_LINE_PATTERN_MASK 0x0000ffff # define RADEON_LINE_REPEAT_COUNT_SHIFT 16 # define RADEON_LINE_PATTERN_START_SHIFT 24 # define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) # define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28) # define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29) #define RADEON_RE_LINE_STATE 0x1cd4 # define RADEON_LINE_CURRENT_PTR_SHIFT 0 # define RADEON_LINE_CURRENT_COUNT_SHIFT 8 #define RADEON_RE_MISC 0x26c4 # define RADEON_STIPPLE_COORD_MASK 0x1f # define RADEON_STIPPLE_X_OFFSET_SHIFT 0 # define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0) # define RADEON_STIPPLE_Y_OFFSET_SHIFT 8 # define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8) # define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16) # define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16) #define RADEON_RE_SOLID_COLOR 0x1c1c #define RADEON_RE_TOP_LEFT 0x26c0 # define RADEON_RE_LEFT_SHIFT 0 # define RADEON_RE_TOP_SHIFT 16 #define RADEON_RE_WIDTH_HEIGHT 0x1c44 # define RADEON_RE_WIDTH_SHIFT 0 # define RADEON_RE_HEIGHT_SHIFT 16 #define RADEON_SE_CNTL 0x1c4c # define RADEON_FFACE_CULL_CW (0 << 0) # define RADEON_FFACE_CULL_CCW (1 << 0) # define RADEON_FFACE_CULL_DIR_MASK (1 << 0) # define RADEON_BFACE_CULL (0 << 1) # define RADEON_BFACE_SOLID (3 << 1) # define RADEON_FFACE_CULL (0 << 3) # define RADEON_FFACE_SOLID (3 << 3) # define RADEON_FFACE_CULL_MASK (3 << 3) # define RADEON_BADVTX_CULL_DISABLE (1 << 5) # define RADEON_FLAT_SHADE_VTX_0 (0 << 6) # define RADEON_FLAT_SHADE_VTX_1 (1 << 6) # define RADEON_FLAT_SHADE_VTX_2 (2 << 6) # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) # define RADEON_DIFFUSE_SHADE_SOLID (0 << 8) # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) # define RADEON_DIFFUSE_SHADE_MASK (3 << 8) # define RADEON_ALPHA_SHADE_SOLID (0 << 10) # define RADEON_ALPHA_SHADE_FLAT (1 << 10) # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) # define RADEON_ALPHA_SHADE_MASK (3 << 10) # define RADEON_SPECULAR_SHADE_SOLID (0 << 12) # define RADEON_SPECULAR_SHADE_FLAT (1 << 12) # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) # define RADEON_SPECULAR_SHADE_MASK (3 << 12) # define RADEON_FOG_SHADE_SOLID (0 << 14) # define RADEON_FOG_SHADE_FLAT (1 << 14) # define RADEON_FOG_SHADE_GOURAUD (2 << 14) # define RADEON_FOG_SHADE_MASK (3 << 14) # define RADEON_ZBIAS_ENABLE_POINT (1 << 16) # define RADEON_ZBIAS_ENABLE_LINE (1 << 17) # define RADEON_ZBIAS_ENABLE_TRI (1 << 18) # define RADEON_WIDELINE_ENABLE (1 << 20) # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) # define RADEON_VTX_PIX_CENTER_D3D (0 << 27) # define RADEON_VTX_PIX_CENTER_OGL (1 << 27) # define RADEON_ROUND_MODE_TRUNC (0 << 28) # define RADEON_ROUND_MODE_ROUND (1 << 28) # define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28) # define RADEON_ROUND_MODE_ROUND_ODD (3 << 28) # define RADEON_ROUND_PREC_16TH_PIX (0 << 30) # define RADEON_ROUND_PREC_8TH_PIX (1 << 30) # define RADEON_ROUND_PREC_4TH_PIX (2 << 30) # define RADEON_ROUND_PREC_HALF_PIX (3 << 30) #define R200_RE_CNTL 0x1c50 # define R200_STIPPLE_ENABLE 0x1 # define R200_SCISSOR_ENABLE 0x2 # define R200_PATTERN_ENABLE 0x4 # define R200_PERSPECTIVE_ENABLE 0x8 # define R200_POINT_SMOOTH 0x20 # define R200_VTX_STQ0_D3D 0x00010000 # define R200_VTX_STQ1_D3D 0x00040000 # define R200_VTX_STQ2_D3D 0x00100000 # define R200_VTX_STQ3_D3D 0x00400000 # define R200_VTX_STQ4_D3D 0x01000000 # define R200_VTX_STQ5_D3D 0x04000000 #define RADEON_SE_CNTL_STATUS 0x2140 # define RADEON_VC_NO_SWAP (0 << 0) # define RADEON_VC_16BIT_SWAP (1 << 0) # define RADEON_VC_32BIT_SWAP (2 << 0) # define RADEON_VC_HALF_DWORD_SWAP (3 << 0) # define RADEON_TCL_BYPASS (1 << 8) #define RADEON_SE_COORD_FMT 0x15c0 # define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) # define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) # define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8) # define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9) # define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10) # define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11) # define RADEON_VTX_W0_NORMALIZE (1 << 12) # define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) # define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) # define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) # define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) # define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) # define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26) # define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26) #define RADEON_SE_LINE_WIDTH 0x1db8 #define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c #define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220 #define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 #define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 #define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c #define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c #define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240 #define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 #define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 #define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c #define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c #define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 #define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258 #define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270 #define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274 #define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278 #define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c #define RADEON_SE_TCL_SHININESS 0x2250 #define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268 #define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264 #define RADEON_SE_VPORT_XSCALE 0x1d98 #define RADEON_SE_VPORT_XOFFSET 0x1d9c #define RADEON_SE_VPORT_YSCALE 0x1da0 #define RADEON_SE_VPORT_YOFFSET 0x1da4 #define RADEON_SE_VPORT_ZSCALE 0x1da8 #define RADEON_SE_VPORT_ZOFFSET 0x1dac /* Registers for CP and Microcode Engine */ #define RADEON_CP_ME_RAM_ADDR 0x07d4 #define RADEON_CP_ME_RAM_RADDR 0x07d8 #define RADEON_CP_ME_RAM_DATAH 0x07dc #define RADEON_CP_ME_RAM_DATAL 0x07e0 #define RADEON_CP_RB_BASE 0x0700 #define RADEON_CP_RB_CNTL 0x0704 #define RADEON_CP_RB_RPTR_ADDR 0x070c #define RADEON_CP_RB_RPTR 0x0710 #define RADEON_CP_RB_WPTR 0x0714 #define RADEON_CP_IB_BASE 0x0738 #define RADEON_CP_IB_BUFSZ 0x073c #define RADEON_CP_CSQ_CNTL 0x0740 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) # define RADEON_CSQ_PRIBM_INDBM (4 << 28) # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) #define RADEON_CP_CSQ_STAT 0x07f8 # define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0) # define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8) # define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16) # define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24) #define RADEON_CP_CSQ_ADDR 0x07f0 #define RADEON_CP_CSQ_DATA 0x07f4 #define RADEON_CP_CSQ_APER_PRIMARY 0x1000 #define RADEON_CP_CSQ_APER_INDIRECT 0x1300 #define RADEON_CP_RB_WPTR_DELAY 0x0718 # define RADEON_PRE_WRITE_TIMER_SHIFT 0 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 #define RADEON_AIC_CNTL 0x01d0 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) #define RADEON_AIC_LO_ADDR 0x01dc /* Constants */ #define RADEON_AGP_TEX_OFFSET 0x02000000 #define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 #define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 /* CP packet types */ #define RADEON_CP_PACKET0 0x00000000 #define RADEON_CP_PACKET1 0x40000000 #define RADEON_CP_PACKET2 0x80000000 #define RADEON_CP_PACKET3 0xC0000000 # define RADEON_CP_PACKET_MASK 0xC0000000 # define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 # define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) # define RADEON_CP_PACKET0_REG_MASK 0x000007ff # define RADEON_CP_PACKET1_REG0_MASK 0x000007ff # define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 #define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000 #define RADEON_CP_PACKET3_NOP 0xC0001000 #define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 #define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 #define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 #define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 #define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 #define RADEON_CP_PACKET3_3D_RNDR_GEN_PRIM 0xC0002500 #define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 #define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 #define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 #define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 #define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 #define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 #define RADEON_CP_PACKET3_3D_CLEAR_ZMASK 0xC0003200 #define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 #define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 #define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 #define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 #define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 #define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 #define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 #define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 #define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 #define RADEON_CP_VC_FRMT_XY 0x00000000 #define RADEON_CP_VC_FRMT_W0 0x00000001 #define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002 #define RADEON_CP_VC_FRMT_FPALPHA 0x00000004 #define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008 #define RADEON_CP_VC_FRMT_FPSPEC 0x00000010 #define RADEON_CP_VC_FRMT_FPFOG 0x00000020 #define RADEON_CP_VC_FRMT_PKSPEC 0x00000040 #define RADEON_CP_VC_FRMT_ST0 0x00000080 #define RADEON_CP_VC_FRMT_ST1 0x00000100 #define RADEON_CP_VC_FRMT_Q1 0x00000200 #define RADEON_CP_VC_FRMT_ST2 0x00000400 #define RADEON_CP_VC_FRMT_Q2 0x00000800 #define RADEON_CP_VC_FRMT_ST3 0x00001000 #define RADEON_CP_VC_FRMT_Q3 0x00002000 #define RADEON_CP_VC_FRMT_Q0 0x00004000 #define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000 #define RADEON_CP_VC_FRMT_N0 0x00040000 #define RADEON_CP_VC_FRMT_XY1 0x08000000 #define RADEON_CP_VC_FRMT_Z1 0x10000000 #define RADEON_CP_VC_FRMT_W1 0x20000000 #define RADEON_CP_VC_FRMT_N1 0x40000000 #define RADEON_CP_VC_FRMT_Z 0x80000000 #define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 #define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 #define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a #define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 #define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 #define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 #define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 #define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 #define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080 #define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000 #define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100 #define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000 #define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200 #define RADEON_CP_VC_CNTL_NUM_SHIFT 16 #define RADEON_ISYNC_CNTL 0x1724 #define RADEON_TV_MASTER_CNTL 0x0800 # define RADEON_TV_ASYNC_RST (1 << 0) # define RADEON_CRT_ASYNC_RST (1 << 1) # define RADEON_RESTART_PHASE_FIX (1 << 3) # define RADEON_TV_FIFO_ASYNC_RST (1 << 4) # define RADEON_VIN_ASYNC_RST (1 << 5) # define RADEON_AUD_ASYNC_RST (1 << 6) # define RADEON_DVS_ASYNC_RST (1 << 7) # define RADEON_CRT_FIFO_CE_EN (1 << 9) # define RADEON_TV_FIFO_CE_EN (1 << 10) # define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14) # define RADEON_TVCLK_ALWAYS_ONb (1 << 30) # define RADEON_TV_ON (1 << 31) #define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888 # define RADEON_Y_RED_EN (1 << 0) # define RADEON_C_GRN_EN (1 << 1) # define RADEON_CMP_BLU_EN (1 << 2) # define RADEON_DAC_DITHER_EN (1 << 3) # define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4) # define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8) # define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12) # define RADEON_TV_FORCE_DAC_DATA_SHIFT 16 #define RADEON_TV_RGB_CNTL 0x0804 # define RADEON_SWITCH_TO_BLUE (1 << 4) # define RADEON_RGB_DITHER_EN (1 << 5) # define RADEON_RGB_SRC_SEL_MASK (3 << 8) # define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8) # define RADEON_RGB_SRC_SEL_RMX (1 << 8) # define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8) # define RADEON_RGB_CONVERT_BY_PASS (1 << 10) # define RADEON_UVRAM_READ_MARGIN_SHIFT 16 # define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20 # define RADEON_TVOUT_SCALE_EN (1 << 26) #define RADEON_TV_SYNC_CNTL 0x0808 # define RADEON_SYNC_OE (1 << 0) # define RADEON_SYNC_OUT (1 << 1) # define RADEON_SYNC_IN (1 << 2) # define RADEON_SYNC_PUB (1 << 3) # define RADEON_SYNC_PD (1 << 4) # define RADEON_TV_SYNC_IO_DRIVE (1 << 5) #define RADEON_TV_HTOTAL 0x080c #define RADEON_TV_HDISP 0x0810 #define RADEON_TV_HSTART 0x0818 #define RADEON_TV_HCOUNT 0x081C #define RADEON_TV_VTOTAL 0x0820 #define RADEON_TV_VDISP 0x0824 #define RADEON_TV_VCOUNT 0x0828 #define RADEON_TV_FTOTAL 0x082c #define RADEON_TV_FCOUNT 0x0830 #define RADEON_TV_FRESTART 0x0834 #define RADEON_TV_HRESTART 0x0838 #define RADEON_TV_VRESTART 0x083c #define RADEON_TV_HOST_READ_DATA 0x0840 #define RADEON_TV_HOST_WRITE_DATA 0x0844 #define RADEON_TV_HOST_RD_WT_CNTL 0x0848 # define RADEON_HOST_FIFO_RD (1 << 12) # define RADEON_HOST_FIFO_RD_ACK (1 << 13) # define RADEON_HOST_FIFO_WT (1 << 14) # define RADEON_HOST_FIFO_WT_ACK (1 << 15) #define RADEON_TV_VSCALER_CNTL1 0x084c # define RADEON_UV_INC_MASK 0xffff # define RADEON_UV_INC_SHIFT 0 # define RADEON_Y_W_EN (1 << 24) # define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */ # define RADEON_Y_DEL_W_SIG_SHIFT 26 #define RADEON_TV_TIMING_CNTL 0x0850 # define RADEON_H_INC_MASK 0xfff # define RADEON_H_INC_SHIFT 0 # define RADEON_REQ_Y_FIRST (1 << 19) # define RADEON_FORCE_BURST_ALWAYS (1 << 21) # define RADEON_UV_POST_SCALE_BYPASS (1 << 23) # define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24 #define RADEON_TV_VSCALER_CNTL2 0x0854 # define RADEON_DITHER_MODE (1 << 0) # define RADEON_Y_OUTPUT_DITHER_EN (1 << 1) # define RADEON_UV_OUTPUT_DITHER_EN (1 << 2) # define RADEON_UV_TO_BUF_DITHER_EN (1 << 3) #define RADEON_TV_Y_FALL_CNTL 0x0858 # define RADEON_Y_FALL_PING_PONG (1 << 16) # define RADEON_Y_COEF_EN (1 << 17) #define RADEON_TV_Y_RISE_CNTL 0x085c # define RADEON_Y_RISE_PING_PONG (1 << 16) #define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860 #define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864 # define RADEON_YUPSAMP_EN (1 << 0) # define RADEON_UVUPSAMP_EN (1 << 2) #define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868 # define RADEON_Y_GAIN_LIMIT_SHIFT 0 # define RADEON_UV_GAIN_LIMIT_SHIFT 16 #define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c # define RADEON_Y_GAIN_SHIFT 0 # define RADEON_UV_GAIN_SHIFT 16 #define RADEON_TV_MODULATOR_CNTL1 0x0870 # define RADEON_YFLT_EN (1 << 2) # define RADEON_UVFLT_EN (1 << 3) # define RADEON_ALT_PHASE_EN (1 << 6) # define RADEON_SYNC_TIP_LEVEL (1 << 7) # define RADEON_BLANK_LEVEL_SHIFT 8 # define RADEON_SET_UP_LEVEL_SHIFT 16 # define RADEON_SLEW_RATE_LIMIT (1 << 23) # define RADEON_CY_FILT_BLEND_SHIFT 28 #define RADEON_TV_MODULATOR_CNTL2 0x0874 # define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff # define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff # define RADEON_TV_V_BURST_LEVEL_SHIFT 16 #define RADEON_TV_CRC_CNTL 0x0890 #define RADEON_TV_UV_ADR 0x08ac # define RADEON_MAX_UV_ADR_MASK 0x000000ff # define RADEON_MAX_UV_ADR_SHIFT 0 # define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00 # define RADEON_TABLE1_BOT_ADR_SHIFT 8 # define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000 # define RADEON_TABLE3_TOP_ADR_SHIFT 16 # define RADEON_HCODE_TABLE_SEL_MASK 0x06000000 # define RADEON_HCODE_TABLE_SEL_SHIFT 25 # define RADEON_VCODE_TABLE_SEL_MASK 0x18000000 # define RADEON_VCODE_TABLE_SEL_SHIFT 27 # define RADEON_TV_MAX_FIFO_ADDR 0x1a7 # define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff #define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */ #define RADEON_TV_PLL_CNTL 0x0021 /* PLL */ # define RADEON_TV_M0LO_MASK 0xff # define RADEON_TV_M0HI_MASK 0x3 # define RADEON_TV_M0HI_SHIFT 18 # define RADEON_TV_N0LO_MASK 0xff # define RADEON_TV_N0LO_SHIFT 8 # define RADEON_TV_N0HI_MASK 0x3 # define RADEON_TV_N0HI_SHIFT 21 # define RADEON_TV_P_MASK 0xf # define RADEON_TV_P_SHIFT 24 # define RADEON_TV_SLIP_EN (1 << 23) # define RADEON_TV_DTO_EN (1 << 28) #define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */ # define RADEON_TVPLL_RESET (1 << 1) # define RADEON_TVPLL_SLEEP (1 << 3) # define RADEON_TVPLL_REFCLK_SEL (1 << 4) # define RADEON_TVPCP_SHIFT 8 # define RADEON_TVPCP_MASK (7 << 8) # define RADEON_TVPVG_SHIFT 11 # define RADEON_TVPVG_MASK (7 << 11) # define RADEON_TVPDC_SHIFT 14 # define RADEON_TVPDC_MASK (3 << 14) # define RADEON_TVPLL_TEST_DIS (1 << 31) # define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) #define RADEON_RS480_UNK_e30 0xe30 #define RADEON_RS480_UNK_e34 0xe34 #define RADEON_RS480_UNK_e38 0xe38 #define RADEON_RS480_UNK_e3c 0xe3c #define RS480_NB_MC_INDEX 0x168 #define RS480_NB_MC_DATA 0x16c #define RS690_NB_MC_INDEX 0x78 # define RS690_MC_INDEX_MASK 0x1ff # define RS690_MC_INDEX_WR_EN (1 << 9) # define RS690_MC_INDEX_WR_ACK 0x7f #define RS690_NB_MC_DATA 0x7c #define AVIVO_MC_INDEX 0x0070 #define R520_MC_STATUS 0x00 #define R520_MC_STATUS_IDLE (1<<1) #define RV515_MC_STATUS 0x08 #define RV515_MC_STATUS_IDLE (1<<4) #define AVIVO_MC_DATA 0x0074 #define RV515_MC_FB_LOCATION 0x1 #define RV515_MC_AGP_LOCATION 0x2 #define R520_MC_FB_LOCATION 0x4 #define R520_MC_AGP_LOCATION 0x5 #define AVIVO_HDP_FB_LOCATION 0x134 #define AVIVO_D1VGA_CONTROL 0x0330 # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) # define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9) # define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) # define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16) # define AVIVO_DVGA_CONTROL_ROTATE (1<<24) #define AVIVO_D2VGA_CONTROL 0x0338 #define AVIVO_VGA_MAIN_CONTROL 0x350 #define AVIVO_VGA25_PPLL_REF_DIV_SRC 0x360 #define AVIVO_VGA25_PPLL_REF_DIV 0x364 #define AVIVO_VGA28_PPLL_REF_DIV_SRC 0x368 #define AVIVO_VGA28_PPLL_REF_DIV 0x36c #define AVIVO_VGA41_PPLL_REF_DIV_SRC 0x370 #define AVIVO_VGA41_PPLL_REF_DIV 0x374 #define AVIVO_VGA25_PPLL_FB_DIV 0x378 #define AVIVO_VGA28_PPLL_FB_DIV 0x37c #define AVIVO_VGA41_PPLL_FB_DIV 0x380 #define AVIVO_VGA25_PPLL_POST_DIV_SRC 0x384 #define AVIVO_VGA25_PPLL_POST_DIV 0x388 #define AVIVO_VGA28_PPLL_POST_DIV_SRC 0x38c #define AVIVO_VGA28_PPLL_POST_DIV 0x390 #define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400 #define AVIVO_EXT1_PPLL_REF_DIV 0x404 #define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408 #define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c #define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410 #define AVIVO_EXT2_PPLL_REF_DIV 0x414 #define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418 #define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c #define AVIVO_EXT1_PPLL_FB_DIV 0x430 #define AVIVO_EXT2_PPLL_FB_DIV 0x434 #define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438 #define AVIVO_EXT1_PPLL_POST_DIV 0x43c #define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440 #define AVIVO_EXT2_PPLL_POST_DIV 0x444 #define AVIVO_EXT1_PPLL_CNTL 0x448 #define AVIVO_EXT2_PPLL_CNTL 0x44c #define AVIVO_P1PLL_CNTL 0x450 #define AVIVO_P2PLL_CNTL 0x454 #define AVIVO_P1PLL_INT_SS_CNTL 0x458 #define AVIVO_P2PLL_INT_SS_CNTL 0x45c #define AVIVO_P1PLL_TMDSA_CNTL 0x460 #define AVIVO_P2PLL_LVTMA_CNTL 0x464 #define AVIVO_PCLK_CRTC1_CNTL 0x480 #define AVIVO_PCLK_CRTC2_CNTL 0x484 #define SD1_MAIN_CNTL 0x5dfc #define SD1_MAIN_CNTL2 0x5e00 #define SD1_TIMING_H_TOTAL 0x5e04 #define SD1_TIMING_V_F_TOTAL 0x5e08 #define SD1_TIMING_H_COUNT 0x5e0c #define SD1_TIMING_V_F_COUNT 0x5e10 #define SD1_TIMING_H_COUNT_INIT 0x5e14 #define SD1_TIMING_V_F_COUNT_INIT 0x5e18 #define SD1_TIMING_INTERNAL_INIT 0x5e1c #define SD1_TIMING_H_HSYNC 0x5e20 #define SD1_TIMING_H_EQUALIZATION1 0x5e24 #define SD1_TIMING_H_EQUALIZATION2 0x5e28 #define SD1_TIMING_H_SERATION1 0x5e2c #define SD1_TIMING_H_SERATION2 0x5e30 #define SD1_TIMING_V_EQUALIZATION1 0x5e34 #define SD1_TIMING_V_EQUALIZATION2 0x5e38 #define SD1_TIMING_V_SERATION1 0x5e3c #define SD1_TIMING_V_SERATION2 0x5e40 #define SD1_TIMING_H_BURST 0x5e44 #define SD1_TIMING_V_BURST1 0x5e48 #define SD1_TIMING_V_BURST2 0x5e4c #define SD1_TIMING_H_SETUP1 0x5e50 #define SD1_TIMING_H_SETUP2 0x5e54 #define SD1_TIMING_V_SETUP1 0x5e58 #define SD1_TIMING_V_SETUP2 0x5e5c #define SD1_TIMING_H_ADV_ACTIVE 0x5e60 #define SD1_TIMING_V_ACTIVE1 0x5e64 #define SD1_TIMING_V_ACTIVE2 0x5e68 #define SD1_VIDOUT_MUX_CNTL 0x5ec8 #define SD1_FORCE_DAC_DATA 0x5ecc #define SD1_CHROMA_MOD_CNTL 0x5ef0 #define SD1_UPSAMPLE_MODE 0x5f94 #define SD1_CRTC_HV_START 0x5f98 #define SD1_CRTC_TV_FRAMESTART_CNTL 0x5f9c #define AVIVO_D1CRTC_H_TOTAL 0x6000 #define AVIVO_D1CRTC_H_BLANK_START_END 0x6004 #define AVIVO_D1CRTC_H_SYNC_A 0x6008 #define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c #define AVIVO_D1CRTC_H_SYNC_B 0x6010 #define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014 #define AVIVO_D1CRTC_V_TOTAL 0x6020 #define AVIVO_D1CRTC_V_BLANK_START_END 0x6024 #define AVIVO_D1CRTC_V_SYNC_A 0x6028 #define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c #define AVIVO_D1CRTC_V_SYNC_B 0x6030 #define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034 #define AVIVO_D1CRTC_CONTROL 0x6080 # define AVIVO_CRTC_EN (1<<0) #define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 #define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 #define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c #define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 /* master controls */ #define AVIVO_DC_CRTC_MASTER_EN 0x60f8 #define AVIVO_DC_CRTC_TV_CONTROL 0x60fc #define AVIVO_D1GRPH_ENABLE 0x6100 #define AVIVO_D1GRPH_CONTROL 0x6104 # define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0) # define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0) # define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0) # define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0) # define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8) # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8) # define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8) # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8) # define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8) # define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8) # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8) # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8) # define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8) # define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8) # define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8) # define AVIVO_D1GRPH_SWAP_RB (1<<16) # define AVIVO_D1GRPH_TILED (1<<20) # define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21) #define AVIVO_D1GRPH_LUT_SEL 0x6108 #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 #define AVIVO_D1GRPH_PITCH 0x6120 #define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 #define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 #define AVIVO_D1GRPH_X_START 0x612c #define AVIVO_D1GRPH_Y_START 0x6130 #define AVIVO_D1GRPH_X_END 0x6134 #define AVIVO_D1GRPH_Y_END 0x6138 #define AVIVO_D1GRPH_UPDATE 0x6144 #define AVIVO_D1GRPH_FLIP_CONTROL 0x6148 #define AVIVO_D1CUR_CONTROL 0x6400 # define AVIVO_D1CURSOR_EN (1<<0) # define AVIVO_D1CURSOR_MODE_SHIFT 8 # define AVIVO_D1CURSOR_MODE_MASK (0x3<<8) # define AVIVO_D1CURSOR_MODE_24BPP (0x2) #define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 #define AVIVO_D1CUR_SIZE 0x6410 #define AVIVO_D1CUR_POSITION 0x6414 #define AVIVO_D1CUR_HOT_SPOT 0x6418 #define AVIVO_D1MODE_VIEWPORT_START 0x6580 #define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 #define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 #define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c #define AVIVO_D1SCL_SCALER_ENABLE 0x6590 #define AVIVO_D1SCL_BYPASS_CONTROL 0x659c /* second crtc */ #define AVIVO_D2CRTC_H_TOTAL 0x6800 #define AVIVO_D2CRTC_H_BLANK_START_END 0x6804 #define AVIVO_D2CRTC_H_SYNC_A 0x6808 #define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c #define AVIVO_D2CRTC_H_SYNC_B 0x6810 #define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814 #define AVIVO_D2CRTC_V_TOTAL 0x6820 #define AVIVO_D2CRTC_V_BLANK_START_END 0x6824 #define AVIVO_D2CRTC_V_SYNC_A 0x6828 #define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c #define AVIVO_D2CRTC_V_SYNC_B 0x6830 #define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834 #define AVIVO_D2CRTC_CONTROL 0x6880 #define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 #define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 #define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c #define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4 #define AVIVO_D2GRPH_ENABLE 0x6900 #define AVIVO_D2GRPH_CONTROL 0x6904 #define AVIVO_D2GRPH_LUT_SEL 0x6908 #define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 #define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 #define AVIVO_D2GRPH_PITCH 0x6920 #define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924 #define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928 #define AVIVO_D2GRPH_X_START 0x692c #define AVIVO_D2GRPH_Y_START 0x6930 #define AVIVO_D2GRPH_X_END 0x6934 #define AVIVO_D2GRPH_Y_END 0x6938 #define AVIVO_D2GRPH_UPDATE 0x6944 #define AVIVO_D2GRPH_FLIP_CONTROL 0x6948 #define AVIVO_D2CUR_CONTROL 0x6c00 #define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08 #define AVIVO_D2CUR_SIZE 0x6c10 #define AVIVO_D2CUR_POSITION 0x6c14 #define AVIVO_D2MODE_VIEWPORT_START 0x6d80 #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 #define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c #define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 #define AVIVO_D2SCL_BYPASS_CONTROL 0x6d9c #define AVIVO_DAC_ENABLE_OFFSET 0x0 #define AVIVO_DAC_SOURCE_SELECT_OFFSET 0x4 #define AVIVO_DAC_FORCE_OUTPUT_CNTL_OFFSET 0x3c #define AVIVO_DAC_POWERDOWN_OFFSET 0x50 #define AVIVO_DACA_ENABLE 0x7800 # define AVIVO_DAC_ENABLE (1 << 0) #define AVIVO_DACA_SOURCE_SELECT 0x7804 # define AVIVO_DAC_SOURCE_CRTC1 (0 << 0) # define AVIVO_DAC_SOURCE_CRTC2 (1 << 0) # define AVIVO_DAC_SOURCE_TV (2 << 0) #define AVIVO_DACA_BASE 0x7800 #define AVIVO_DACB_BASE 0x7a00 #define RV620_DACA_BASE 0x7000 #define RV620_DACB_BASE 0x7100 #define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c # define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) #define AVIVO_DACA_POWERDOWN 0x7850 # define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0) # define AVIVO_DACA_POWERDOWN_BLUE (1 << 8) # define AVIVO_DACA_POWERDOWN_GREEN (1 << 16) # define AVIVO_DACA_POWERDOWN_RED (1 << 24) #define AVIVO_DACB_ENABLE 0x7a00 #define AVIVO_DACB_SOURCE_SELECT 0x7a04 #define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c # define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) #define AVIVO_DACB_POWERDOWN 0x7a50 # define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0) # define AVIVO_DACB_POWERDOWN_BLUE (1 << 8) # define AVIVO_DACB_POWERDOWN_GREEN (1 << 16) # define AVIVO_DACB_POWERDOWN_RED #define AVIVO_TMDSA_CNTL 0x7880 # define AVIVO_TMDSA_CNTL_ENABLE (1 << 0) # define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4) # define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8) # define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12) # define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16) # define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24) # define AVIVO_TMDSA_CNTL_SWAP (1 << 28) #define AVIVO_TMDSA_CRTC_SOURCE 0x7884 /* 78a8 appears to be some kind of (reasonably tolerant) clock? * 78d0 definitely hits the transmitter, definitely clock. */ /* MYSTERY1 This appears to control dithering? */ #define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894 # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) #define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0 # define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0) # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8) # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) # define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24) #define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8 # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) #define AVIVO_TMDSA_CLOCK_ENABLE 0x7900 #define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904 # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) #define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910 # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) # define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) #define AVIVO_LVTMA_CNTL 0x7a80 # define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) # define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) # define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) # define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) # define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16) # define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24) # define AVIVO_LVTMA_CNTL_SWAP (1 << 28) #define AVIVO_LVTMA_SOURCE_SELECT 0x7a84 #define AVIVO_LVTMA_COLOR_FORMAT 0x7a88 #define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94 # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) #define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0 # define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0) # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8) # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) # define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24) #define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) #define AVIVO_LVTMA_CLOCK_ENABLE 0x7b00 #define AVIVO_LVTMA_TRANSMITTER_ENABLE 0x7b04 # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) #define AVIVO_LVTMA_TRANSMITTER_CONTROL 0x7b10 # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) # define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) #define AVIVO_LVTMA_PWRSEQ_CNTL 0x7af0 # define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) # define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) # define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) # define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4) # define AVIVO_LVTMA_SYNCEN (1 << 8) # define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9) # define AVIVO_LVTMA_SYNCEN_POL (1 << 10) # define AVIVO_LVTMA_DIGON (1 << 16) # define AVIVO_LVTMA_DIGON_OVRD (1 << 17) # define AVIVO_LVTMA_DIGON_POL (1 << 18) # define AVIVO_LVTMA_BLON (1 << 24) # define AVIVO_LVTMA_BLON_OVRD (1 << 25) # define AVIVO_LVTMA_BLON_POL (1 << 26) #define AVIVO_LVTMA_PWRSEQ_STATE 0x7af4 # define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) # define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) # define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) # define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3) # define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4) # define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8) #define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8 # define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0) # define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 # define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 #define AVIVO_GPIO_0 0x7e30 #define AVIVO_GPIO_1 0x7e40 #define AVIVO_GPIO_2 0x7e50 #define AVIVO_GPIO_3 0x7e60 #define AVIVO_DC_GPIO_HPD_Y 0x7e9c #define AVIVO_I2C_STATUS 0x7d30 # define AVIVO_I2C_STATUS_DONE (1 << 0) # define AVIVO_I2C_STATUS_NACK (1 << 1) # define AVIVO_I2C_STATUS_HALT (1 << 2) # define AVIVO_I2C_STATUS_GO (1 << 3) # define AVIVO_I2C_STATUS_MASK 0x7 /* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe * DONE? */ # define AVIVO_I2C_STATUS_CMD_RESET 0x7 # define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3) #define AVIVO_I2C_STOP 0x7d34 #define AVIVO_I2C_START_CNTL 0x7d38 # define AVIVO_I2C_START (1 << 8) # define AVIVO_I2C_CONNECTOR0 (0 << 16) # define AVIVO_I2C_CONNECTOR1 (1 << 16) #define R520_I2C_START (1<<0) #define R520_I2C_STOP (1<<1) #define R520_I2C_RX (1<<2) #define R520_I2C_EN (1<<8) #define R520_I2C_DDC1 (0<<16) #define R520_I2C_DDC2 (1<<16) #define R520_I2C_DDC3 (2<<16) #define R520_I2C_DDC_MASK (3<<16) #define AVIVO_I2C_CONTROL2 0x7d3c # define AVIVO_I2C_7D3C_SIZE_SHIFT 8 # define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8) #define AVIVO_I2C_CONTROL3 0x7d40 /* Reading is done 4 bytes at a time: read the bottom 8 bits from * 7d44, four times in a row. * Writing is a little more complex. First write DATA with * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic * magic number, zz is, I think, the slave address, and yy is the byte * you want to write. */ #define AVIVO_I2C_DATA 0x7d44 #define R520_I2C_ADDR_COUNT_MASK (0x7) #define R520_I2C_DATA_COUNT_SHIFT (8) #define R520_I2C_DATA_COUNT_MASK (0xF00) #define AVIVO_I2C_CNTL 0x7d50 # define AVIVO_I2C_EN (1 << 0) # define AVIVO_I2C_RESET (1 << 8) #define AVIVO_ENGINE_STATUS 0x14 /* Audio clocks */ #define DCE3_DCCG_AUDIO_DTO0_PHASE 0x0514 #define DCE3_DCCG_AUDIO_DTO0_MODULE 0x0518 #define DCE3_DCCG_AUDIO_DTO0_LOAD 0x051c #define DCE3_DCCG_AUDIO_DTO0_CNTL 0x0520 #define DCE3_DCCG_AUDIO_DTO1_PHASE 0x0524 #define DCE3_DCCG_AUDIO_DTO1_MODULE 0x0528 #define DCE3_DCCG_AUDIO_DTO1_LOAD 0x052c #define DCE3_DCCG_AUDIO_DTO1_CNTL 0x0530 #define DCE3_DCCG_AUDIO_DTO_SELECT 0x0534 #define R600_MC_VM_FB_LOCATION 0x2180 #define R600_MC_VM_AGP_TOP 0x2184 #define R600_MC_VM_AGP_BOT 0x2188 #define R600_MC_VM_AGP_BASE 0x218c #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 #define R600_BUS_CNTL 0x5420 #define R600_CONFIG_CNTL 0x5424 #define R600_CONFIG_MEMSIZE 0x5428 #define R600_CONFIG_F0_BASE 0x542C #define R600_CONFIG_APER_SIZE 0x5430 /* Audio general */ #define R600_AUDIO_ENABLE 0x7300 #define DCE32_AZ_HOT_PLUG_CONTROL 0x7300 #define DCE2_AUDIO_DTO 0x7340 #define R600_AUDIO_DTO_SELECT 0x7344 /* Allows forcing audio to use specified DTO */ /* Audio params */ #define R600_AUDIO_VENDOR_ID 0x7380 #define R600_AUDIO_REVISION_ID 0x7384 #define R600_AUDIO_ROOT_NODE_COUNT 0x7388 #define R600_AUDIO_NID1_NODE_COUNT 0x738c #define R600_AUDIO_NID1_TYPE 0x7390 #define R600_AUDIO_SUPPORTED_SIZE_RATE 0x7394 #define R600_AUDIO_SUPPORTED_CODEC 0x7398 #define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c #define R600_AUDIO_NID2_CAPS 0x73a0 #define R600_AUDIO_NID3_CAPS 0x73a4 #define R600_AUDIO_NID3_PIN_CAPS 0x73a8 /* Audio conn list */ #define R600_AUDIO_CONN_LIST_LEN 0x73ac #define R600_AUDIO_CONN_LIST 0x73b0 /* Audio verbs */ #define R600_AUDIO_RATE_BPS_CHANNEL 0x73c0 #define R600_AUDIO_PLAYING 0x73c4 #define R600_AUDIO_IMPLEMENTATION_ID 0x73c8 #define R600_AUDIO_CONFIG_DEFAULT 0x73cc #define R600_AUDIO_PIN_SENSE 0x73d0 #define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4 #define R600_AUDIO_STATUS_BITS 0x73d8 /* HDMI base register addresses */ #define DCE2_HDMI_BLOCK0 0x7400 #define DCE2_HDMI_BLOCK1 0x7700 /* DCE3 second instance starts at 0x7800 */ #define DCE3_HDMI_BLOCK0 0x7400 #define DCE3_HDMI_BLOCK1 0x7800 #define RADEON_MC_ARB_CNTL 0x18c #define RADEON_PWRMAN_MISC 0x16 #define RADEON_SS_INT_CNTL 0x33 #define RADEON_RBBM_CMDFIFO_ADDR 0xe70 #define RADEON_RBBM_CMDFIFO_DATA 0xe74 #define RADEON_RBBM_CMDFIFO_STAT 0xe7c #define RADEON_CLK_TEST_ONE 0x1d #define RADEON_SPLL_CNTL 0x0c #define RADEON_CLK_PWRMGT_CNTL 0x14 #define RADEON_PLL_PWRMGT_CNTL 0x15 #define RADEON_MC_DEBUG 0x188 #endif /* Audio clocks */ #define DCE4_DCCG_AUDIO_DTO_SOURCE 0x05ac #define DCE4_DCCG_AUDIO_DTO0_PHASE 0x05b0 #define DCE4_DCCG_AUDIO_DTO0_MODULE 0x05b4 #define DCE4_DCCG_AUDIO_DTO0_LOAD 0x05b8 #define DCE4_DCCG_AUDIO_DTO0_CNTL 0x05bc #define DCE4_DCCG_AUDIO_DTO1_PHASE 0x05c0 #define DCE4_DCCG_AUDIO_DTO1_MODULE 0x05c4 #define DCE4_DCCG_AUDIO_DTO1_LOAD 0x05c8 #define DCE4_DCCG_AUDIO_DTO1_CNTL 0x05cc #define DCE4_AZ_HOT_PLUG_CONTROL 0x5e78 #define EVERGREEN_AUDIO_VENDOR_ID 0x5ec0 #define EVERGREEN_AUDIO_RATE_BPS_CHANNEL 0x5f00 #define EVERGREEN_AUDIO_PLAYING 0x5f04 #define EVERGREEN_AUDIO_CAT_STATUS 0x5f18 /* GRPH blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */ #define EVERGREEN_GRPH_ENABLE 0x6800 #define EVERGREEN_GRPH_CONTROL 0x6804 #define EVERGREEN_GRPH_SWAP_CONTROL 0x680c #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x6810 #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x6814 #define EVERGREEN_GRPH_PITCH 0x6818 #define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x681c #define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x6820 #define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x6824 #define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x6828 #define EVERGREEN_GRPH_X_START 0x682c #define EVERGREEN_GRPH_Y_START 0x6830 #define EVERGREEN_GRPH_X_END 0x6834 #define EVERGREEN_GRPH_Y_END 0x6838 /* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ #define EVERGREEN_CUR_CONTROL 0x6998 #define EVERGREEN_CUR_SURFACE_ADDRESS 0x699c #define EVERGREEN_CUR_SIZE 0x69a0 #define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x69a4 #define EVERGREEN_CUR_POSITION 0x69a8 /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ #define EVERGREEN_CRTC0_REGISTER_OFFSET (0x6df0 - 0x6df0) #define EVERGREEN_CRTC1_REGISTER_OFFSET (0x79f0 - 0x6df0) #define EVERGREEN_CRTC2_REGISTER_OFFSET (0x105f0 - 0x6df0) #define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0) #define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0) #define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0) #define EVERGREEN_VIEWPORT_START 0x6d70 #define EVERGREEN_VIEWPORT_SIZE 0x6d74 /* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ #define EVERGREEN_CRTC_CONTROL 0x6e70 #define EVERGREEN_DIG_CNTL 0x7000 # define EVERGREEN_DIG_CNTL_ENC_MODE_MASK 0x7000 # define EVERGREEN_DIG_CNTL_ENC_MODE_SHIFT 12 # define EVERGREEN_DIG_CNTL_ENC_MODE_DP 0 # define EVERGREEN_DIG_CNTL_ENC_MODE_LVDS 1 # define EVERGREEN_DIG_CNTL_ENC_MODE_DVI 2 # define EVERGREEN_DIG_CNTL_ENC_MODE_HDMI 3 # define EVERGREEN_DIG_CNTL_ENC_MODE_SDVO 4 /* HDMI blocks at 0x7030, 0x7c30, 0x10830, 0x11430, 0x12030, 0x12c30 */ #define EVERGREEN_HDMI_BASE 0x7030 /* from ROM tables, EG DAC1 is at 0x66b0 and DAC2 at 0x6790 */ #define EVERGREEN_DACA_BASE 0x6690 #define EVERGREEN_DACB_BASE 0x6790 #define EVERGREEN_DACA_CONTROL 0x6690 #define EVERGREEN_DACA_SOURCE_SELECT 0x6694 #define EVERGREEN_DACB_CONTROL 0x6790 /* DCE6 registers for indirect audio engine access */ #define DCE6_AUDIO_ADDR 0x5e00 #define DCE6_AUDIO_DATA 0x5e04 #define MC_VM_FB_LOCATION 0x2024 #define MC_VM_AGP_TOP 0x2028 #define MC_VM_AGP_BOT 0x202C #define MC_VM_AGP_BASE 0x2030 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C #define MC_FUS_VM_FB_OFFSET 0x2898 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c