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authorRafał Miłecki <zajec5@gmail.com>2011-12-20 09:44:48 +0100
committerDave Airlie <airlied@redhat.com>2011-12-20 10:14:37 +0000
commit1e2863cbd861b86be7864e945cfc1a10885eaaa4 (patch)
treeeaebb27b7f20d5482947120d4b9a255c376c77af
parentee909f17f5dfecba935c50f1f5c04a6901a284b3 (diff)
avivotool: allow reading HDMI related regs on R600
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r--avivotool.c46
-rw-r--r--radeon_reg.h42
2 files changed, 88 insertions, 0 deletions
diff --git a/avivotool.c b/avivotool.c
index 33469d6..b8e3c5e 100644
--- a/avivotool.c
+++ b/avivotool.c
@@ -1117,6 +1117,7 @@ void radeon_cmd_regs(const char *type)
int show_pll1 = (show_all || strstr(type, "pll1"));
int show_pll2 = (show_all || strstr(type, "pll2"));
int show_tv = (show_all || strstr(type, "tv"));
+ int show_hdmi = (show_all || strstr(type, "hdmi"));
int shut_up = 1;
int tmp; /* may be stomped at any moment. */
unsigned long i;
@@ -1613,7 +1614,52 @@ void radeon_cmd_regs(const char *type)
SHOW_REG(SD1_CRTC_TV_FRAMESTART_CNTL);
}
+ if (show_hdmi) {
+ printf("\nAudio clocks:\n");
+ SHOW_REG(R600_AUDIO_PLL1_MUL);
+ SHOW_REG(R600_AUDIO_PLL1_DIV);
+ SHOW_REG(R600_AUDIO_PLL2_MUL);
+ SHOW_REG(R600_AUDIO_PLL2_DIV);
+ SHOW_REG(R600_AUDIO_CLK_SRCSEL);
+
+ printf("\nAudio general:\n");
+ SHOW_REG(R600_AUDIO_ENABLE);
+ SHOW_REG(R600_AUDIO_TIMING);
+
+ printf("\nAudio params:\n");
+ SHOW_REG(R600_AUDIO_VENDOR_ID);
+ SHOW_REG(R600_AUDIO_REVISION_ID);
+ SHOW_REG(R600_AUDIO_ROOT_NODE_COUNT);
+ SHOW_REG(R600_AUDIO_NID1_NODE_COUNT);
+ SHOW_REG(R600_AUDIO_NID1_TYPE);
+ SHOW_REG(R600_AUDIO_SUPPORTED_SIZE_RATE);
+ SHOW_REG(R600_AUDIO_SUPPORTED_CODEC);
+ SHOW_REG(R600_AUDIO_SUPPORTED_POWER_STATES);
+ SHOW_REG(R600_AUDIO_NID2_CAPS);
+ SHOW_REG(R600_AUDIO_NID3_CAPS);
+ SHOW_REG(R600_AUDIO_NID3_PIN_CAPS);
+
+ printf("\nAudio conn list:\n");
+ SHOW_REG(R600_AUDIO_CONN_LIST_LEN);
+ SHOW_REG(R600_AUDIO_CONN_LIST);
+
+ printf("\nAudio verbs:\n");
+ SHOW_REG(R600_AUDIO_RATE_BPS_CHANNEL);
+ SHOW_REG(R600_AUDIO_PLAYING);
+ SHOW_REG(R600_AUDIO_IMPLEMENTATION_ID);
+ SHOW_REG(R600_AUDIO_CONFIG_DEFAULT);
+ SHOW_REG(R600_AUDIO_PIN_SENSE);
+ SHOW_REG(R600_AUDIO_PIN_WIDGET_CNTL);
+ SHOW_REG(R600_AUDIO_STATUS_BITS);
+
+ printf("\nHDMI block at 0x%x:\n", R600_HDMI_BLOCK1);
+ for (i = R600_HDMI_BLOCK1; i < R600_HDMI_BLOCK1 + 0xf0; i += 4)
+ SHOW_UNKNOWN_REG(i);
+ printf("\nHDMI block at 0x%x:\n", R600_HDMI_BLOCK3);
+ for (i = R600_HDMI_BLOCK3; i < R600_HDMI_BLOCK3 + 0xf0; i += 4)
+ SHOW_UNKNOWN_REG(i);
+ }
}
void radeon_regsrange(unsigned int start, unsigned int end)
diff --git a/radeon_reg.h b/radeon_reg.h
index 98a8eee..f564714 100644
--- a/radeon_reg.h
+++ b/radeon_reg.h
@@ -3005,6 +3005,13 @@
#define AVIVO_ENGINE_STATUS 0x14
+/* Audio clocks */
+#define R600_AUDIO_PLL1_MUL 0x0514
+#define R600_AUDIO_PLL1_DIV 0x0518
+#define R600_AUDIO_PLL2_MUL 0x0524
+#define R600_AUDIO_PLL2_DIV 0x0528
+#define R600_AUDIO_CLK_SRCSEL 0x0534
+
#define R600_MC_VM_FB_LOCATION 0x2180
#define R600_MC_VM_AGP_TOP 0x2184
#define R600_MC_VM_AGP_BOT 0x2188
@@ -3019,6 +3026,41 @@
#define R600_CONFIG_F0_BASE 0x542C
#define R600_CONFIG_APER_SIZE 0x5430
+/* Audio general */
+#define R600_AUDIO_ENABLE 0x7300
+#define R600_AUDIO_TIMING 0x7344
+
+/* Audio params */
+#define R600_AUDIO_VENDOR_ID 0x7380
+#define R600_AUDIO_REVISION_ID 0x7384
+#define R600_AUDIO_ROOT_NODE_COUNT 0x7388
+#define R600_AUDIO_NID1_NODE_COUNT 0x738c
+#define R600_AUDIO_NID1_TYPE 0x7390
+#define R600_AUDIO_SUPPORTED_SIZE_RATE 0x7394
+#define R600_AUDIO_SUPPORTED_CODEC 0x7398
+#define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c
+#define R600_AUDIO_NID2_CAPS 0x73a0
+#define R600_AUDIO_NID3_CAPS 0x73a4
+#define R600_AUDIO_NID3_PIN_CAPS 0x73a8
+
+/* Audio conn list */
+#define R600_AUDIO_CONN_LIST_LEN 0x73ac
+#define R600_AUDIO_CONN_LIST 0x73b0
+
+/* Audio verbs */
+#define R600_AUDIO_RATE_BPS_CHANNEL 0x73c0
+#define R600_AUDIO_PLAYING 0x73c4
+#define R600_AUDIO_IMPLEMENTATION_ID 0x73c8
+#define R600_AUDIO_CONFIG_DEFAULT 0x73cc
+#define R600_AUDIO_PIN_SENSE 0x73d0
+#define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4
+#define R600_AUDIO_STATUS_BITS 0x73d8
+
+/* HDMI base register addresses */
+#define R600_HDMI_BLOCK1 0x7400
+#define R600_HDMI_BLOCK2 0x7700
+#define R600_HDMI_BLOCK3 0x7800
+
#define RADEON_MC_ARB_CNTL 0x18c
#define RADEON_PWRMAN_MISC 0x16
#define RADEON_SS_INT_CNTL 0x33