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2015-09-21drm/amdgpu: Add DM (Display Manager)DAL-wipHarry Wentland16-11/+4151
This is the interface we use to bridge the drm modesetting APIs with the internal DAL APIs. The idea behind this is to allow us to separate the hw abstractions and programming sequences and the high level APIs. It also allows us to easily change internal APIs without affecting the higher level APIs and allows us to easily support changes to the high level APIs such as adding plane support and transitioning to the atomic modesetting API. Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: DAL InterfaceHarry Wentland7-3/+2424
This abstracts our internal hw programming sequences so we can (a) test it in user space and (b) use it more easily with current and future kernel modesetting APIs such as atomic. SW Layer /===============================================================\ | DAL Display Timing Mode Asic | | Interface Service Service Manager Capability | | | | Display Topology Display Link Adapter | | Path Manager Capability Service Service | | Service | |---------------------------------------------------------------| | GPIO IRQ I2cAux HW BIOS | | Service Manager Sequencer Parser | | | | Connector Encoder Audio GPU Controller | | | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: Display ServiceHarry Wentland41-2/+16099
The display service maintains display state, implements driver feature policy, builds parameters for HW programming, and call HWSS to program HW. SW Layer /===============================================================\ | Display Timing Mode Asic | | Service Service Manager Capability | | | | Display Topology Display Link Adapter | | Path Manager Capability Service Service | | Service | |---------------------------------------------------------------| | GPIO IRQ I2cAux HW BIOS | | Service Manager Sequencer Parser | | | | Connector Encoder Audio GPU Controller | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: TopologyManagerHarry Wentland19-1/+16731
The topology manager is responsible for creating and management of graphics objects and display paths. It also encapsulates the display detection logic. SW Layer /===============================================================\ | Timing Mode Asic | | Service Manager Capability | | | | Display Topology Display Link Adapter | | Path Manager Capability Service Service | | Service | |---------------------------------------------------------------| | GPIO IRQ I2cAux HW BIOS | | Service Manager Sequencer Parser | | | | Connector Encoder Audio GPU Controller | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: Mode ManagerHarry Wentland31-1/+6485
The mode manager implements mode enumeration. It maintains a list of render modes for all connected displays. For each display mode manager fetches the list of timings from Display Capability Service (DCS). For each requested video network topology, Mode Manager will enumerate valid combinations of render modes and timings. SW Layer /===============================================================\ | Timing Mode Asic | | Service Manager Capability | | | | Display Display Link Adapter | | Path Capability Service Service | | Service | |---------------------------------------------------------------| | GPIO IRQ I2cAux HW BIOS | | Service Manager Sequencer Parser | | | | Connector Encoder Audio GPU Controller | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: Link ServiceHarry Wentland8-1/+6382
Implements policy and logic for video stream backend enablement. Also maintains some part of display (sink) capabilities. It manages DisplayPort links, including link training and short pulse interrupt handling. SW Layer /===============================================================\ | Timing Asic | | Service Capability | | | | Display Display Link Adapter | | Path Capability Service Service | | Service | |---------------------------------------------------------------| | GPIO IRQ I2cAux HW BIOS | | Service Manager Sequencer Parser | | | | Connector Encoder Audio GPU Controller | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: HW SequencerHarry Wentland17-1/+7923
The HW Sequencer is responsible for programming sequences and other DCE specific operations. It is stateless and doesn't program HW by itself. It calls graphics objects (encoder, controller, etc) to do HW register and VBIOS command table programming SW Layer /===============================================================\ | Timing Asic | | Service Capability | | | | Display Display Adapter | | Path Capability Service | | Service | |---------------------------------------------------------------| | GPIO IRQ I2cAux HW BIOS | | Service Manager Sequencer Parser | | | | Connector Encoder Audio GPU Controller | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: Display PathHarry Wentland8-1/+2233
The core (anchor) of Display Path are Connector and Encoder – these actually define a Display Path. The rest of the objects are added and removed to/from Display Path on the fly – whenever DAL requires to setup or reset the video stream. SW Layer /===============================================================\ | Timing Asic | | Service Capability | | | | Display Display Adapter | | Path Capability Service | | Service | |---------------------------------------------------------------| | GPIO IRQ I2cAux BIOS | | Service Manager Parser | | | | Connector Encoder Audio GPU Controller | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: Display Capability ServiceHarry Wentland46-1/+16598
Reads, parses, caches an enumerates display (sink) capabilities. Uses I2cAux component to read capabilities from the receiver. While parsing the EDID, DCS will call Timing Service to get timing parameters for DMT and CVT EDID timings. SW Layer /===============================================================\ | Timing Asic | | Service Capability | | | | Display Adapter | | Capability Service | | Service | |---------------------------------------------------------------| | GPIO IRQ I2cAux BIOS | | Service Manager Parser | | | | Connector Encoder Audio GPU Controller | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: AudioHarry Wentland12-2/+4681
Responsible for programming the audio encoder in the display path. SW Layer /===============================================================\ | Timing Asic | | Service Capability | | | | Adapter | | Service | | | |---------------------------------------------------------------| | GPIO IRQ I2cAux BIOS | | Service Manager Parser | | | | Connector Encoder Audio GPU Controller | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: EncoderHarry Wentland40-1/+11312
Responsible for programming back-end of display path, such as DIG, UNIPHY, DP, DAC, and DVO. Supports: - DisplayPort (single stream) - HDMI - DVI - LVDS (through Travis encoder) SW Layer /===============================================================\ | Timing Asic | | Service Capability | | | | Adapter | | Service | | | |---------------------------------------------------------------| | GPIO IRQ I2cAux BIOS | | Service Manager Parser | | | | Connector Encoder GPU Controller | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: ControllerHarry Wentland83-2/+26063
Responsible for programming front-end of display path, such as DCP, LB, SCL, CRTC and FMT. SW Layer /===============================================================\ | Timing Asic | | Service Capability | | | | Adapter | | Service | | | |---------------------------------------------------------------| | GPIO IRQ I2cAux BIOS | | Service Manager Parser | | | | Connector GPU Controller | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: Timing ServiceHarry Wentland27-2/+6673
Implements industry timing standards and maintains list of timings for each display path. SW Layer /===============================================================\ | Timing Asic | | Service Capability | | | | Adapter | | Service | | | |---------------------------------------------------------------| | GPIO IRQ I2cAux BIOS | | Service Manager Parser | | | | Connector GPU | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: GPUHarry Wentland59-2/+16533
Encapsulates programming for HW blocks which are shared between display paths, such as clock sources. SW Layer /===============================================================\ | Asic | | Capability | | | | Adapter | | Service | | | |---------------------------------------------------------------| | GPIO IRQ I2cAux BIOS | | Service Manager Parser | | | | Connector GPU | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: ConnectorHarry Wentland6-1/+847
Represents a connector and supported signal types. SW Layer /===============================================================\ | Asic | | Capability | | | | Adapter | | Service | | | |---------------------------------------------------------------| | GPIO IRQ I2cAux BIOS | | Service Manager Parser | | | | Connector | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: IRQ ServiceHarry Wentland7-1/+749
Interface to set and ack DCE interrupts. SW Layer /===============================================================\ | Asic | | Capability | | | | Adapter | | Service | | | |---------------------------------------------------------------| | GPIO IRQ I2cAux BIOS | | Service Manager Parser | | | | | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: I2C Aux ManagerHarry Wentland25-1/+5553
Implements low-level communication layer over I2C and Aux lines using GPIO handles. SW Layer /===============================================================\ | Asic | | Capability | | | | Adapter | | Service | | | |---------------------------------------------------------------| | GPIO I2cAux BIOS | | Manager Parser | | | | | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: BIOS ParserHarry Wentland14-1/+9326
Wrapper to access Video BIOS command and data tables SW Layer /===============================================================\ | Asic | | Capability | | | | Adapter | | Service | | | |---------------------------------------------------------------| | GPIO BIOS | | Parser | | | | | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: Adapter ServiceHarry Wentland17-1/+5695
Provides information about ASIC features and capabilities. Also provides access to ASIC resources such as VBIOS, GPIO and I2cAux Manager SW Layer /===============================================================\ | Asic | | Capability | | | | Adapter | | Service | | | |---------------------------------------------------------------| | GPIO | | | | | | | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: GPIO (General Purpose IO)Harry Wentland42-1/+6110
Manages all DCE GPIO pins. The pins are represented as generic IO handles as well as handles dedicated for certain functions, such as DDC, HPD, and DVO. SW Layer /===============================================================\ | Asic | | Capability | | | | | | | | | |---------------------------------------------------------------| | GPIO | | | | | | | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: Asic CapabilitiesHarry Wentland7-1/+552
Add a generic way to manage display HW capabilities for different ASICs and implement it for Carrizo. This is the first patch for DAL. I've split DAL into patches by components for its initial submission. The diagram below shows the components divided by SW and HW layers and will be filled in by the patch series. SW Layer /===============================================================\ | Asic | | Capability | | | | | | | | | |---------------------------------------------------------------| | | | | | | | | \===============================================================/ HW Layer Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21amd/dal: Fixed point arithmeticHarry Wentland5-1/+1385
Arithmetic operations on real numbers represented as fixed-point numbers. Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21drm/amdgpu: Add DAL Basic Types and LoggerHarry Wentland30-1/+5371
Laying the groundwork for the AMD DAL display driver. This patch includes the basic services and defines basic types required by the display driver, such as: - ASIC register access - VBIOS access - Vector and flat_set data structures - Display signal types - ASIC versions and IDs - HW IDs - Logging functionality This patch adds Kconfig options to enable the DAL display driver. - DRM_AMD_DAL - DRM_AMD_DAL_VBIOS_PRESENT - DRM_AMD_DAL_DCE11_0 - DEBUG_KERNEL_DAL Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21drm/amdgpu: Define variable for amd path in MakefileHarry Wentland1-4/+6
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
2015-09-21drm/amd: Add IV SRC headerHarry Wentland1-0/+102
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Tim Writer <Tim.Writer@amd.com>
2015-09-21drm/amdgpu: use kmemdup rather than duplicating its implementationAndrzej Hajda1-3/+1
The patch was generated using fixed coccinelle semantic patch scripts/coccinelle/api/memdup.cocci [1]. [1]: http://permalink.gmane.org/gmane.linux.kernel/2014320 Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-09-21drm/amdgpu: fix UVD suspend and resume for VI APULeo Liu1-8/+12
User space passed the same handle before suspend and after resume, so we have remove the session and handle destroy, and keep the firmware untouched. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
2015-09-21drm/amdgpu: fix the UVD suspend sequence orderLeo Liu3-6/+6
Fixes suspend issues with UVD. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
2015-09-21drm/amdgpu: make UVD handle checking more strictLeo Liu1-27/+41
Invalid messages can crash the hw otherwise Ported from radeon commit a1b403da70e038ca6c6c6fe434d1d873546873a3 Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
2015-09-21drm/amdgpu: Disable UVD PGLeo Liu1-1/+2
This causes problems with multiple suspend/resume cycles. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
2015-09-21drm/amdgpu: more scheduler cleanups v2Christian König11-76/+87
Embed the scheduler into the ring structure instead of allocating it. Use the ring name directly instead of the id. v2: rebased, whitespace cleanup Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Chunming Zhou<david1.zhou@amd.com>
2015-09-21drm/amdgpu: cleanup fence queue init v2Christian König2-2/+2
Move the fence related stuff into amdgpu_fence.c v2: rework commit message, cause this is actually not a bug Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou<david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
2015-09-21drm/amdgpu: rename fence->scheduler to sched v2Christian König10-22/+22
Just to be consistent with the other members. v2: rename the ring member as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> (v1) Reviewed-by: Chunming Zhou<david1.zhou@amd.com>
2015-09-21drm/amdgpu: cleanup entity initChristian König3-19/+25
Reorder the fields and properly return the kfifo_alloc error code. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Chunming Zhou<david1.zhou@amd.com>
2015-09-21drm/amdgpu: refine the scheduler job type conversionJunwei Zhang3-4/+6
Use container_of rather than casting. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: David Zhou <david1.zhou@amd.com> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
2015-09-21drm/amdgpu: refine the job naming for amdgpu_job and amdgpu_sched_jobJunwei Zhang8-69/+71
Use consistent naming across functions. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: David Zhou <david1.zhou@amd.com> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
2015-09-21drm/amdgpu: use only one reservation object for each VM v2Christian König2-30/+9
Reduces the locking and fencing overhead. v2: add comment why we need the duplicates list in the GEM op. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-09-21drm/amdgpu: validate duplicates in the CS as wellChristian König1-14/+20
This allows for multiple BOs to have the same reservation object. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-09-21drm/amdgpu: export reservation_object from dmabuf to ttm (v2)Christian König24-52/+70
Adds an extra argument to amdgpu_bo_create, which is only used in amdgpu_prime.c. Port of radeon commit 831b6966a60fe72d85ae3576056b4e4e0775b112. v2: fix up kfd. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-09-21drm/amdgpu: fix overflow on 32bit systemsChristian König1-1/+1
mem->start is a long, so this can overflow on 32bit systems. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Cc: stable@vger.kernel.org
2015-09-21drm/amdgpu: remove process_job callback from the schedulerChristian König3-24/+7
Just free the resources immediately after submitting the job. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-09-21drm/amdgpu: move scheduler fence callback into fence v2Christian König2-11/+12
And call the processed callback directly after submitting the job. v2: split adding error handling into separate patch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-09-21drm/amdgpu: signal scheduler fence when hw submission fails v3Christian König1-0/+3
Otherwise the resource blocked by it will never be reclaimed. v2: add DRM_ERROR. v3: fix typo in commit message Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Chunming Zhou<david1.zhou@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-09-21drm/amdgpu: add tracepoint for scheduler (v2)Chunming Zhou2-1/+45
track sched job status like the length of job queue and hw job queue. v2: fix build after rebase Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2015-09-21drm/amdgpu: use write confirm for vm_flush()Christian König1-1/+2
Make sure the CP waits for the write to be confirmed before invalidating. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-09-21drm/amdgpu: execution barrier after fence v2Anatoli Antonovitch1-0/+12
Insert wait for reg mem after EOP to fix potential issue with vm context switch v2: move wait to vm_flush() use equal instead of greater than. Signed-off-by: Anatoli Antonovitch <anatoli.antonovitch@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-09-21drm/amdgpu: disable semaphores by defaultChristian König3-1/+21
Provide module parameter to enable them again. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-09-11Merge branch 'linux-4.3' of ↵Dave Airlie3-4/+5
git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next three nouveau regression fixes. * 'linux-4.3' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: drm/nouveau/device: enable c800 quirk for tecra w50 drm/nouveau/clk/gt215: Unbreak engine pausing for GT21x/MCP7x drm/nouveau/gr/nv04: fix big endian setting on gr context
2015-09-11drm/nouveau/device: enable c800 quirk for tecra w50Ben Skeggs1-0/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-09-11drm/nouveau/clk/gt215: Unbreak engine pausing for GT21x/MCP7xRoy Spliet1-1/+1
Typo that snuck in with commit 6979c6303a4abf263753cd9d577d79f05c6e8c47 Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Reported-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-14 15:23:50 +0000