drm/amdgpu: Add DAL Basic Types and Logger

Laying the groundwork for the AMD DAL display driver.
This patch includes the basic services and defines basic
types required by the display driver, such as:
- ASIC register access
- VBIOS access
- Vector and flat_set data structures
- Display signal types
- ASIC versions and IDs
- HW IDs
- Logging functionality

This patch adds Kconfig options to enable the DAL
display driver.
- DRM_AMD_DAL
- DRM_AMD_DAL_VBIOS_PRESENT
- DRM_AMD_DAL_DCE11_0
- DEBUG_KERNEL_DAL

Signed-off-by: Harry Wentland <harry.wentland@amd.com>

30 files changed, 5371 insertions, 1 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig
index b30fcfa4b1f2..052baf5b26ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/Kconfig
+++ b/drivers/gpu/drm/amd/amdgpu/Kconfig
@@ -15,3 +15,5 @@ config DRM_AMDGPU_USERPTR
 	help
 	  This option selects CONFIG_MMU_NOTIFIER if it isn't already
 	  selected to enabled full userptr support.
+
+source "drivers/gpu/drm/amd/dal/Kconfig"
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index e47ac467fd96..00804b482eb0 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -3,11 +3,16 @@
 # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
 
 FULL_AMD_PATH=drivers/gpu/drm/amd
+DAL_FOLDER_NAME=dal
+FULL_AMD_DAL_PATH = $(FULL_AMD_PATH)/$(DAL_FOLDER_NAME)
 
 ccflags-y := -Iinclude/drm -I$(FULL_AMD_PATH)/include/asic_reg \
 		-I$(FULL_AMD_PATH)/include \
 		-I$(FULL_AMD_PATH)/amdgpu \
-		-I$(FULL_AMD_PATH)/scheduler
+		-I$(FULL_AMD_PATH)/scheduler \
+		-I$(FULL_AMD_DAL_PATH) \
+		-I$(FULL_AMD_DAL_PATH)/include \
+		-I$(FULL_AMD_DAL_PATH)/amdgpu_dm
 
 amdgpu-y := amdgpu_drv.o
 
@@ -96,6 +101,14 @@ amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o
 amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o
 amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_mn.o
 
+ifneq ($(CONFIG_DRM_AMD_DAL),)
+
+RELATIVE_AMD_DAL_PATH = ../$(DAL_FOLDER_NAME)
+include $(FULL_AMD_DAL_PATH)/Makefile
+
+amdgpu-y += $(AMD_DAL_FILES)
+endif
+
 obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o
 
 CFLAGS_amdgpu_trace_points.o := -I$(src)
diff --git a/drivers/gpu/drm/amd/dal/Kconfig b/drivers/gpu/drm/amd/dal/Kconfig
new file mode 100644
index 000000000000..5834dacc34cb
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/Kconfig
@@ -0,0 +1,36 @@
+menu "Display Engine Configuration"
+	depends on DRM && DRM_AMDGPU
+
+config DRM_AMD_DAL
+        bool "AMD DAL - Enable new display engine
+        help
+          Choose this option if you want to use the new display engine
+          support for AMDGPU.
+
+config DRM_AMD_DAL_VBIOS_PRESENT
+        bool "Video Bios available on board"
+        depends on DRM_AMD_DAL
+        help
+         This option is needed to allow a full range of feature
+	 support when working on
+	 x86 platforms and there is a VBIOS
+	 present in the system
+
+config DRM_AMD_DAL_DCE11_0
+        bool "Carrizo family"
+        depends on DRM_AMD_DAL
+        help
+         Choose this option
+	 if you want to have
+	 CZ family
+	 for display engine
+
+config DEBUG_KERNEL_DAL
+        bool "Enable kgdb break in DAL"
+        depends on DRM_AMD_DAL
+        help
+         Choose this option
+         if you want to hit
+         kdgb_break in assert.
+
+endmenu
diff --git a/drivers/gpu/drm/amd/dal/Makefile b/drivers/gpu/drm/amd/dal/Makefile
new file mode 100644
index 000000000000..f1cc942c725f
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/Makefile
@@ -0,0 +1,14 @@
+#
+# Makefile for the DAL (Display Abstract Layer), which is a  sub-component
+# of the AMDGPU drm driver.
+# It provides the HW control for display related functionalities.
+
+AMDDALPATH = $(RELATIVE_AMD_DAL_PATH)
+
+subdir-ccflags-y += -I$(AMDDALPATH)/ -I$(AMDDALPATH)/include -DDAL_CZ_BRINGUP
+
+DAL_LIBS = amdgpu_dm basics
+
+AMD_DAL = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DAL_PATH)/,$(DAL_LIBS)))
+
+include $(AMD_DAL)
diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile b/drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile
new file mode 100644
index 000000000000..1709ec8dfb33
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for the 'dm' sub-component of DAL.
+# It provides the control and status of dm blocks.
+
+AMDGPUDM = amdgpu_dal_services.o
+
+AMDGPU_DM = $(addprefix $(AMDDALPATH)/amdgpu_dm/,$(AMDGPUDM))
+
+AMD_DAL_FILES += $(AMDGPU_DM)
diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
new file mode 100644
index 000000000000..9a4d38161412
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dal_services.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include <linux/string.h>
+#include <linux/acpi.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/amdgpu_drm.h>
+
+#include "amdgpu.h"
+#include "dal_services.h"
+
+long dal_get_pid(void)
+{
+	return current->pid;
+}
+
+long dal_get_tgid(void)
+{
+	return current->tgid;
+}
diff --git a/drivers/gpu/drm/amd/dal/basics/Makefile b/drivers/gpu/drm/amd/dal/basics/Makefile
new file mode 100644
index 000000000000..9f369873ae33
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/basics/Makefile
@@ -0,0 +1,12 @@
+#
+# Makefile for the 'utils' sub-component of DAL.
+# It provides the general basic services required by other DAL
+# subcomponents.
+
+CONTAINERS = vector.o flat_set.o
+BASICS = signal_types.o grph_object_id.o \
+	$(CONTAINERS) logger.o register_logger.o
+
+AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/basics/,$(BASICS))
+
+AMD_DAL_FILES += $(AMD_DAL_BASICS)
diff --git a/drivers/gpu/drm/amd/dal/basics/flat_set.c b/drivers/gpu/drm/amd/dal/basics/flat_set.c
new file mode 100644
index 000000000000..8c5d0f599848
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/basics/flat_set.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dal_services.h"
+#include "include/flat_set.h"
+
+bool dal_flat_set_construct(
+		struct flat_set *flat_set,
+		const struct flat_set_init_data *init_data)
+{
+	if (init_data == NULL ||
+		init_data->funcs.less_than == NULL ||
+		!dal_vector_construct(
+				&flat_set->vector,
+				init_data->capacity,
+				init_data->struct_size))
+		return false;
+
+	flat_set->funcs.less_than = init_data->funcs.less_than;
+	return true;
+}
+
+struct flat_set *dal_flat_set_create(
+		const struct flat_set_init_data *init_data)
+{
+	struct flat_set *flat_set;
+
+	if (init_data == NULL)
+		return NULL;
+
+	flat_set = dal_alloc(sizeof(struct flat_set));
+	if (flat_set == NULL)
+		return NULL;
+
+	if (!dal_flat_set_construct(flat_set, init_data)) {
+		dal_free(flat_set);
+		return NULL;
+	}
+
+	return flat_set;
+}
+
+void dal_flat_set_destruct(struct flat_set *set)
+{
+	dal_vector_destruct(&set->vector);
+}
+
+void dal_flat_set_destroy(struct flat_set **set)
+{
+	if (set == NULL || *set == NULL)
+		return;
+	dal_flat_set_destruct(*set);
+	dal_free(*set);
+	*set = NULL;
+}
+
+void *dal_flat_set_search(
+		const struct flat_set *flat_set,
+		const void *what,
+		uint32_t *index)
+{
+	uint32_t start = 0;
+	uint32_t end = flat_set->vector.count;
+	uint32_t middle = (start + end)/2;
+	void *elm;
+
+	if (flat_set->vector.count == 0 ||
+			flat_set->funcs.less_than(
+					what,
+					dal_vector_at_index(
+							&flat_set->vector,
+							start))) {
+		*index = 0;
+		return NULL;
+	}
+
+	if (flat_set->funcs.less_than(
+				dal_vector_at_index(&flat_set->vector, end - 1),
+				what)) {
+		*index = flat_set->vector.count;
+		return NULL;
+	}
+
+	do {
+		elm = dal_vector_at_index(&flat_set->vector, middle);
+		if (flat_set->funcs.less_than(what, elm))
+			end = middle;
+		else if (flat_set->funcs.less_than(elm, what))
+			start = middle + 1;
+		else {
+			*index = middle;
+			return elm;
+		}
+		middle = (start + end) / 2;
+	} while (start < middle);
+
+	elm = dal_vector_at_index(&flat_set->vector, middle);
+	if (flat_set->funcs.less_than(what, elm))
+		*index = start;
+	else if (flat_set->funcs.less_than(elm, what))
+		*index = end;
+	else {
+		*index = start;
+		return elm;
+	}
+
+	return NULL;
+}
+
+void *dal_flat_set_insert(
+		struct flat_set *flat_set,
+		const void *what)
+{
+	uint32_t where;
+	void *found_elm = dal_flat_set_search(flat_set, what, &where);
+
+	if (found_elm)
+		/*already there, not inserting*/
+		return found_elm;
+	if (dal_vector_insert_at(&flat_set->vector, what, where))
+		return dal_vector_at_index(&flat_set->vector, where);
+	return NULL;
+}
+
+uint32_t dal_flat_set_get_count(const struct flat_set *flat_set)
+{
+	return dal_vector_get_count(&flat_set->vector);
+}
+
+void *dal_flat_set_at_index(const struct flat_set *fs, uint32_t index)
+{
+	return dal_vector_at_index(&fs->vector, index);
+}
+
+bool dal_flat_set_remove_at_index(struct flat_set *fs, uint32_t index)
+{
+	return dal_vector_remove_at_index(&fs->vector, index);
+}
+
+uint32_t dal_flat_set_capacity(const struct flat_set *fs)
+{
+	return dal_vector_capacity(&fs->vector);
+}
+
+bool dal_flat_set_reserve(struct flat_set *fs, uint32_t capacity)
+{
+	return dal_vector_reserve(&fs->vector, capacity);
+}
+
+void dal_flat_set_clear(struct flat_set *fs)
+{
+	dal_vector_clear(&fs->vector);
+}
diff --git a/drivers/gpu/drm/amd/dal/basics/grph_object_id.c b/drivers/gpu/drm/amd/dal/basics/grph_object_id.c
new file mode 100644
index 000000000000..14962297ccb9
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/basics/grph_object_id.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dal_services.h"
+
+#include "include/grph_object_id.h"
+
+bool dal_graphics_object_id_is_valid(struct graphics_object_id id)
+{
+	bool rc = true;
+
+	switch (id.type) {
+	case OBJECT_TYPE_UNKNOWN:
+		rc = false;
+		break;
+	case OBJECT_TYPE_GPU:
+	case OBJECT_TYPE_ENGINE:
+		/* do NOT check for id.id == 0 */
+		if (id.enum_id == ENUM_ID_UNKNOWN)
+			rc = false;
+		break;
+	default:
+		if (id.id == 0 || id.enum_id == ENUM_ID_UNKNOWN)
+			rc = false;
+		break;
+	}
+
+	return rc;
+}
+
+bool dal_graphics_object_id_is_equal(
+	struct graphics_object_id id1,
+	struct graphics_object_id id2)
+{
+	if (false == dal_graphics_object_id_is_valid(id1)) {
+		dal_output_to_console(
+		"%s: Warning: comparing invalid object 'id1'!\n", __func__);
+		return false;
+	}
+
+	if (false == dal_graphics_object_id_is_valid(id2)) {
+		dal_output_to_console(
+		"%s: Warning: comparing invalid object 'id2'!\n", __func__);
+		return false;
+	}
+
+	if (id1.id == id2.id && id1.enum_id == id2.enum_id
+		&& id1.type == id2.type)
+		return true;
+
+	return false;
+}
+
+/* Based on internal data members memory layout */
+uint32_t dal_graphics_object_id_to_uint(struct graphics_object_id id)
+{
+	uint32_t object_id = 0;
+
+	object_id = id.id + (id.enum_id << 0x8) + (id.type << 0xc);
+	return object_id;
+}
+
+/*
+ * ******* get specific ID - internal safe cast into specific type *******
+ */
+
+enum controller_id dal_graphics_object_id_get_controller_id(
+	struct graphics_object_id id)
+{
+	if (id.type == OBJECT_TYPE_CONTROLLER)
+		return id.id;
+	return CONTROLLER_ID_UNDEFINED;
+}
+
+enum clock_source_id dal_graphics_object_id_get_clock_source_id(
+	struct graphics_object_id id)
+{
+	if (id.type == OBJECT_TYPE_CLOCK_SOURCE)
+		return id.id;
+	return CLOCK_SOURCE_ID_UNDEFINED;
+}
+
+enum encoder_id dal_graphics_object_id_get_encoder_id(
+	struct graphics_object_id id)
+{
+	if (id.type == OBJECT_TYPE_ENCODER)
+		return id.id;
+	return ENCODER_ID_UNKNOWN;
+}
+
+enum connector_id dal_graphics_object_id_get_connector_id(
+	struct graphics_object_id id)
+{
+	if (id.type == OBJECT_TYPE_CONNECTOR)
+		return id.id;
+	return CONNECTOR_ID_UNKNOWN;
+}
+
+enum audio_id dal_graphics_object_id_get_audio_id(struct graphics_object_id id)
+{
+	if (id.type == OBJECT_TYPE_AUDIO)
+		return id.id;
+	return AUDIO_ID_UNKNOWN;
+}
+
+enum engine_id dal_graphics_object_id_get_engine_id(
+	struct graphics_object_id id)
+{
+	if (id.type == OBJECT_TYPE_ENGINE)
+		return id.id;
+	return ENGINE_ID_UNKNOWN;
+}
diff --git a/drivers/gpu/drm/amd/dal/basics/logger.c b/drivers/gpu/drm/amd/dal/basics/logger.c
new file mode 100644
index 000000000000..e52dd3d46559
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/basics/logger.c
@@ -0,0 +1,923 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include <stdarg.h>
+#include "dal_services.h"
+#include "include/dal_types.h"
+#include "include/logger_interface.h"
+#include "logger.h"
+
+/* TODO: for now - empty, use DRM defines from dal services.
+		Need to define appropriate levels of prints, and implement
+		this component
+void dal_log(const char *format, ...)
+{
+}
+*/
+
+/* ----------- Logging Major/Minor names ------------ */
+
+#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
+
+static const struct log_minor_info component_minor_info_tbl[] = {
+	{LOG_MINOR_COMPONENT_LINK_SERVICE, "LS"},
+	{LOG_MINOR_COMPONENT_DAL_INTERFACE, "DalIf"},
+	{LOG_MINOR_COMPONENT_HWSS, "HWSS"},
+	{LOG_MINOR_COMPONENT_ADAPTER_SERVICE, "AS"},
+	{LOG_MINOR_COMPONENT_DISPLAY_SERVICE, "DS"},
+	{LOG_MINOR_COMPONENT_TOPOLOGY_MANAGER, "TM"},
+	{LOG_MINOR_COMPONENT_ENCODER, "Encoder"},
+	{LOG_MINOR_COMPONENT_I2C_AUX, "I2cAux"},
+	{LOG_MINOR_COMPONENT_AUDIO, "Audio"},
+	{LOG_MINOR_COMPONENT_DISPLAY_CAPABILITY_SERVICE, "Dcs"},
+	{LOG_MINOR_COMPONENT_DMCU, "Dmcu"},
+	{LOG_MINOR_COMPONENT_GPU, "GPU"},
+	{LOG_MINOR_COMPONENT_CONTROLLER, "Cntrlr"},
+	{LOG_MINOR_COMPONENT_ISR, "ISR"},
+	{LOG_MINOR_COMPONENT_BIOS, "BIOS"},
+	{LOG_MINOR_COMPONENT_IRQ_SERVICE, "IRQ SERVICE"}
+};
+
+static const struct log_minor_info hw_trace_minor_info_tbl[] = {
+	{LOG_MINOR_HW_TRACE_MST, "Mst" },
+	{LOG_MINOR_HW_TRACE_TRAVIS, "Travis" },
+	{LOG_MINOR_HW_TRACE_HOTPLUG, "Hotplug" },
+	{LOG_MINOR_HW_TRACE_LINK_TRAINING, "LinkTraining" },
+	{LOG_MINOR_HW_TRACE_SET_MODE, "SetMode" },
+	{LOG_MINOR_HW_TRACE_RESUME_S3, "ResumeS3" },
+	{LOG_MINOR_HW_TRACE_RESUME_S4, "ResumeS4" },
+	{LOG_MINOR_HW_TRACE_BOOTUP, "BootUp" },
+	{LOG_MINOR_HW_TRACE_AUDIO, "Audio"},
+	{LOG_MINOR_HW_TRACE_HPD_IRQ, "HpdIrq" },
+	{LOG_MINOR_HW_TRACE_INTERRUPT, "Interrupt" },
+	{LOG_MINOR_HW_TRACE_MPO, "Planes" },
+};
+
+static const struct log_minor_info mst_minor_info_tbl[] = {
+	{LOG_MINOR_MST_IRQ_HPD_RX, "IrqHpdRx"},
+	{LOG_MINOR_MST_IRQ_TIMER, "IrqTimer"},
+	{LOG_MINOR_MST_NATIVE_AUX, "NativeAux"},
+	{LOG_MINOR_MST_SIDEBAND_MSG, "SB"},
+	{LOG_MINOR_MST_MSG_TRANSACTION, "MT"},
+	{LOG_MINOR_MST_SIDEBAND_MSG_PARSED, "SB Parsed"},
+	{LOG_MINOR_MST_MSG_TRANSACTION_PARSED, "MT Parsed"},
+	{LOG_MINOR_MST_AUX_MSG_DPCD_ACCESS, "AuxMsgDpcdAccess"},
+	{LOG_MINOR_MST_PROGRAMMING, "Programming"},
+	{LOG_MINOR_MST_TOPOLOGY_DISCOVERY, "TopologyDiscovery"},
+	{LOG_MINOR_MST_CONVERTER_CAPS, "ConverterCaps"},
+};
+
+static const struct log_minor_info dcs_minor_info_tbl[] = {
+	{LOG_MINOR_DCS_EDID_EMULATOR, "EdidEmul"},
+	{LOG_MINOR_DCS_DONGLE_DETECTION, "DongleDetect"},
+};
+
+static const struct log_minor_info dcp_minor_info_tbl[] = {
+	{ LOG_MINOR_DCP_GAMMA_GRPH, "GammaGrph"},
+	{ LOG_MINOR_DCP_GAMMA_OVL, "GammaOvl"},
+	{ LOG_MINOR_DCP_CSC_GRPH, "CscGrph"},
+	{ LOG_MINOR_DCP_CSC_OVL, "CscOvl"},
+	{ LOG_MINOR_DCP_SCALER, "Scaler"},
+	{ LOG_MINOR_DCP_SCALER_TABLES, "ScalerTables"},
+};
+
+static const struct log_minor_info bios_minor_info_tbl[] = {
+	{LOG_MINOR_BIOS_CMD_TABLE, "CmdTbl"},
+};
+
+static const struct log_minor_info reg_minor_info_tbl[] = {
+	{LOG_MINOR_REGISTER_INDEX, "Index"},
+};
+
+static const struct log_minor_info info_packet_minor_info_tbl[] = {
+	{LOG_MINOR_INFO_PACKETS_HDMI, "Hdmi"},
+};
+
+
+static const struct log_minor_info dsat_minor_info_tbl[] = {
+	{LOG_MINOR_DSAT_LOGGER, "Logger"},
+	{LOG_MINOR_DSAT_EDID_OVERRIDE, "EDID_Override"},
+};
+
+static const struct log_minor_info ec_minor_info_tbl[] = {
+	{LOG_MINOR_EC_PPLIB_NOTIFY, "PPLib_Notify" }, /* PPLib notifies DAL */
+	{LOG_MINOR_EC_PPLIB_QUERY, "PPLib_Query" } /* DAL requested info from
+							PPLib */
+};
+
+static const struct log_minor_info bwm_minor_info_tbl[] = {
+	{LOG_MINOR_BWM_MODE_VALIDATION, "ModeValidation"},
+	{LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS, "Req_Bandw_Calcs"}
+};
+
+static const struct log_minor_info mode_enum_minor_info_tbl[] = {
+	{LOG_MINOR_MODE_ENUM_BEST_VIEW_CANDIDATES, "BestviewCandidates"},
+	{LOG_MINOR_MODE_ENUM_VIEW_SOLUTION, "ViewSolution"},
+	{LOG_MINOR_MODE_ENUM_TS_LIST_BUILD, "TsListBuild"},
+	{LOG_MINOR_MODE_ENUM_TS_LIST, "TsList"},
+	{LOG_MINOR_MODE_ENUM_MASTER_VIEW_LIST, "MasterViewList"},
+	{LOG_MINOR_MODE_ENUM_MASTER_VIEW_LIST_UPDATE, "MasterViewListUpdate"},
+};
+
+static const struct log_minor_info i2caux_minor_info_tbl[] = {
+	{LOG_MINOR_I2C_AUX_LOG, "Aux Log"},
+	{LOG_MINOR_I2C_AUX_AUX_TIMESTAMP, "Aux Timestamp"},
+};
+
+static const struct log_minor_info line_buffer_minor_info_tbl[] = {
+	{LOG_MINOR_LINE_BUFFER_POWERGATING, "PowerGating"}
+};
+
+static const struct log_minor_info hwss_minor_info_tbl[] = {
+	{LOG_MINOR_HWSS_TAPS_VALIDATION, "HWSS Taps"}
+};
+
+static const struct log_minor_info optimization_minor_info_tbl[] = {
+	{LOG_MINOR_OPTMZ_GENERAL, "General Optimizations"},
+	{LOG_MINOR_OPTMZ_DO_NOT_TURN_OFF_VCC_DURING_SET_MODE,
+		"Skip Vcc Off During Set Mode"}
+};
+
+static const struct log_minor_info perf_measure_minor_info_tbl[] = {
+	{LOG_MINOR_PERF_MEASURE_GENERAL, "General Performance Measurement"},
+	{LOG_MINOR_PERF_MEASURE_HEAP_MEMORY, "Heap Memory Management"}
+};
+
+static const struct log_minor_info sync_minor_info_tbl[] = {
+	{LOG_MINOR_SYNC_HW_CLOCK_ADJUST, "Pixel Rate Tune-up"},
+};
+
+static const struct log_minor_info backlight_minor_info_tbl[] = {
+	{LOG_MINOR_BACKLIGHT_BRIGHTESS_CAPS, "Backlight Caps"},
+	{LOG_MINOR_BACKLIGHT_DMCU_DELTALUT, "DMCU Backlight Delta LUT"},
+	{LOG_MINOR_BACKLIGHT_DMCU_BUILD_DELTALUT,
+		"Build DMCU Backlight Delta LUT"},
+	{LOG_MINOR_BACKLIGHT_INTERFACE, "Backlight Dal Interface"},
+	{LOG_MINOR_BACKLIGHT_LID, "Lid status"}
+};
+
+
+static const struct log_minor_info override_feature_minor_info_tbl[] = {
+	{LOG_MINOR_FEATURE_OVERRIDE, "overriden feature"},
+};
+
+static const struct log_minor_info tm_minor_info_tbl[] = {
+	{LOG_MINOR_TM_INFO, "INFO"},
+	{LOG_MINOR_TM_IFACE_TRACE, "IFACE_TRACE"},
+	{LOG_MINOR_TM_RESOURCES, "RESOURCES"},
+	{LOG_MINOR_TM_ENCODER_CTL, "ENCODER_CTL"},
+	{LOG_MINOR_TM_ENG_ASN, "ENG_ASN"},
+	{LOG_MINOR_TM_CONTROLLER_ASN, "CONTROLLER_ASN"},
+	{LOG_MINOR_TM_PWR_GATING, "PWR_GATING"},
+	{LOG_MINOR_TM_BUILD_DSP_PATH, "BUILD_PATH"},
+	{LOG_MINOR_TM_DISPLAY_DETECT, "DISPLAY_DETECT"},
+	{LOG_MINOR_TM_LINK_SRV,	"LINK_SRV"},
+	{LOG_MINOR_TM_NOT_IMPLEMENTED, "NOT_IMPL"},
+	{LOG_MINOR_TM_COFUNC_PATH, "COFUNC_PATH"}
+};
+
+static const struct log_minor_info ds_minor_info_tbl[] = {
+	{LOG_MINOR_DS_MODE_SETTING, "Mode_Setting"},
+};
+
+
+struct log_major_mask_info {
+	struct log_major_info major_info;
+	uint32_t default_mask;
+	const struct log_minor_info *minor_tbl;
+	uint32_t tbl_element_cnt;
+};
+
+/* A mask for each Major.
+ * Use a mask or zero. */
+#define LG_ERR_MSK 0xffffffff
+#define LG_WRN_MSK 0xffffffff
+#define LG_TM_MSK (1 << LOG_MINOR_TM_INFO)
+#define LG_FO_MSK (1 << LOG_MINOR_FEATURE_OVERRIDE)
+#define LG_EC_MSK ((1 << LOG_MINOR_EC_PPLIB_NOTIFY) | \
+			(1 << LOG_MINOR_EC_PPLIB_QUERY))
+#define LG_DSAT_MSK (1 << LOG_MINOR_DSAT_EDID_OVERRIDE)
+
+/* IFT - InterFaceTrace */
+#define LG_IFT_MSK (1 << LOG_MINOR_COMPONENT_DAL_INTERFACE)
+
+
+#define LG_HW_TR_AUD_MSK (1 << LOG_MINOR_HW_TRACE_AUDIO)
+#define LG_HW_TR_INTERRUPT_MSK (1 << LOG_MINOR_HW_TRACE_INTERRUPT)
+#define LG_HW_TR_PLANES_MSK (1 << LOG_MINOR_HW_TRACE_MPO)
+
+
+static const struct log_major_mask_info log_major_mask_info_tbl[] = {
+	/* LogMajor                  major name       default     MinorTble                    tblElementCnt */
+	{{LOG_MAJOR_ERROR,           "Error"       }, LG_ERR_MSK, component_minor_info_tbl,    NUM_ELEMENTS(component_minor_info_tbl)},
+	{{LOG_MAJOR_WARNING,         "Warning"     }, LG_WRN_MSK, component_minor_info_tbl,    NUM_ELEMENTS(component_minor_info_tbl)},
+	{{LOG_MAJOR_INTERFACE_TRACE, "IfTrace"     }, 0,          component_minor_info_tbl,    NUM_ELEMENTS(component_minor_info_tbl)},
+	{{LOG_MAJOR_HW_TRACE,        "HwTrace"     }, 0,          hw_trace_minor_info_tbl,     NUM_ELEMENTS(hw_trace_minor_info_tbl)},
+	{{LOG_MAJOR_MST,             "MST"         }, 0,          mst_minor_info_tbl,          NUM_ELEMENTS(mst_minor_info_tbl)},
+	{{LOG_MAJOR_DCS,             "DCS"         }, 0,          dcs_minor_info_tbl,          NUM_ELEMENTS(dcs_minor_info_tbl)},
+	{{LOG_MAJOR_DCP,             "DCP"         }, 0,          dcp_minor_info_tbl,          NUM_ELEMENTS(dcp_minor_info_tbl)},
+	{{LOG_MAJOR_BIOS,            "Bios"        }, 0,          bios_minor_info_tbl,         NUM_ELEMENTS(bios_minor_info_tbl)},
+	{{LOG_MAJOR_REGISTER,        "Register"    }, 0,          reg_minor_info_tbl,          NUM_ELEMENTS(reg_minor_info_tbl)},
+	{{LOG_MAJOR_INFO_PACKETS,    "InfoPacket"  }, 0,          info_packet_minor_info_tbl,  NUM_ELEMENTS(info_packet_minor_info_tbl)},
+	{{LOG_MAJOR_DSAT,            "DSAT"        }, 0,	  dsat_minor_info_tbl,         NUM_ELEMENTS(dsat_minor_info_tbl)},
+	{{LOG_MAJOR_EC,              "EC"          }, LG_EC_MSK,  ec_minor_info_tbl,           NUM_ELEMENTS(ec_minor_info_tbl)},
+	{{LOG_MAJOR_BWM,             "BWM"         }, 0,          bwm_minor_info_tbl,          NUM_ELEMENTS(bwm_minor_info_tbl)},
+	{{LOG_MAJOR_MODE_ENUM,       "ModeEnum"    }, 0,          mode_enum_minor_info_tbl,    NUM_ELEMENTS(mode_enum_minor_info_tbl)},
+	{{LOG_MAJOR_I2C_AUX,         "I2cAux"      }, 0,	  i2caux_minor_info_tbl,       NUM_ELEMENTS(i2caux_minor_info_tbl)},
+	{{LOG_MAJOR_LINE_BUFFER,     "LineBuffer"  }, 0,          line_buffer_minor_info_tbl,  NUM_ELEMENTS(line_buffer_minor_info_tbl)},
+	{{LOG_MAJOR_HWSS,            "HWSS"        }, 0,          hwss_minor_info_tbl,         NUM_ELEMENTS(hwss_minor_info_tbl)},
+	{{LOG_MAJOR_OPTIMIZATION,    "Optimization"}, 0,          optimization_minor_info_tbl, NUM_ELEMENTS(optimization_minor_info_tbl)},
+	{{LOG_MAJOR_PERF_MEASURE,    "PerfMeasure" }, 0,          perf_measure_minor_info_tbl, NUM_ELEMENTS(perf_measure_minor_info_tbl)},
+	{{LOG_MAJOR_SYNC,            "Sync"        }, 0,          sync_minor_info_tbl,         NUM_ELEMENTS(sync_minor_info_tbl)},
+	{{LOG_MAJOR_BACKLIGHT,       "Backlight"   }, 0,          backlight_minor_info_tbl,    NUM_ELEMENTS(backlight_minor_info_tbl)},
+	{{LOG_MAJOR_INTERRUPTS,      "Interrupts"  }, 0,          component_minor_info_tbl,    NUM_ELEMENTS(component_minor_info_tbl)},
+	{{LOG_MAJOR_TM,              "TM"          }, LG_TM_MSK,  tm_minor_info_tbl,           NUM_ELEMENTS(tm_minor_info_tbl)},
+	{{LOG_MAJOR_DISPLAY_SERVICE, "DS"          }, 0,          ds_minor_info_tbl,           NUM_ELEMENTS(ds_minor_info_tbl)},
+	{{LOG_MAJOR_FEATURE_OVERRIDE, "FeatureOverride" }, LG_FO_MSK, override_feature_minor_info_tbl, NUM_ELEMENTS(override_feature_minor_info_tbl)},
+
+};
+
+/* ----------- Object init and destruction ----------- */
+static bool construct(struct dal_logger *logger)
+{
+	uint32_t i;
+	/* malloc buffer and init offsets */
+
+	logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE;
+	logger->log_buffer = (char *)dal_alloc(logger->log_buffer_size *
+					sizeof(char));
+
+	if (!logger->log_buffer)
+		return false;
+
+	/* todo: Fill buffer with \0 if not done by dal_alloc */
+
+	/* Initialize both offsets to start of buffer (empty) */
+	logger->buffer_read_offset = 0;
+	logger->buffer_write_offset = 0;
+
+	logger->write_wrap_count = 0;
+	logger->read_wrap_count = 0;
+	logger->open_count = 0;
+
+	logger->flags.bits.ENABLE_CONSOLE = 1;
+	logger->flags.bits.ENABLE_BUFFER = 0;
+
+	/* malloc and init minor mask array */
+	logger->log_enable_mask_minors =
+			(uint32_t *)dal_alloc(
+					NUM_ELEMENTS(log_major_mask_info_tbl)
+					* sizeof(uint32_t));
+	if (!logger->log_enable_mask_minors)
+		return false;
+
+
+	/* Set default values for mask */
+	for (i = 0; i < NUM_ELEMENTS(log_major_mask_info_tbl); i++) {
+
+		uint32_t dflt_mask = log_major_mask_info_tbl[i].default_mask;
+
+		logger->log_enable_mask_minors[i] = dflt_mask;
+	}
+
+	return true;
+}
+
+static void destruct(struct dal_logger *logger)
+{
+	if (logger->log_buffer) {
+		dal_free(logger->log_buffer);
+		logger->log_buffer = NULL;
+	}
+
+	if (logger->log_enable_mask_minors) {
+		dal_free(logger->log_enable_mask_minors);
+		logger->log_enable_mask_minors = NULL;
+	}
+}
+
+struct dal_logger *dal_logger_create(void)
+{
+	/* malloc struct */
+	struct dal_logger *logger = dal_alloc(sizeof(struct dal_logger));
+
+	if (!logger)
+		return NULL;
+	if (!construct(logger)) {
+		dal_free(logger);
+		return NULL;
+	}
+
+	return logger;
+}
+
+uint32_t dal_logger_destroy(struct dal_logger **logger)
+{
+	if (logger == NULL || *logger == NULL)
+		return 1;
+	destruct(*logger);
+	dal_free(*logger);
+	*logger = NULL;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------ */
+
+static void lock(struct dal_logger *logger)
+{
+	/* Todo: lock mutex? */
+}
+
+static void unlock(struct dal_logger *logger)
+{
+	/* Todo: unlock mutex */
+}
+
+bool dal_logger_should_log(
+	struct dal_logger *logger,
+	enum log_major major,
+	enum log_minor minor)
+{
+	if (major < LOG_MAJOR_COUNT) {
+
+		uint32_t minor_mask = logger->log_enable_mask_minors[major];
+
+		if ((minor_mask & (1 << minor)) != 0)
+			return true;
+	}
+
+	return false;
+}
+
+static void log_to_debug_console(struct log_entry *entry)
+{
+	struct dal_logger *logger = entry->logger;
+
+	if (logger->flags.bits.ENABLE_CONSOLE == 0)
+		return;
+
+	switch (entry->major) {
+	case LOG_MAJOR_ERROR:
+		dal_error("%s", entry->buf);
+		break;
+	default:
+		dal_output_to_console("%s", entry->buf);
+		break;
+	}
+}
+
+/* Print everything unread existing in log_buffer to debug console*/
+static void flush_to_debug_console(struct dal_logger *logger)
+{
+	int i = logger->buffer_read_offset;
+	char *string_start = &logger->log_buffer[i];
+
+	dal_output_to_console(
+		"---------------- FLUSHING LOG BUFFER ----------------\n");
+	while (i < logger->buffer_write_offset)	{
+
+		if (logger->log_buffer[i] == '\0') {
+			dal_output_to_console("%s", string_start);
+			string_start = (char *)logger->log_buffer + i + 1;
+		}
+		i++;
+	}
+	dal_output_to_console(
+		"-------------- END FLUSHING LOG BUFFER --------------\n\n");
+}
+
+static void log_to_internal_buffer(struct log_entry *entry)
+{
+
+	uint32_t size = entry->buf_offset;
+	struct dal_logger *logger = entry->logger;
+
+	if (logger->flags.bits.ENABLE_BUFFER == 0)
+		return;
+
+	if (logger->log_buffer == NULL)
+		return;
+
+	if (size > 0 && size < logger->log_buffer_size) {
+
+		int total_free_space = 0;
+		int space_before_wrap = 0;
+
+		if (logger->buffer_write_offset > logger->buffer_read_offset) {
+			total_free_space = logger->log_buffer_size -
+					logger->buffer_write_offset +
+					logger->buffer_read_offset;
+			space_before_wrap = logger->log_buffer_size -
+					logger->buffer_write_offset;
+		} else if (logger->buffer_write_offset <
+				logger->buffer_read_offset) {
+			total_free_space = logger->log_buffer_size -
+					logger->buffer_read_offset +
+					logger->buffer_write_offset;
+			space_before_wrap = total_free_space;
+		} else if (logger->write_wrap_count !=
+				logger->read_wrap_count) {
+			/* Buffer is completely full already */
+			total_free_space = 0;
+			space_before_wrap = 0;
+		} else {
+			/* Buffer is empty, start writing at beginning */
+			total_free_space = logger->log_buffer_size;
+			space_before_wrap = logger->log_buffer_size;
+			logger->buffer_write_offset = 0;
+			logger->buffer_read_offset = 0;
+		}
+
+
+
+
+		if (space_before_wrap > size) {
+			/* No wrap around, copy 'size' bytes
+			 * from 'entry->buf' to 'log_buffer'
+			 */
+			dal_memmove(logger->log_buffer +
+					logger->buffer_write_offset,
+					entry->buf, size);
+			logger->buffer_write_offset += size;
+
+		} else if (total_free_space > size) {
+			/* We have enough room without flushing,
+			 * but need to wrap around */
+
+			int space_after_wrap = total_free_space -
+					space_before_wrap;
+
+			dal_memmove(logger->log_buffer +
+					logger->buffer_write_offset,
+					entry->buf, space_before_wrap);
+			dal_memmove(logger->log_buffer, entry->buf +
+					space_before_wrap, space_after_wrap);
+
+			logger->buffer_write_offset = space_after_wrap;
+			logger->write_wrap_count++;
+
+		} else {
+			/* Not enough room remaining, we should flush
+			 * existing logs */
+
+			/* Flush existing unread logs to console */
+			flush_to_debug_console(logger);
+
+			/* Start writing to beginning of buffer */
+			dal_memmove(logger->log_buffer, entry->buf, size);
+			logger->buffer_write_offset = size;
+			logger->buffer_read_offset = 0;
+		}
+
+	}
+
+	unlock(logger);
+}
+
+
+static void log_timestamp(struct log_entry *entry)
+{
+	dal_logger_append(entry, "00:00:00 ");
+}
+
+static void log_major_minor(struct log_entry *entry)
+{
+	uint32_t i;
+	enum log_major major = entry->major;
+	enum log_minor minor = entry->minor;
+
+	for (i = 0; i < NUM_ELEMENTS(log_major_mask_info_tbl); i++) {
+
+		const struct log_major_mask_info *maj_mask_info =
+				&log_major_mask_info_tbl[i];
+
+		if (maj_mask_info->major_info.major == major) {
+
+			dal_logger_append(entry, "[%s_",
+					maj_mask_info->major_info.major_name);
+
+			if (maj_mask_info->minor_tbl != NULL) {
+				uint32_t j;
+
+				for (j = 0; j < maj_mask_info->tbl_element_cnt; j++) {
+
+					const struct log_minor_info *min_info = &maj_mask_info->minor_tbl[j];
+
+					if (min_info->minor == minor)
+						dal_logger_append(entry, "%s]\t", min_info->minor_name);
+				}
+			}
+
+			break;
+		}
+	}
+}
+
+static void log_heading(struct log_entry *entry,
+			enum log_major major,
+			enum log_minor minor)
+{
+	log_timestamp(entry);
+	log_major_minor(entry);
+}
+
+
+static void append_entry(
+		struct log_entry *entry,
+		char *buffer,
+		uint32_t buf_size)
+{
+	if (!entry->buf ||
+		entry->buf_offset + buf_size > entry->max_buf_bytes
+	) {
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+
+	/* Todo: check if off by 1 byte due to \0 anywhere */
+	dal_memmove(entry->buf + entry->buf_offset, buffer, buf_size);
+	entry->buf_offset += buf_size;
+}
+
+/* ------------------------------------------------------------------------ */
+
+/* Warning: Be careful that 'msg' is null terminated and the total size is
+ * less than DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE (256) including '\0'
+ */
+void dal_logger_write(
+	struct dal_logger *logger,
+	enum log_major major,
+	enum log_minor minor,
+	const char *msg,
+	...)
+{
+
+	if (logger && dal_logger_should_log(logger, major, minor)) {
+
+		uint32_t size;
+		va_list args;
+		char buffer[DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE];
+		struct log_entry entry;
+
+		va_start(args, msg);
+		dal_logger_open(logger, &entry, major, minor);
+
+
+		size = dal_log_to_buffer(
+			buffer, DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE, msg, args);
+
+		if (size > 0 && size <
+				DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE - 1) {
+
+			if (buffer[size] == '\0')
+				size++; /* Add one for null terminator */
+
+			/* Concatenate onto end of entry buffer */
+			append_entry(&entry, buffer, size);
+		} else {
+			append_entry(&entry, "LOG_ERROR\n", 12);
+		}
+
+		dal_logger_close(&entry);
+		va_end(args);
+
+	}
+}
+
+
+/* Same as dal_logger_write, except without open() and close(), which must
+ * be done separately.
+ */
+void dal_logger_append(
+	struct log_entry *entry,
+	const char *msg,
+	...)
+{
+	struct dal_logger *logger;
+
+	if (!entry) {
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+
+	logger = entry->logger;
+
+	if (logger && logger->open_count > 0 &&
+		dal_logger_should_log(logger, entry->major, entry->minor)) {
+
+		uint32_t size;
+		va_list args;
+		char buffer[DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE];
+
+		va_start(args, msg);
+
+		size = dal_log_to_buffer(
+			buffer, DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE, msg, args);
+		append_entry(entry, buffer, size);
+
+		va_end(args);
+	}
+}
+
+
+uint32_t dal_logger_read(
+	struct dal_logger *logger, /* <[in] */
+	uint32_t output_buffer_size, /* <[in] */
+	char *output_buffer, /* >[out] */
+	uint32_t *bytes_read, /* >[out] */
+	bool single_line)
+{
+	uint32_t bytes_remaining = 0;
+	uint32_t bytes_read_count = 0;
+	bool keep_reading = true;
+
+	if (!logger || output_buffer == NULL || output_buffer_size == 0) {
+		BREAK_TO_DEBUGGER();
+		*bytes_read = 0;
+		return 0;
+	}
+
+	lock(logger);
+
+	/* Read until null terminator (if single_line==true,
+	 *  max buffer size, or until we've read everything new
+	 */
+
+	do {
+		char cur;
+
+		/* Stop when we've read everything */
+		if (logger->buffer_read_offset ==
+			logger->buffer_write_offset) {
+
+			break;
+		}
+
+		cur = logger->log_buffer[logger->buffer_read_offset];
+		logger->buffer_read_offset++;
+
+		/* Wrap read pointer if at end */
+		if (logger->buffer_read_offset == logger->log_buffer_size) {
+
+			logger->buffer_read_offset = 0;
+			logger->read_wrap_count++;
+		}
+
+		/* Don't send null terminators to buffer */
+		if (cur != '\0') {
+			output_buffer[bytes_read_count] = cur;
+			bytes_read_count++;
+		} else if (single_line) {
+			keep_reading = false;
+		}
+
+	} while (bytes_read_count <= output_buffer_size && keep_reading);
+
+	/* We assume that reading can never be ahead of writing */
+	if (logger->write_wrap_count > logger->read_wrap_count) {
+		bytes_remaining = logger->log_buffer_size -
+			logger->buffer_read_offset +
+			logger->buffer_write_offset;
+	} else {
+		bytes_remaining = logger->buffer_write_offset -
+				logger->buffer_read_offset;
+	}
+
+	/* reset write/read wrap count to 0 if we've read everything */
+	if (bytes_remaining == 0) {
+
+		logger->write_wrap_count = 0;
+		logger->read_wrap_count = 0;
+	}
+
+	*bytes_read = bytes_read_count;
+	unlock(logger);
+
+	return bytes_remaining;
+}
+
+void dal_logger_open(
+		struct dal_logger *logger,
+		struct log_entry *entry, /* out */
+		enum log_major major,
+		enum log_minor minor)
+{
+	if (!entry) {
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+
+	entry->major = LOG_MAJOR_COUNT;
+	entry->minor = 0;
+	entry->logger = logger;
+
+	entry->buf = dal_alloc(
+		DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE * sizeof(char));
+
+	entry->buf_offset = 0;
+	entry->max_buf_bytes =
+			DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE * sizeof(char);
+
+	logger->open_count++;
+	entry->major = major;
+	entry->minor = minor;
+
+	log_heading(entry, major, minor);
+}
+
+void dal_logger_close(struct log_entry *entry)
+{
+	struct dal_logger *logger = entry->logger;
+
+
+	if (logger && logger->open_count > 0) {
+		logger->open_count--;
+	} else {
+		BREAK_TO_DEBUGGER();
+		goto cleanup;
+	}
+
+	/* --Flush log_entry buffer-- */
+	/* print to kernel console */
+	log_to_debug_console(entry);
+	/* log internally for dsat */
+	log_to_internal_buffer(entry);
+
+	/* TODO: Write end heading */
+
+cleanup:
+	if (entry->buf) {
+		dal_free(entry->buf);
+		entry->buf = NULL;
+		entry->buf_offset = 0;
+		entry->max_buf_bytes = 0;
+	}
+}
+
+uint32_t dal_logger_get_mask(
+	struct dal_logger *logger,
+	enum log_major lvl_major, enum log_minor lvl_minor)
+{
+	uint32_t log_mask = 0;
+
+	if (logger && lvl_major < LOG_MAJOR_COUNT)
+		log_mask = logger->log_enable_mask_minors[lvl_major];
+
+	log_mask &= 1 << lvl_minor;
+	return log_mask;
+}
+
+uint32_t dal_logger_set_mask(
+	struct dal_logger *logger,
+	enum log_major lvl_major, enum log_minor lvl_minor)
+{
+
+	if (logger && lvl_major < LOG_MAJOR_COUNT) {
+		if (lvl_minor == LOG_MINOR_MASK_ALL) {
+			logger->log_enable_mask_minors[lvl_major] = 0xFFFFFFFF;
+		} else {
+			logger->log_enable_mask_minors[lvl_major] |=
+				(1 << lvl_minor);
+		}
+		return 0;
+	}
+	return 1;
+}
+
+uint32_t dal_logger_get_masks(
+	struct dal_logger *logger,
+	enum log_major lvl_major)
+{
+	uint32_t log_mask = 0;
+
+	if (logger && lvl_major < LOG_MAJOR_COUNT)
+		log_mask = logger->log_enable_mask_minors[lvl_major];
+
+	return log_mask;
+}
+
+void dal_logger_set_masks(
+	struct dal_logger *logger,
+	enum log_major lvl_major, uint32_t log_mask)
+{
+	if (logger && lvl_major < LOG_MAJOR_COUNT)
+		logger->log_enable_mask_minors[lvl_major] = log_mask;
+}
+
+uint32_t dal_logger_unset_mask(
+	struct dal_logger *logger,
+	enum log_major lvl_major, enum log_minor lvl_minor)
+{
+
+	if (lvl_major < LOG_MAJOR_COUNT) {
+		if (lvl_minor == LOG_MINOR_MASK_ALL) {
+			logger->log_enable_mask_minors[lvl_major] = 0;
+		} else {
+			logger->log_enable_mask_minors[lvl_major] &=
+				~(1 << lvl_minor);
+		}
+		return 0;
+	}
+	return 1;
+}
+
+uint32_t dal_logger_get_flags(
+		struct dal_logger *logger)
+{
+
+	return logger->flags.value;
+}
+
+void dal_logger_set_flags(
+		struct dal_logger *logger,
+		union logger_flags flags)
+{
+
+	logger->flags = flags;
+}
+
+
+uint32_t dal_logger_get_buffer_size(struct dal_logger *logger)
+{
+	return DAL_LOGGER_BUFFER_MAX_SIZE;
+}
+
+uint32_t dal_logger_set_buffer_size(
+		struct dal_logger *logger,
+		uint32_t new_size)
+{
+	/* ToDo: implement dynamic size */
+
+	/* return new size */
+	return DAL_LOGGER_BUFFER_MAX_SIZE;
+}
+
+
+const struct log_major_info *dal_logger_enum_log_major_info(
+		struct dal_logger *logger,
+		unsigned int enum_index)
+{
+	const struct log_major_info *major_info;
+
+	if (enum_index >= NUM_ELEMENTS(log_major_mask_info_tbl))
+		return NULL;
+
+	major_info = &log_major_mask_info_tbl[enum_index].major_info;
+	return major_info;
+}
+
+const struct log_minor_info *dal_logger_enum_log_minor_info(
+		struct dal_logger *logger,
+		enum log_major major,
+		unsigned int enum_index)
+{
+	const struct log_minor_info *minor_info = NULL;
+	uint32_t i;
+
+	for (i = 0; i < NUM_ELEMENTS(log_major_mask_info_tbl); i++) {
+
+		const struct log_major_mask_info *maj_mask_info =
+				&log_major_mask_info_tbl[i];
+
+		if (maj_mask_info->major_info.major == major) {
+
+			if (maj_mask_info->minor_tbl != NULL) {
+				uint32_t j;
+
+				for (j = 0; j < maj_mask_info->tbl_element_cnt; j++) {
+
+					minor_info = &maj_mask_info->minor_tbl[j];
+
+					if (minor_info->minor == enum_index)
+						return minor_info;
+				}
+			}
+
+			break;
+		}
+	}
+	return NULL;
+
+}
diff --git a/drivers/gpu/drm/amd/dal/basics/logger.h b/drivers/gpu/drm/amd/dal/basics/logger.h
new file mode 100644
index 000000000000..26c2990320dc
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/basics/logger.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_LOGGER_H__
+#define __DAL_LOGGER_H__
+
+/* Structure for keeping track of offsets, buffer, etc */
+
+#define DAL_LOGGER_BUFFER_MAX_SIZE 2048
+#define DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE 256
+
+
+#include "include/logger_types.h"
+
+struct dal_logger {
+
+	/* How far into the circular buffer has been read by dsat
+	 * Read offset should never cross write offset. Write \0's to
+	 * read data just to be sure?
+	 */
+	uint32_t buffer_read_offset;
+
+	/* How far into the circular buffer we have written
+	 * Write offset should never cross read offset
+	 */
+	uint32_t buffer_write_offset;
+
+	uint32_t write_wrap_count;
+	uint32_t read_wrap_count;
+
+	uint32_t open_count;
+
+	char *log_buffer;	/* Pointer to malloc'ed buffer */
+	uint32_t log_buffer_size; /* Size of circular buffer */
+
+	uint32_t *log_enable_mask_minors; /*array of masks for major elements*/
+
+	union logger_flags flags;
+};
+
+#endif /* __DAL_LOGGER_H__ */
diff --git a/drivers/gpu/drm/amd/dal/basics/register_logger.c b/drivers/gpu/drm/amd/dal/basics/register_logger.c
new file mode 100644
index 000000000000..d1bbb2d4ce53
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/basics/register_logger.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dal_services.h"
+#include "include/dal_types.h"
+#include "include/logger_interface.h"
+#include "logger.h"
+
+/******************************************************************************
+ * Register Logger.
+ * A facility to create register R/W logs.
+ * Currently used for DAL Test.
+ *****************************************************************************/
+
+/******************************************************************************
+ * Private structures
+ *****************************************************************************/
+struct dal_reg_dump_stack_location {
+	const char *current_caller_func;
+	long current_pid;
+	long current_tgid;
+	uint32_t rw_count;/* register access counter for current function. */
+};
+
+/* This the maximum number of nested calls to the 'reg_dump' facility. */
+#define DAL_REG_DUMP_STACK_MAX_SIZE 32
+
+struct dal_reg_dump_stack {
+	int32_t stack_pointer;
+	struct dal_reg_dump_stack_location
+		stack_locations[DAL_REG_DUMP_STACK_MAX_SIZE];
+	uint32_t total_rw_count; /* Total count for *all* functions. */
+};
+
+static struct dal_reg_dump_stack reg_dump_stack = {0};
+
+/******************************************************************************
+ * Private functions
+ *****************************************************************************/
+
+/* Check if current process is the one which requested register dump.
+ * The reason for the check:
+ * mmCRTC_STATUS_FRAME_COUNT is accessed by dal_controller_get_vblank_counter().
+ * Which runs all the time when at least one display is connected.
+ * (Triggered by drm_mode_page_flip_ioctl()). */
+static bool is_reg_dump_process(void)
+{
+	uint32_t i;
+
+	/* walk the list of our processes */
+	for (i = 0; i < reg_dump_stack.stack_pointer; i++) {
+		struct dal_reg_dump_stack_location *stack_location
+					= &reg_dump_stack.stack_locations[i];
+
+		if (stack_location->current_pid == dal_get_pid()
+			&& stack_location->current_tgid == dal_get_tgid())
+			return true;
+	}
+
+	return false;
+}
+
+static bool dal_reg_dump_stack_is_empty(void)
+{
+	if (reg_dump_stack.stack_pointer <= 0)
+		return true;
+	else
+		return false;
+}
+
+static struct dal_reg_dump_stack_location *dal_reg_dump_stack_push(void)
+{
+	struct dal_reg_dump_stack_location *current_location = NULL;
+
+	if (reg_dump_stack.stack_pointer >= DAL_REG_DUMP_STACK_MAX_SIZE) {
+		/* stack is full */
+		dal_output_to_console("[REG_DUMP]: %s: stack is full!\n",
+				__func__);
+	} else {
+		current_location =
+		&reg_dump_stack.stack_locations[reg_dump_stack.stack_pointer];
+		++reg_dump_stack.stack_pointer;
+	}
+
+	return current_location;
+}
+
+static struct dal_reg_dump_stack_location *dal_reg_dump_stack_pop(void)
+{
+	struct dal_reg_dump_stack_location *current_location = NULL;
+
+	if (dal_reg_dump_stack_is_empty()) {
+		/* stack is empty */
+		dal_output_to_console("[REG_DUMP]: %s: stack is empty!\n",
+				__func__);
+	} else {
+		--reg_dump_stack.stack_pointer;
+		current_location =
+		&reg_dump_stack.stack_locations[reg_dump_stack.stack_pointer];
+	}
+
+	return current_location;
+}
+
+/******************************************************************************
+ * Public functions
+ *****************************************************************************/
+
+void dal_reg_logger_push(const char *caller_func)
+{
+	struct dal_reg_dump_stack_location *free_stack_location;
+
+	free_stack_location = dal_reg_dump_stack_push();
+
+	if (NULL == free_stack_location)
+		return;
+
+	dal_memset(free_stack_location, 0, sizeof(*free_stack_location));
+
+	free_stack_location->current_caller_func = caller_func;
+	free_stack_location->current_pid = dal_get_pid();
+	free_stack_location->current_tgid = dal_get_tgid();
+
+	dal_output_to_console("[REG_DUMP]:%s - start (pid:%ld, tgid:%ld)\n",
+		caller_func,
+		free_stack_location->current_pid,
+		free_stack_location->current_tgid);
+}
+
+void dal_reg_logger_pop(void)
+{
+	struct dal_reg_dump_stack_location *top_stack_location;
+
+	top_stack_location = dal_reg_dump_stack_pop();
+
+	if (NULL == top_stack_location) {
+		dal_output_to_console("[REG_DUMP]:%s - Stack is Empty!\n",
+				__func__);
+		return;
+	}
+
+	dal_output_to_console(
+	"[REG_DUMP]:%s - end."\
+	" Reg R/W Count: Total=%d Function=%d. (pid:%ld, tgid:%ld)\n",
+			top_stack_location->current_caller_func,
+			reg_dump_stack.total_rw_count,
+			top_stack_location->rw_count,
+			dal_get_pid(),
+			dal_get_tgid());
+
+	dal_memset(top_stack_location, 0, sizeof(*top_stack_location));
+}
+
+void dal_reg_logger_rw_count_increment(void)
+{
+	++reg_dump_stack.total_rw_count;
+
+	++reg_dump_stack.stack_locations
+		[reg_dump_stack.stack_pointer - 1].rw_count;
+}
+
+bool dal_reg_logger_should_dump_register(void)
+{
+	if (true == dal_reg_dump_stack_is_empty())
+		return false;
+
+	if (false == is_reg_dump_process())
+		return false;
+
+	return true;
+}
+
+/******************************************************************************
+ * End of File.
+ *****************************************************************************/
diff --git a/drivers/gpu/drm/amd/dal/basics/signal_types.c b/drivers/gpu/drm/amd/dal/basics/signal_types.c
new file mode 100644
index 000000000000..fad12ed30f32
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/basics/signal_types.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dal_services.h"
+#include "include/signal_types.h"
+
+bool dal_is_hdmi_signal(enum signal_type signal)
+{
+	return (signal == SIGNAL_TYPE_HDMI_TYPE_A);
+}
+
+bool dal_is_dp_sst_signal(enum signal_type signal)
+{
+	return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
+		signal == SIGNAL_TYPE_EDP);
+}
+
+bool dal_is_dp_signal(enum signal_type signal)
+{
+	return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
+		signal == SIGNAL_TYPE_EDP ||
+		signal == SIGNAL_TYPE_DISPLAY_PORT_MST);
+}
+
+bool dal_is_dp_external_signal(enum signal_type signal)
+{
+	return (signal == SIGNAL_TYPE_DISPLAY_PORT ||
+		signal == SIGNAL_TYPE_DISPLAY_PORT_MST);
+}
+
+bool dal_is_analog_signal(enum signal_type signal)
+{
+	switch (signal) {
+	case SIGNAL_TYPE_RGB:
+	case SIGNAL_TYPE_YPBPR:
+	case SIGNAL_TYPE_COMPOSITE:
+	case SIGNAL_TYPE_SVIDEO:
+	case SIGNAL_TYPE_SCART:
+		return true;
+	break;
+	default:
+		return false;
+	}
+}
+
+bool dal_is_embedded_signal(enum signal_type signal)
+{
+	return (signal == SIGNAL_TYPE_EDP ||
+		signal == SIGNAL_TYPE_LVDS);
+}
+
+bool dal_is_dvi_signal(enum signal_type signal)
+{
+	switch (signal) {
+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
+	case SIGNAL_TYPE_DVI_SINGLE_LINK1:
+	case SIGNAL_TYPE_DVI_DUAL_LINK:
+		return true;
+	break;
+	default:
+		return false;
+	}
+}
+
+bool dal_is_dvo_signal(enum signal_type signal)
+{
+	return (signal == SIGNAL_TYPE_DVO ||
+		signal == SIGNAL_TYPE_DVO24);
+}
+
+bool dal_is_mvpu_signal(enum signal_type signal)
+{
+	switch (signal) {
+	case SIGNAL_TYPE_MVPU_A:
+	case SIGNAL_TYPE_MVPU_B:
+	case SIGNAL_TYPE_MVPU_AB:
+		return true;
+	break;
+	default:
+		return false;
+	}
+}
+
+bool dal_is_cf_signal(enum signal_type signal)
+{
+	switch (signal) {
+	case SIGNAL_TYPE_DVO24:
+	case SIGNAL_TYPE_MVPU_AB:
+	case SIGNAL_TYPE_DVO:
+	case SIGNAL_TYPE_MVPU_A:
+	case SIGNAL_TYPE_MVPU_B:
+		return true;
+	break;
+	default:
+		return false;
+	}
+}
+
+bool dal_is_dvi_single_link_signal(enum signal_type signal)
+{
+	return (signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
+		signal == SIGNAL_TYPE_DVI_SINGLE_LINK1);
+}
+
+bool dal_is_dual_link_signal(enum signal_type signal)
+{
+	return (signal == SIGNAL_TYPE_DVI_DUAL_LINK);
+}
+
+bool dal_is_audio_capable_signal(enum signal_type signal)
+{
+	return (dal_is_dp_signal(signal) ||
+		dal_is_hdmi_signal(signal) ||
+		signal == SIGNAL_TYPE_WIRELESS);
+}
+
+/*
+ * @brief
+ * Returns whether the signal is compatible
+ * with other digital encoder signal types.
+ * This is true for DVI, LVDS, and HDMI signal types.
+ */
+bool dal_is_digital_encoder_compatible_signal(enum signal_type signal)
+{
+	switch (signal) {
+	case SIGNAL_TYPE_DVI_SINGLE_LINK:
+	case SIGNAL_TYPE_DVI_SINGLE_LINK1:
+	case SIGNAL_TYPE_DVI_DUAL_LINK:
+	case SIGNAL_TYPE_HDMI_TYPE_A:
+	case SIGNAL_TYPE_LVDS:
+		return true;
+	default:
+		return false;
+	}
+}
diff --git a/drivers/gpu/drm/amd/dal/basics/vector.c b/drivers/gpu/drm/amd/dal/basics/vector.c
new file mode 100644
index 000000000000..21235132494e
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/basics/vector.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dal_services.h"
+#include "include/vector.h"
+
+bool dal_vector_construct(
+	struct vector *vector,
+	uint32_t capacity,
+	uint32_t struct_size)
+{
+	vector->container = NULL;
+
+	if (!struct_size || !capacity) {
+		/* Container must be non-zero size*/
+		BREAK_TO_DEBUGGER();
+		return false;
+	}
+
+	vector->container = dal_alloc(struct_size * capacity);
+	if (vector->container == NULL)
+		return false;
+	vector->capacity = capacity;
+	vector->struct_size = struct_size;
+	vector->count = 0;
+	return true;
+}
+
+bool dal_vector_presized_costruct(
+	struct vector *vector,
+	uint32_t count,
+	void *initial_value,
+	uint32_t struct_size)
+{
+	uint32_t i;
+
+	vector->container = NULL;
+
+	if (!struct_size || !count) {
+		/* Container must be non-zero size*/
+		BREAK_TO_DEBUGGER();
+		return false;
+	}
+
+	vector->container = dal_alloc(struct_size * count);
+
+	if (vector->container == NULL)
+		return false;
+
+	/* If caller didn't supply initial value then the default
+	 * of all zeros is expected, which is exactly what dal_alloc()
+	 * initialises the memory to. */
+	if (NULL != initial_value) {
+		for (i = 0; i < count; ++i)
+			dal_memmove(
+				vector->container + i * struct_size,
+				initial_value,
+				struct_size);
+	}
+
+	vector->capacity = count;
+	vector->struct_size = struct_size;
+	vector->count = count;
+	return true;
+}
+
+struct vector *dal_vector_presized_create(
+	uint32_t size,
+	void *initial_value,
+	uint32_t struct_size)
+{
+	struct vector *vector = dal_alloc(sizeof(struct vector));
+
+	if (vector == NULL)
+		return NULL;
+
+	if (dal_vector_presized_costruct(
+		vector, size, initial_value, struct_size))
+		return vector;
+
+	BREAK_TO_DEBUGGER();
+	dal_free(vector);
+	return NULL;
+}
+
+struct vector *dal_vector_create(
+	uint32_t capacity,
+	uint32_t struct_size)
+{
+	struct vector *vector = dal_alloc(sizeof(struct vector));
+
+	if (vector == NULL)
+		return NULL;
+
+	if (dal_vector_construct(vector, capacity, struct_size))
+		return vector;
+
+
+	BREAK_TO_DEBUGGER();
+	dal_free(vector);
+	return NULL;
+}
+
+void dal_vector_destruct(
+	struct vector *vector)
+{
+	if (vector->container != NULL)
+		dal_free(vector->container);
+	vector->count = 0;
+	vector->capacity = 0;
+}
+
+void dal_vector_destroy(
+	struct vector **vector)
+{
+	if (vector == NULL || *vector == NULL)
+		return;
+	dal_vector_destruct(*vector);
+	dal_free(*vector);
+	*vector = NULL;
+}
+
+uint32_t dal_vector_get_count(
+	const struct vector *vector)
+{
+	return vector->count;
+}
+
+void *dal_vector_at_index(
+	const struct vector *vector,
+	uint32_t index)
+{
+	if (vector->container == NULL || index >= vector->count)
+		return NULL;
+	return vector->container + (index * vector->struct_size);
+}
+
+bool dal_vector_remove_at_index(
+	struct vector *vector,
+	uint32_t index)
+{
+	if (index >= vector->count)
+		return false;
+
+	if (index != vector->count - 1)
+		dal_memmove(
+			vector->container + (index * vector->struct_size),
+			vector->container + ((index + 1) * vector->struct_size),
+			(vector->count - index - 1) * vector->struct_size);
+	vector->count -= 1;
+
+	return true;
+}
+
+void dal_vector_set_at_index(
+	const struct vector *vector,
+	const void *what,
+	uint32_t index)
+{
+	void *where = dal_vector_at_index(vector, index);
+
+	if (!where) {
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+	dal_memmove(
+		where,
+		what,
+		vector->struct_size);
+}
+
+static inline uint32_t calc_increased_capacity(
+	uint32_t old_capacity)
+{
+	return old_capacity * 2;
+}
+
+bool dal_vector_insert_at(
+	struct vector *vector,
+	const void *what,
+	uint32_t position)
+{
+	uint8_t *insert_address;
+
+	if (vector->count == vector->capacity) {
+		if (!dal_vector_reserve(
+			vector,
+			calc_increased_capacity(vector->capacity)))
+			return false;
+	}
+
+	insert_address = vector->container + (vector->struct_size * position);
+
+	if (vector->count && position < vector->count)
+		dal_memmove(
+			insert_address + vector->struct_size,
+			insert_address,
+			vector->struct_size * (vector->count - position));
+
+	dal_memmove(
+		insert_address,
+		what,
+		vector->struct_size);
+
+	vector->count++;
+
+	return true;
+}
+
+bool dal_vector_append(
+	struct vector *vector,
+	const void *item)
+{
+	return dal_vector_insert_at(vector, item, vector->count);
+}
+
+struct vector *dal_vector_clone(
+	const struct vector *vector)
+{
+	struct vector *vec_cloned;
+	uint32_t count;
+
+	/* create new vector */
+	count = dal_vector_get_count(vector);
+
+	if (count == 0)
+		/* when count is 0 we still want to create clone of the vector
+		 */
+		vec_cloned = dal_vector_create(
+			vector->capacity,
+			vector->struct_size);
+	else
+		/* Call "presized create" version, independently of how the
+		 * original vector was created.
+		 * The owner of original vector must know how to treat the new
+		 * vector - as "presized" or as "regular".
+		 * But from vector point of view it doesn't matter. */
+		vec_cloned = dal_vector_presized_create(count,
+			NULL,/* no initial value */
+			vector->struct_size);
+
+	if (NULL == vec_cloned) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	/* copy vector's data */
+	dal_memmove(vec_cloned->container, vector->container,
+			vec_cloned->struct_size * vec_cloned->capacity);
+
+	return vec_cloned;
+}
+
+uint32_t dal_vector_capacity(const struct vector *vector)
+{
+	return vector->capacity;
+}
+
+bool dal_vector_reserve(struct vector *vector, uint32_t capacity)
+{
+	void *new_container;
+
+	if (capacity <= vector->capacity)
+		return true;
+
+	new_container = dal_realloc(vector->container,
+		capacity * vector->struct_size);
+
+	if (new_container) {
+		vector->container = new_container;
+		vector->capacity = capacity;
+		return true;
+	}
+
+	return false;
+}
+
+void dal_vector_clear(struct vector *vector)
+{
+	vector->count = 0;
+}
diff --git a/drivers/gpu/drm/amd/dal/dal_power_interface_types.h b/drivers/gpu/drm/amd/dal/dal_power_interface_types.h
new file mode 100644
index 000000000000..82e8ca24093f
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dal_power_interface_types.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_POWER_INTERFACE_TYPES_H__
+#define __DAL_POWER_INTERFACE_TYPES_H__
+
+enum dal_to_power_clocks_state {
+	PP_CLOCKS_STATE_INVALID,
+	PP_CLOCKS_STATE_ULTRA_LOW,
+	PP_CLOCKS_STATE_LOW,
+	PP_CLOCKS_STATE_NOMINAL,
+	PP_CLOCKS_STATE_PERFORMANCE
+};
+
+/* clocks in khz */
+struct dal_to_power_info {
+	enum dal_to_power_clocks_state required_clock;
+	uint32_t min_sclk;
+	uint32_t min_mclk;
+	uint32_t min_deep_sleep_sclk;
+};
+
+/* clocks in khz */
+struct power_to_dal_info {
+	uint32_t min_sclk;
+	uint32_t max_sclk;
+	uint32_t min_mclk;
+	uint32_t max_mclk;
+};
+
+/* clocks in khz */
+struct dal_system_clock_range {
+	uint32_t min_sclk;
+	uint32_t max_sclk;
+
+	uint32_t min_mclk;
+	uint32_t max_mclk;
+
+	uint32_t min_dclk;
+	uint32_t max_dclk;
+
+	/* Wireless Display */
+	uint32_t min_eclk;
+	uint32_t max_eclk;
+};
+
+/* clocks in khz */
+struct dal_to_power_dclk {
+	uint32_t optimal; /* input: best optimizes for stutter efficiency */
+	uint32_t minimal; /* input: the lowest clk that DAL can support */
+	uint32_t established; /* output: the actually set one */
+};
+
+#endif /* __DAL_POWER_INTERFACE_TYPES_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dal_services.h b/drivers/gpu/drm/amd/dal/dal_services.h
new file mode 100644
index 000000000000..47fa6a3fa0d8
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dal_services.h
@@ -0,0 +1,400 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_SERVICES_H__
+#define __DAL_SERVICES_H__
+
+#include <linux/slab.h>
+
+#include "dal_services_types.h"
+#include "dal_power_interface_types.h"
+
+#include "include/irq_types.h"
+#include "include/dal_types.h"
+
+/*
+ *
+ * interrupt services to register and unregister handlers
+ *
+ */
+
+/* the timer "interrupt" current implementation supports only
+'one-shot' type, and LOW level (asynchronous) context */
+void dal_register_timer_interrupt(
+	struct dal_context *context,
+	struct dal_timer_interrupt_params *int_params,
+	interrupt_handler ih,
+	void *handler_args);
+
+irq_handler_idx dal_register_interrupt(
+	struct dal_context *context,
+	struct dal_interrupt_params *int_params,
+	interrupt_handler ih,
+	void *handler_args);
+
+void dal_unregister_interrupt(
+	struct dal_context *context,
+	enum dal_irq_source irq_source,
+	irq_handler_idx handler_idx);
+
+/*
+ *
+ * kernel memory manipulation
+ *
+ */
+
+/* if the pointer is not NULL, the allocated memory is zeroed */
+#define dal_alloc(size) kzalloc(size, GFP_KERNEL)
+
+/* Reallocate memory. The contents will remain unchanged.*/
+#define dal_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL)
+
+#define dal_memmove(dst, src, size) memmove(dst, src, size)
+
+/* free the memory which was allocated by dal_alloc or dal_realloc */
+#define dal_free(p) kfree(p)
+
+#define dal_memset(ptr, value, count) memset(ptr, value, count)
+
+#define dal_memcmp(p1, p2, count) memcmp(p1, p2, count)
+
+/* comparison of null-terminated strings */
+#define dal_strcmp(p1, p2) strcmp(p1, p2)
+
+#define dal_strncmp(p1, p2, count) strncmp(p1, p2, count)
+
+/*
+ *
+ * GPU registers access
+ *
+ */
+static inline uint32_t dal_read_reg(
+	struct dal_context *ctx,
+	uint32_t address)
+{
+	uint32_t value = cgs_read_register(ctx->cgs_device, address);
+
+#if defined(__DAL_REGISTER_LOGGER__)
+	if (true == dal_reg_logger_should_dump_register()) {
+		dal_reg_logger_rw_count_increment();
+		DRM_INFO("%s 0x%x 0x%x\n", __func__, address, value);
+	}
+#endif
+	return value;
+}
+
+static inline uint32_t get_reg_field_value_ex(
+	uint32_t reg_value,
+	uint32_t mask,
+	uint8_t shift)
+{
+	return (mask & reg_value) >> shift;
+}
+
+#define get_reg_field_value(reg_value, reg_name, reg_field)\
+	get_reg_field_value_ex(\
+		(reg_value),\
+		reg_name ## __ ## reg_field ## _MASK,\
+		reg_name ## __ ## reg_field ## __SHIFT)
+
+static inline uint32_t set_reg_field_value_ex(
+	uint32_t reg_value,
+	uint32_t value,
+	uint32_t mask,
+	uint8_t shift)
+{
+	return (reg_value & ~mask) | (mask & (value << shift));
+}
+
+#define set_reg_field_value(reg_value, value, reg_name, reg_field)\
+	(reg_value) = set_reg_field_value_ex(\
+		(reg_value),\
+		(value),\
+		reg_name ## __ ## reg_field ## _MASK,\
+		reg_name ## __ ## reg_field ## __SHIFT)
+
+static inline void dal_write_reg(
+	struct dal_context *ctx,
+	uint32_t address,
+	uint32_t value)
+{
+#if defined(__DAL_REGISTER_LOGGER__)
+	if (true == dal_reg_logger_should_dump_register()) {
+		dal_reg_logger_rw_count_increment();
+		DRM_INFO("%s 0x%x 0x%x\n", __func__, address, value);
+	}
+#endif
+	cgs_write_register(ctx->cgs_device, address, value);
+}
+
+static inline uint32_t dal_read_index_reg(
+	struct dal_context *ctx,
+	enum cgs_ind_reg addr_space,
+	uint32_t index)
+{
+
+	return cgs_read_ind_register(ctx->cgs_device,addr_space,index);
+}
+
+static inline void dal_write_index_reg(
+	struct dal_context *ctx,
+	enum cgs_ind_reg addr_space,
+	uint32_t index,
+	uint32_t value)
+{
+	cgs_write_ind_register(ctx->cgs_device,addr_space,index,value);
+}
+
+enum platform_method {
+	PM_GET_AVAILABLE_METHODS = 1 << 0,
+	PM_GET_LID_STATE = 1 << 1,
+	PM_GET_EXTENDED_BRIGHNESS_CAPS = 1 << 2
+};
+
+struct platform_info_params {
+	enum platform_method method;
+	void *data;
+};
+
+struct platform_info_brightness_caps {
+	uint8_t ac_level_percentage;
+	uint8_t dc_level_percentage;
+};
+
+struct platform_info_ext_brightness_caps {
+	struct platform_info_brightness_caps basic_caps;
+	struct data_point {
+		uint8_t luminance;
+		uint8_t	signal_level;
+	} data_points[99];
+
+	uint8_t	data_points_num;
+	uint8_t	min_input_signal;
+	uint8_t	max_input_signal;
+};
+
+bool dal_get_platform_info(
+	struct dal_context *dal_context,
+	struct platform_info_params *params);
+
+
+static inline uint32_t dal_bios_cmd_table_para_revision(
+	struct dal_context *ctx,
+	uint32_t index)
+{
+	uint8_t frev;
+	uint8_t crev;
+
+	if (cgs_atom_get_cmd_table_revs(
+			ctx->cgs_device,
+			index,
+			&frev,
+			&crev) != 0)
+		return 0;
+
+	return crev;
+}
+
+/**************************************
+ * Calls to Power Play (PP) component
+ **************************************/
+
+/* DAL calls this function to notify PP about clocks it needs for the Mode Set.
+ * This is done *before* it changes DCE clock.
+ *
+ * If required clock is higher than current, then PP will increase the voltage.
+ *
+ * If required clock is lower than current, then PP will defer reduction of
+ * voltage until the call to dal_pp_post_dce_clock_change().
+ *
+ * \input - Contains clocks needed for Mode Set.
+ *
+ * \output - Contains clocks adjusted by PP which DAL should use for Mode Set.
+ *		Valid only if function returns zero.
+ *
+ * \returns	true - call is successful
+ *		false - call failed
+ */
+bool dal_pp_pre_dce_clock_change(
+	struct dal_context *ctx,
+	struct dal_to_power_info *input,
+	struct power_to_dal_info *output);
+
+/* DAL calls this function to notify PP about completion of Mode Set.
+ * For PP it means that current DCE clocks are those which were returned
+ * by dal_pp_pre_dce_clock_change(), in the 'output' parameter.
+ *
+ * If the clocks are higher than before, then PP does nothing.
+ *
+ * If the clocks are lower than before, then PP reduces the voltage.
+ *
+ * \returns	true - call is successful
+ *		false - call failed
+ */
+bool dal_pp_post_dce_clock_change(struct dal_context *ctx);
+
+/* The returned clocks range are 'static' system clocks which will be used for
+ * mode validation purposes.
+ *
+ * \returns	true - call is successful
+ *		false - call failed
+ */
+bool dal_get_system_clocks_range(
+	struct dal_context *ctx,
+	struct dal_system_clock_range *sys_clks);
+
+/* for future use */
+bool dal_pp_set_display_clock(
+	struct dal_context *ctx,
+	struct dal_to_power_dclk *dclk);
+
+
+/* end of power component calls */
+
+
+/* Calls to notification */
+
+/* Notify display manager for hotplug event */
+void dal_notify_hotplug(
+	struct dal_context *ctx,
+	uint32_t display_index,
+	bool is_connected);
+
+/* Notify display manager for capability change event */
+void dal_notify_capability_change(
+	struct dal_context *ctx,
+	uint32_t display_index);
+
+void dal_notify_setmode_complete(
+	struct dal_context *ctx,
+	uint32_t h_total,
+	uint32_t v_total,
+	uint32_t h_active,
+	uint32_t v_active,
+	uint32_t pix_clk_in_khz);
+
+/* End of notification calls */
+
+/*
+ *
+ * Delay functions.
+ *
+ *
+ */
+
+/* Following the guidance:
+ * https://www.kernel.org/doc/Documentation/timers/timers-howto.txt
+ *
+ * This is a busy wait for nano seconds and should be used only for
+ * extremely short ranges
+ */
+#define dal_delay_in_nanoseconds(nanoseconds) ndelay(nanoseconds)
+
+/* Following the guidance:
+ * https://www.kernel.org/doc/Documentation/timers/timers-howto.txt
+ *
+ * This is a busy wait for micro seconds and should.
+ */
+#define dal_delay_in_microseconds(microseconds) udelay(microseconds)
+
+/* Following the guidances:
+ * https://www.kernel.org/doc/Documentation/timers/timers-howto.txt
+ * http://lkml.indiana.edu/hypermail/linux/kernel/1008.0/00733.html
+ *
+ * This is a sleep (not busy-waiting) for milliseconds with a
+ * good precision.
+ */
+#define dal_sleep_in_milliseconds(milliseconds) \
+{ \
+	if (milliseconds >= 20) \
+		msleep(milliseconds); \
+	else \
+		usleep_range(milliseconds*1000, milliseconds*1000+1); \
+}
+
+/*
+ *
+ * atombios services
+ *
+ */
+
+bool dal_exec_bios_cmd_table(
+	struct dal_context *ctx,
+	uint32_t index,
+	void *params);
+
+
+/*
+ *
+ * print-out services
+ *
+ */
+#define dal_log_to_buffer(buffer, size, fmt, args)\
+	vsnprintf(buffer, size, fmt, args)
+
+long dal_get_pid(void);
+long dal_get_tgid(void);
+
+/*
+ *
+ * general debug capabilities
+ *
+ */
+#if defined(CONFIG_DEBUG_KERNEL) || defined(CONFIG_DEBUG_DRIVER)
+
+#if defined(CONFIG_HAVE_KGDB) || defined(CONFIG_KGDB)
+#define ASSERT_CRITICAL(expr) do {	\
+	if (WARN_ON(!(expr))) { \
+		kgdb_breakpoint(); \
+	} \
+} while (0)
+#else
+#define ASSERT_CRITICAL(expr) do {	\
+	if (WARN_ON(!(expr))) { \
+		; \
+	} \
+} while (0)
+#endif
+
+#if defined(CONFIG_DEBUG_KERNEL_DAL)
+#define ASSERT(expr) ASSERT_CRITICAL(expr)
+
+#else
+#define ASSERT(expr) WARN_ON(!(expr))
+#endif
+
+#define BREAK_TO_DEBUGGER() ASSERT(0)
+
+#else
+
+#define ASSERT_CRITICAL(expr)  do {if (expr)/* Do nothing */; } while (0)
+
+#define ASSERT(expr) do {if (expr)/* Do nothing */; } while (0)
+
+#define BREAK_TO_DEBUGGER() do {} while (0)
+
+#endif /* CONFIG_DEBUG_KERNEL || CONFIG_DEBUG_DRIVER */
+
+#endif /* __DAL_SERVICES_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dal_services_types.h b/drivers/gpu/drm/amd/dal/dal_services_types.h
new file mode 100644
index 000000000000..89c73c651d09
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dal_services_types.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_SERVICES_TYPES_H__
+#define __DAL_SERVICES_TYPES_H__
+
+#define INVALID_DISPLAY_INDEX 0xffffffff
+
+#if defined __KERNEL__
+
+#include <asm/byteorder.h>
+#include <linux/types.h>
+#include <drm/drmP.h>
+
+#include "cgs_linux.h"
+
+#if defined(__BIG_ENDIAN) && !defined(BIGENDIAN_CPU)
+#define BIGENDIAN_CPU
+#elif defined(__LITTLE_ENDIAN) && !defined(LITTLEENDIAN_CPU)
+#define LITTLEENDIAN_CPU
+#endif
+
+#undef READ
+#undef WRITE
+#undef FRAME_SIZE
+
+#define dal_output_to_console(fmt, ...) DRM_INFO(fmt, ##__VA_ARGS__)
+
+#define dal_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
+
+#define dal_debug(fmt, ...) DRM_DEBUG_KMS(fmt, ##__VA_ARGS__)
+
+#define dal_vlog(fmt, args) vprintk(fmt, args)
+
+#define dal_min(x, y) min(x, y)
+#define dal_max(x, y) max(x, y)
+
+#endif
+
+#endif
diff --git a/drivers/gpu/drm/amd/dal/include/bit_set.h b/drivers/gpu/drm/amd/dal/include/bit_set.h
new file mode 100644
index 000000000000..6e3d3a57cb31
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/include/bit_set.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_BIT_SET_H__
+#define __DAL_BIT_SET_H__
+
+struct bit_set_iterator_32 {
+	uint32_t value;
+};
+
+static inline uint32_t least_significant_bit(uint32_t bs32_container)
+{
+	return bs32_container & (-bs32_container);
+}
+/* iterates over bit_set_iterator by means of least significant bit purge*/
+static inline uint32_t get_next_significant_bit(
+		struct bit_set_iterator_32 *bs32)
+{
+	uint32_t lsb = least_significant_bit(bs32->value);
+
+	bs32->value &= ~lsb;
+	return lsb;
+}
+
+static inline void bit_set_iterator_reset_to_mask(
+		struct bit_set_iterator_32 *bs32,
+		uint32_t mask)
+{
+	bs32->value = mask;
+}
+
+static inline void bit_set_iterator_construct(
+		struct bit_set_iterator_32 *bs32,
+		uint32_t mask)
+{
+	bit_set_iterator_reset_to_mask(bs32, mask);
+}
+
+#endif /* __DAL_BIT_SET_H__ */
diff --git a/drivers/gpu/drm/amd/dal/include/dal_asic_id.h b/drivers/gpu/drm/amd/dal/include/dal_asic_id.h
new file mode 100644
index 000000000000..da33f4dea666
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/include/dal_asic_id.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_ASIC_ID_H__
+#define __DAL_ASIC_ID_H__
+
+/*
+ * ASIC internal revision ID
+ */
+
+/* DCE80 (based on ci_id.h in Perforce) */
+#define	CI_BONAIRE_M_A0 0x14
+#define	CI_BONAIRE_M_A1	0x15
+#define	CI_HAWAII_P_A0	0x28
+#define CI_UNKNOWN	0xFF
+
+#define ASIC_REV_IS_BONAIRE_M(rev) \
+	((rev >= CI_BONAIRE_M_A0) && (rev < CI_HAWAII_P_A0))
+
+#define ASIC_REV_IS_HAWAII_P(rev) \
+	(rev >= CI_HAWAII_P_A0)
+
+/* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */
+#define KV_SPECTRE_A0 0x01
+
+/* KV2 with Spooky GFX core, including downgraded from Spectre core,
+ * 3-4-1-1 (CU-Pix-Primitive-RB) */
+#define KV_SPOOKY_A0 0x41
+
+/* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
+#define KB_KALINDI_A0 0x81
+
+/* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
+#define KB_KALINDI_A1 0x82
+
+/* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
+#define BV_KALINDI_A2 0x85
+
+/* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
+#define ML_GODAVARI_A0 0xA1
+
+/* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
+#define ML_GODAVARI_A1 0xA2
+
+#define KV_UNKNOWN 0xFF
+
+#define ASIC_REV_IS_KALINDI(rev) \
+	((rev >= KB_KALINDI_A0) && (rev < KV_UNKNOWN))
+
+#define ASIC_REV_IS_BHAVANI(rev) \
+	((rev >= BV_KALINDI_A2) && (rev < ML_GODAVARI_A0))
+
+#define ASIC_REV_IS_GODAVARI(rev) \
+	((rev >= ML_GODAVARI_A0) && (rev < KV_UNKNOWN))
+
+/* DCE11 */
+#define CZ_CARRIZO_A0 0x01
+#define CZ_UNKNOWN 0xFF
+
+
+/*
+ * ASIC chip ID
+ */
+/* DCE80 */
+#define DEVICE_ID_KALINDI_9834 0x9834
+#define DEVICE_ID_TEMASH_9839 0x9839
+#define DEVICE_ID_TEMASH_983D 0x983D
+
+
+/* Asic Family IDs for different asic family. */
+#define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
+#define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
+#define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */
+#define FAMILY_CZ 135 /* Carrizo */
+#define	FAMILY_UNKNOWN 0xFF
+
+#endif /* __DAL_ASIC_ID_H__ */
diff --git a/drivers/gpu/drm/amd/dal/include/dal_register_logger.h b/drivers/gpu/drm/amd/dal/include/dal_register_logger.h
new file mode 100644
index 000000000000..176d811327af
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/include/dal_register_logger.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_REGISTER_LOGGER__
+#define __DAL_REGISTER_LOGGER__
+
+/****************
+ * API functions
+ ***************/
+
+/* dal_reg_logger_push - begin Register Logging */
+void dal_reg_logger_push(const char *caller_func);
+/* dal_reg_logger_pop - stop Register Logging */
+void dal_reg_logger_pop(void);
+
+
+/* for internal use of the Logger only */
+void dal_reg_logger_rw_count_increment(void);
+bool dal_reg_logger_should_dump_register(void);
+
+#endif /* __DAL_REGISTER_LOGGER__ */
diff --git a/drivers/gpu/drm/amd/dal/include/dal_types.h b/drivers/gpu/drm/amd/dal/include/dal_types.h
new file mode 100644
index 000000000000..d1e64737bed6
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/include/dal_types.h
@@ -0,0 +1,317 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_TYPES_H__
+#define __DAL_TYPES_H__
+
+struct dal_logger;
+
+enum dce_version {
+	DCE_VERSION_UNKNOWN = (-1),
+	DCE_VERSION_11_0,
+	DCE_VERSION_MAX
+};
+
+enum dal_power_state {
+	DAL_POWER_STATE_ON = 1,
+	DAL_POWER_STATE_STANDBY,
+	DAL_POWER_STATE_SUSPEND,
+	DAL_POWER_STATE_OFF
+};
+
+/* DAL PowerStates */
+enum dal_video_power_state {
+	DAL_VIDEO_POWER_UNSPECIFIED = 0,
+	DAL_VIDEO_POWER_ON = 1,
+	DAL_VIDEO_POWER_STANDBY,
+	DAL_VIDEO_POWER_SUSPEND,
+	DAL_VIDEO_POWER_OFF,
+	DAL_VIDEO_POWER_HIBERNATE,
+	DAL_VIDEO_POWER_SHUTDOWN,
+	DAL_VIDEO_POWER_ULPS,	/* BACO or Ultra-Light-Power-State */
+	DAL_VIDEO_POWER_AFTER_RESET,
+	DAL_VIDEO_POWER_MAXIMUM
+};
+
+enum dal_acpi_cm_power_state {
+	DAL_ACPI_CM_POWER_STATE_D0 = 1,
+	DAL_ACPI_CM_POWER_STATE_D1 = 2,
+	DAL_ACPI_CM_POWER_STATE_D2 = 4,
+	DAL_ACPI_CM_POWER_STATE_D3 = 8
+};
+
+struct view_port_alignment {
+	uint8_t x_width_size_alignment;
+	uint8_t y_height_size_alignment;
+	uint8_t x_start_alignment;
+	uint8_t y_start_alignment;
+};
+
+/*
+ * ASIC Runtime Flags
+ */
+struct dal_asic_runtime_flags {
+	union {
+		uint32_t raw;
+		struct {
+			uint32_t EMULATE_REPLUG_ON_CAP_CHANGE:1;
+			uint32_t SUPPORT_XRBIAS:1;
+			uint32_t SKIP_POWER_DOWN_ON_RESUME:1;
+			uint32_t FULL_DETECT_ON_RESUME:1;
+			uint32_t GSL_FRAMELOCK:1;
+			uint32_t NO_LOW_BPP_MODES:1;
+			uint32_t BLOCK_ON_INITIAL_DETECTION:1;
+			uint32_t OPTIMIZED_DISPLAY_PROGRAMMING_ON_BOOT:1;
+			uint32_t DRIVER_CONTROLLED_BRIGHTNESS:1;
+			uint32_t MODIFIABLE_FRAME_DURATION:1;
+			uint32_t MIRACAST_SUPPORTED:1;
+			uint32_t CONNECTED_STANDBY_SUPPORTED:1;
+			uint32_t GNB_WAKEUP_SUPPORTED:1;
+		} bits;
+	};
+};
+
+struct hw_asic_id {
+	uint32_t chip_family;
+	uint32_t chip_id;
+	uint32_t pci_revision_id;
+	uint32_t hw_internal_rev;
+	uint32_t vram_type;
+	uint32_t vram_width;
+	uint32_t feature_flags;
+	struct dal_asic_runtime_flags runtime_flags;
+	uint32_t fake_paths_num;
+	void *atombios_base_address;
+};
+
+/* this is pci information. BDF stands for BUS,DEVICE,FUNCTION*/
+
+struct bdf_info {
+	uint16_t BUS_NUMBER:8;
+	uint16_t DEVICE_NUMBER:5;
+	uint16_t FUNCTION_NUMBER:3;
+};
+
+#define DAL_PARAM_INVALID_INT 0x80000000
+
+/* shift values for bool override parameter mask
+ * bmask is for this struct,if we touch this feature
+ * bval indicates every bit fields for this struct too,1 is enable this feature
+ * amdgpu.disp_bval=1594, amdgpu.disp_bmask=1594 ,
+ * finally will show log like this:
+ * Overridden FEATURE_LIGHT_SLEEP is enabled now
+ * Overridden FEATURE_USE_MAX_DISPLAY_CLK is enabled now
+ * Overridden FEATURE_ENABLE_DFS_BYPASS is enabled now
+ * Overridden FEATURE_POWER_GATING_PIPE_IN_TILE is enabled now
+ * Overridden FEATURE_USE_PPLIB is enabled now
+ * Overridden FEATURE_DISABLE_LPT_SUPPORT is enabled now
+ * Overridden FEATURE_DUMMY_FBC_BACKEND is enabled now */
+enum bool_param_shift {
+	DAL_PARAM_MAXIMIZE_STUTTER_MARKS = 0,
+	DAL_PARAM_LIGHT_SLEEP,
+	DAL_PARAM_MAXIMIZE_URGENCY_WATERMARKS,
+	DAL_PARAM_USE_MAX_DISPLAY_CLK,
+	DAL_PARAM_ENABLE_DFS_BYPASS,
+	DAL_PARAM_POWER_GATING_PIPE_IN_TILE,
+	DAL_PARAM_POWER_GATING_LB_PORTION,
+	DAL_PARAM_PSR_ENABLE,
+	DAL_PARAM_VARI_BRIGHT_ENABLE,
+	DAL_PARAM_USE_PPLIB,
+	DAL_PARAM_DISABLE_LPT_SUPPORT,
+	DAL_PARAM_DUMMY_FBC_BACKEND,
+	DAL_PARAM_ENABLE_GPU_SCALING,
+	DAL_BOOL_PARAM_MAX
+};
+
+/* array index for integer override parameters*/
+enum int_param_array_index {
+	DAL_PARAM_MAX_COFUNC_NON_DP_DISPLAYS = 0,
+	DAL_PARAM_DRR_SUPPORT,
+	DAL_INT_PARAM_MAX
+};
+
+struct dal_override_parameters {
+	uint32_t bool_param_enable_mask;
+	uint32_t bool_param_values;
+	uint32_t int_param_values[DAL_INT_PARAM_MAX];
+};
+
+
+struct dal_init_data {
+	struct hw_asic_id asic_id;
+	struct view_port_alignment vp_alignment;
+	struct bdf_info bdf_info;
+	struct dal_override_parameters display_param;
+	void *driver; /* dal_context */
+	void *cgs_device;
+};
+
+
+struct dal_dev_c_lut {
+	uint8_t red;
+	uint8_t green;
+	uint8_t blue;
+	uint8_t reserved;
+};
+
+struct dal_dev_gamma_lut {
+	uint16_t red;
+	uint16_t green;
+	uint16_t blue;
+};
+
+struct dal_context {
+	void *driver_context; /* e.g. amdgpu_device */
+	struct dal_logger *logger;
+	void *cgs_device;
+};
+
+/* Wireless display structs */
+
+union dal_remote_display_cea_mode_bitmap {
+	struct {
+		uint32_t CEA_640X480_60P:1;/*0*/
+		uint32_t CEA_720X480_60P:1;/*1*/
+		uint32_t CEA_720X480_60I:1;/*2*/
+		uint32_t CEA_720X576_50P:1;/*3*/
+		uint32_t CEA_720X576_50I:1;/*4*/
+		uint32_t CEA_1280X720_30P:1;/*5*/
+		uint32_t CEA_1280X720_60P:1;/*6*/
+		uint32_t CEA_1920X1080_30P:1;/*7*/
+		uint32_t CEA_1920X1080_60P:1;/*8*/
+		uint32_t CEA_1920X1080_60I:1;/*9*/
+		uint32_t CEA_1280X720_25P:1;/*10*/
+		uint32_t CEA_1280X728_50P:1;/*11*/
+		uint32_t CEA_1920X1080_25P:1;/*12*/
+		uint32_t CEA_1920X1080_50P:1;/*13*/
+		uint32_t CEA_1920X1080_50I:1;/*14*/
+		uint32_t CEA_1280X1024_24P:1;/*15*/
+		uint32_t CEA_1920X1080_24P:1;/*16*/
+		uint32_t RESERVED:15;/*[17-31]*/
+	} flags;
+	uint32_t raw;
+};
+
+union dal_remote_display_vesa_mode_bitmap {
+	struct {
+		uint32_t VESA_800X600_30P:1;/*0*/
+		uint32_t VESA_800X600_60P:1;/*1*/
+		uint32_t VESA_1024X768_30P:1;/*2*/
+		uint32_t VESA_1024X768_60P:1;/*3*/
+		uint32_t VESA_1152X864_30P:1;/*4*/
+		uint32_t VESA_1152X864_60P:1;/*5*/
+		uint32_t VESA_1280X768_30P:1;/*6*/
+		uint32_t VESA_1280X768_60P:1;/*7*/
+		uint32_t VESA_1280X800_30P:1;/*8*/
+		uint32_t VESA_1280X800_60P:1;/*9*/
+		uint32_t VESA_1360X768_30P:1;/*10*/
+		uint32_t VESA_1360X768_60P:1;/*11*/
+		uint32_t VESA_1366X768_30P:1;/*12*/
+		uint32_t VESA_1366X768_60P:1;/*13*/
+		uint32_t VESA_1280X1024_30P:1;/*14*/
+		uint32_t VESA_1280X1024_60P:1;/*15*/
+		uint32_t VESA_1400X1050_30P:1;/*16*/
+		uint32_t VESA_1400X1050_60P:1;/*17*/
+		uint32_t VESA_1440X900_30P:1;/*18*/
+		uint32_t VESA_1440X900_60P:1;/*19*/
+		uint32_t VESA_1600X900_30P:1;/*20*/
+		uint32_t VESA_1600X900_60P:1;/*21*/
+		uint32_t VESA_1600X1200_30P:1;/*22*/
+		uint32_t VESA_1600X1200_60P:1;/*23*/
+		uint32_t VESA_1680X1024_30P:1;/*24*/
+		uint32_t VESA_1680X1024_60P:1;/*25*/
+		uint32_t VESA_1680X1050_30P:1;/*26*/
+		uint32_t VESA_1680X1050_60P:1;/*27*/
+		uint32_t VESA_1920X1200_30P:1;/*28*/
+		uint32_t VESA_1920X1200_60P:1;/*29*/
+		uint32_t RESERVED:2;/*[30-31]*/
+	} flags;
+	uint32_t raw;
+};
+
+union dal_remote_display_hh_mode_bitmap {
+	struct {
+		uint32_t HH_800X480_30P:1;/*0*/
+		uint32_t HH_800X480_60P:1;/*1*/
+		uint32_t HH_854X480_30P:1;/*2*/
+		uint32_t HH_854X480_60P:1;/*3*/
+		uint32_t HH_864X480_30P:1;/*4*/
+		uint32_t HH_864X480_60P:1;/*5*/
+		uint32_t HH_640X360_30P:1;/*6*/
+		uint32_t HH_640X360_60P:1;/*7*/
+		uint32_t HH_960X540_30P:1;/*8*/
+		uint32_t HH_960X540_60P:1;/*9*/
+		uint32_t HH_848X480_30P:1;/*10*/
+		uint32_t HH_848X480_60P:1;/*11*/
+		uint32_t RESERVED:20;/*[12-31]*/
+	} flags;
+	uint32_t raw;
+};
+
+union dal_remote_display_stereo_3d_mode_bitmap {
+	struct {
+		uint32_t STEREO_1920X1080_24P_TOP_AND_BOTTOM:1;/*0*/
+		uint32_t STEREO_1280X720_60P_TOP_AND_BOTTOM:1;/*1*/
+		uint32_t STEREO_1280X720_50P_TOP_AND_BOTTOM:1;/*2*/
+		uint32_t STEREO_1920X1080_24X2P_FRAME_ALTERNATE:1;/*3*/
+		uint32_t STEREO_1280X720_60X2P_FRAME_ALTERNATE:1;/*4*/
+		uint32_t STEREO_1280X720_30X2P_FRAME_ALTERNATE:1;/*5*/
+		uint32_t STEREO_1280X720_50X2P_FRAME_ALTERNATE:1;/*6*/
+		uint32_t STEREO_1280X720_25X2P_FRAME_ALTERNATE:1;/*7*/
+		uint32_t STEREO_1920X1080_24P_FRAME_PACKING:1;/* 8*/
+		uint32_t STEREO_1280X720_60P_FRAME_PACKING:1;/* 9*/
+		uint32_t STEREO_1280X720_30P_FRAME_PACKING:1;/*10*/
+		uint32_t STEREO_1280X720_50P_FRAME_PACKING:1;/*11*/
+		uint32_t STEREO_1280X720_25P_FRAME_PACKING:1;/*12*/
+		uint32_t RESERVED:19; /*[13-31]*/
+	} flags;
+	uint32_t raw;
+};
+
+union dal_remote_display_audio_bitmap {
+	struct {
+		uint32_t LPCM_44100HZ_16BITS_2_CHANNELS:1;/*0*/
+		uint32_t LPCM_48000HZ_16BITS_2_CHANNELS:1;/*1*/
+		uint32_t AAC_48000HZ_16BITS_2_CHANNELS:1;/*2*/
+		uint32_t AAC_48000HZ_16BITS_4_CHANNELS:1;/*3*/
+		uint32_t AAC_48000HZ_16BITS_6_CHANNELS:1;/*4*/
+		uint32_t AAC_48000HZ_16BITS_8_CHANNELS:1;/*5*/
+		uint32_t AC3_48000HZ_16BITS_2_CHANNELS:1;/*6*/
+		uint32_t AC3_48000HZ_16BITS_4_CHANNELS:1;/*7*/
+		uint32_t AC3_48000HZ_16BITS_6_CHANNELS:1;/*8*/
+		uint32_t RESERVED:23;/*[9-31]*/
+	} flags;
+	uint32_t raw;
+};
+
+struct dal_remote_display_receiver_capability {
+	union dal_remote_display_cea_mode_bitmap cea_mode;
+	union dal_remote_display_vesa_mode_bitmap vesa_mode;
+	union dal_remote_display_hh_mode_bitmap hh_mode;
+	union dal_remote_display_stereo_3d_mode_bitmap stereo_3d_mode;
+	union dal_remote_display_audio_bitmap audio;
+};
+
+#endif /* __DAL_TYPES_H__ */
diff --git a/drivers/gpu/drm/amd/dal/include/flat_set.h b/drivers/gpu/drm/amd/dal/include/flat_set.h
new file mode 100644
index 000000000000..56fbfe4093a5
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/include/flat_set.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_FLAT_SET_H__
+#define __DAL_FLAT_SET_H__
+
+#include "vector.h"
+
+struct flat_set_funcs {
+	bool (*less_than)(const void *lhs, const void *rhs);
+};
+
+struct flat_set {
+	struct vector vector;
+	struct flat_set_funcs funcs;
+};
+
+struct flat_set_init_data {
+	uint32_t capacity;
+	uint32_t struct_size;
+	struct flat_set_funcs funcs;
+};
+
+struct flat_set *dal_flat_set_create(
+		const struct flat_set_init_data *init_data);
+
+bool dal_flat_set_construct(
+		struct flat_set *flat_set,
+		const struct flat_set_init_data *init_data);
+
+void dal_flat_set_destruct(struct flat_set *set);
+
+void dal_flat_set_destroy(struct flat_set **flat_set);
+
+
+/* dal_flat_set_insert()
+ * check if container already holds such element
+ * if not, insert it keeping underlying vector sorted
+ * according to less_then function.
+ * Insertion implemented by container methods
+ * refer to dal_vector_insert
+ * It will return either newly inserted elem or elem that was already isnerted
+ * and satisfied less_then function. In case of error NULL is returned */
+void *dal_flat_set_insert(
+		struct flat_set *flat_set,
+		const void *what);
+
+
+/* dal_flat_set_search()
+ * return pointer to found item, NULL otherwise
+ * write a value of index to memory pointed by index if found
+ * write a position in underlying vector where to insert new element
+ * to keep vector sorted*/
+void *dal_flat_set_search(
+		const struct flat_set *flat_set,
+		const void *what,
+		uint32_t *index);
+
+uint32_t dal_flat_set_get_count(const struct flat_set *flat_set);
+
+
+/* dal_flat_set_at_index()
+ * return address of container's memory where an item of provided index is*/
+void *dal_flat_set_at_index(const struct flat_set *fs, uint32_t index);
+
+bool dal_flat_set_remove_at_index(struct flat_set *fs, uint32_t index);
+
+uint32_t dal_flat_set_capacity(const struct flat_set *fs);
+
+bool dal_flat_set_reserve(struct flat_set *fs, uint32_t capacity);
+
+void dal_flat_set_clear(struct flat_set *fs);
+
+#define DAL_FLAT_SET_INSERT(flat_set_type, type_t) \
+static type_t flat_set_type##_set_insert(\
+	struct flat_set *set,\
+	type_t what)\
+{\
+	return dal_flat_set_insert(set, what);\
+}
+
+#define DAL_FLAT_SET_AT_INDEX(flat_set_type, type_t) \
+static type_t flat_set_type##_set_at_index(\
+	struct flat_set *set,\
+	uint32_t index)\
+{\
+	return dal_flat_set_at_index(set, index);\
+}
+
+#endif /* __DAL_FLAT_SET_H__ */
diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
new file mode 100644
index 000000000000..9f1060a0922e
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
@@ -0,0 +1,616 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_GRPH_OBJECT_CTRL_DEFS_H__
+#define __DAL_GRPH_OBJECT_CTRL_DEFS_H__
+
+#include "grph_object_defs.h"
+
+/*
+ * #####################################################
+ * #####################################################
+ *
+ * These defines shared between asic_control/bios_parser and other
+ * DAL components
+ *
+ * #####################################################
+ * #####################################################
+ */
+
+enum tv_standard {
+	TV_STANDARD_UNKNOWN = 0, /* direct HW (mmBIOS_SCRATCH_2) translation! */
+	TV_STANDARD_NTSC,
+	TV_STANDARD_NTSCJ,
+	TV_STANDARD_PAL,
+	TV_STANDARD_PALM,
+	TV_STANDARD_PALCN,
+	TV_STANDARD_PALN,
+	TV_STANDARD_PAL60,
+	TV_STANDARD_SECAM
+};
+
+enum cv_standard {
+	CV_STANDARD_UNKNOWN = 0x0000,
+	CV_STANDARD_HD_MASK = 0x0800,		/* Flag mask HDTV output */
+	CV_STANDARD_SD_NTSC_MASK = 0x1000,	/* Flag mask NTSC output */
+	CV_STANDARD_SD_NTSC_M,		/* NTSC (North America) output 1001 */
+	CV_STANDARD_SD_NTSC_J,		/* NTSC (Japan) output 1002 */
+	CV_STANDARD_SD_480I,		/* SDTV 480i output 1003 */
+	CV_STANDARD_SD_480P,		/* SDTV 480p output 1004 */
+	CV_STANDARD_HD_720_60P = 0x1800,/* HDTV 720/60p output 1800 */
+	CV_STANDARD_HD_1080_60I,	/* HDTV 1080/60i output 1801 */
+	CV_STANDARD_SD_PAL_MASK = 0x2000,/* Flag mask PAL output */
+	CV_STANDARD_SD_PAL_B,			/* PAL B output 2001 */
+	CV_STANDARD_SD_PAL_D,			/* PAL D output 2002 */
+	CV_STANDARD_SD_PAL_G,			/* PAL G output 2003 */
+	CV_STANDARD_SD_PAL_H,			/* PAL H output 2004 */
+	CV_STANDARD_SD_PAL_I,			/* PAL I output 2005 */
+	CV_STANDARD_SD_PAL_M,			/* PAL M output 2006 */
+	CV_STANDARD_SD_PAL_N,			/* PAL N output 2007 */
+	CV_STANDARD_SD_PAL_N_COMB,	/* PAL Combination N output 2008 */
+	CV_STANDARD_SD_PAL_60,		/* PAL 60 output (test mode) 2009 */
+	CV_STANDARD_SD_576I,		/* SDTV 576i output 2010 */
+	CV_STANDARD_SD_576P,		/* SDTV 576p output 2011 */
+	CV_STANDARD_HD_720_50P = 0x2800,/* HDTV 720/50p output 2800 */
+	CV_STANDARD_HD_1080_50I,	/* HDTV 1080/50i output 2801 */
+	CV_STANDARD_SD_SECAM_MASK = 0x4000, /* Flag mask SECAM output */
+	CV_STANDARD_SD_SECAM_B,		/* SECAM B output 4001 */
+	CV_STANDARD_SD_SECAM_D,		/* SECAM D output 4002 */
+	CV_STANDARD_SD_SECAM_G,		/* SECAM G output 4003 */
+	CV_STANDARD_SD_SECAM_H,		/* SECAM H output 4004 */
+	CV_STANDARD_SD_SECAM_K,		/* SECAM K output 4005 */
+	CV_STANDARD_SD_SECAM_K1,	/* SECAM K1 output 4006 */
+	CV_STANDARD_SD_SECAM_L,		/* SECAM L output 4007 */
+	CV_STANDARD_SD_SECAM_L1		/* SECAM L1 output 4009 */
+};
+
+enum disp_pll_config {
+	DISP_PLL_CONFIG_UNKNOWN = 0,
+	DISP_PLL_CONFIG_DVO_DDR_MODE_LOW_12BIT,
+	DISP_PLL_CONFIG_DVO_DDR_MODE_UPPER_12BIT,
+	DISP_PLL_CONFIG_DVO_DDR_MODE_24BIT
+};
+
+enum transmitter_color_depth {
+	TRANSMITTER_COLOR_DEPTH_24 = 0,	/* 8 bits */
+	TRANSMITTER_COLOR_DEPTH_30,	/* 10 bits */
+	TRANSMITTER_COLOR_DEPTH_36,	/* 12 bits */
+	TRANSMITTER_COLOR_DEPTH_48	/* 16 bits */
+};
+
+enum display_output_bit_depth {
+	PANEL_UNDEFINE = 0,
+	PANEL_6BIT_COLOR = 1,
+	PANEL_8BIT_COLOR = 2,
+	PANEL_10BIT_COLOR = 3,
+	PANEL_12BIT_COLOR = 4,
+	PANEL_16BIT_COLOR = 5,
+};
+
+/* Color depth of DP transmitter */
+enum dp_transmitter_color_depth {
+	DP_TRANSMITTER_COLOR_DEPTH_UNKNOWN = 0,
+	DP_TRANSMITTER_COLOR_DEPTH_666,
+	DP_TRANSMITTER_COLOR_DEPTH_888,
+	DP_TRANSMITTER_COLOR_DEPTH_101010,
+	DP_TRANSMITTER_COLOR_DEPTH_121212,
+	DP_TRANSMITTER_COLOR_DEPTH_141414,
+	DP_TRANSMITTER_COLOR_DEPTH_161616
+};
+
+enum lcd_scale {
+	/* No request to turn on LCD SCALER (Centering or Replication) */
+	LCD_SCALE_NONE = 0,
+	/* Request LCD SCALER in full panel mode */
+	LCD_SCALE_FULLPANEL,
+	/* Request LCD SCALER in aspect-ratio mode */
+	LCD_SCALE_ASPECTRATIO,
+
+	LCD_SCALE_UNKNOWN = (-1L),
+};
+
+/* Device type as abstracted by ATOM BIOS */
+enum dal_device_type {
+	DEVICE_TYPE_UNKNOWN = 0,
+	DEVICE_TYPE_LCD,
+	DEVICE_TYPE_CRT,
+	DEVICE_TYPE_DFP,
+	DEVICE_TYPE_CV,
+	DEVICE_TYPE_TV,
+	DEVICE_TYPE_CF,
+	DEVICE_TYPE_WIRELESS
+};
+
+/* Device ID as abstracted by ATOM BIOS */
+struct device_id {
+	enum dal_device_type device_type:16;
+	uint32_t enum_id:16;	/* 1 based enum */
+};
+
+struct graphics_object_i2c_info {
+	struct gpio_info {
+		uint32_t clk_mask_register_index;
+		uint32_t clk_en_register_index;
+		uint32_t clk_y_register_index;
+		uint32_t clk_a_register_index;
+		uint32_t data_mask_register_index;
+		uint32_t data_en_register_index;
+		uint32_t data_y_register_index;
+		uint32_t data_a_register_index;
+
+		uint32_t clk_mask_shift;
+		uint32_t clk_en_shift;
+		uint32_t clk_y_shift;
+		uint32_t clk_a_shift;
+		uint32_t data_mask_shift;
+		uint32_t data_en_shift;
+		uint32_t data_y_shift;
+		uint32_t data_a_shift;
+	} gpio_info;
+
+	bool i2c_hw_assist;
+	uint32_t i2c_line;
+	uint32_t i2c_engine_id;
+	uint32_t i2c_slave_address;
+};
+
+
+struct graphics_object_hpd_info {
+	uint8_t hpd_int_gpio_uid;
+	uint8_t hpd_active;
+};
+
+struct connector_device_tag_info {
+	uint32_t acpi_device;
+	struct device_id dev_id;
+};
+
+struct device_timing {
+	struct misc_info {
+		uint32_t HORIZONTAL_CUT_OFF:1;
+		/* 0=Active High, 1=Active Low */
+		uint32_t H_SYNC_POLARITY:1;
+		/* 0=Active High, 1=Active Low */
+		uint32_t V_SYNC_POLARITY:1;
+		uint32_t VERTICAL_CUT_OFF:1;
+		uint32_t H_REPLICATION_BY2:1;
+		uint32_t V_REPLICATION_BY2:1;
+		uint32_t COMPOSITE_SYNC:1;
+		uint32_t INTERLACE:1;
+		uint32_t DOUBLE_CLOCK:1;
+		uint32_t RGB888:1;
+		uint32_t GREY_LEVEL:2;
+		uint32_t SPATIAL:1;
+		uint32_t TEMPORAL:1;
+		uint32_t API_ENABLED:1;
+	} misc_info;
+
+	uint32_t pixel_clk; /* in KHz */
+	uint32_t horizontal_addressable;
+	uint32_t horizontal_blanking_time;
+	uint32_t vertical_addressable;
+	uint32_t vertical_blanking_time;
+	uint32_t horizontal_sync_offset;
+	uint32_t horizontal_sync_width;
+	uint32_t vertical_sync_offset;
+	uint32_t vertical_sync_width;
+	uint32_t horizontal_border;
+	uint32_t vertical_border;
+};
+
+struct supported_refresh_rate {
+	uint32_t REFRESH_RATE_30HZ:1;
+	uint32_t REFRESH_RATE_40HZ:1;
+	uint32_t REFRESH_RATE_48HZ:1;
+	uint32_t REFRESH_RATE_50HZ:1;
+	uint32_t REFRESH_RATE_60HZ:1;
+};
+
+struct embedded_panel_info {
+	struct device_timing lcd_timing;
+	uint32_t ss_id;
+	struct supported_refresh_rate supported_rr;
+	uint32_t drr_enabled;
+	uint32_t min_drr_refresh_rate;
+};
+
+struct embedded_panel_patch_mode {
+	uint32_t width;
+	uint32_t height;
+};
+
+struct firmware_info {
+	struct pll_info {
+		uint32_t crystal_frequency; /* in KHz */
+		uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */
+		uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */
+		uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */
+		uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */
+	} pll_info;
+
+	struct firmware_feature {
+		uint32_t memory_clk_ss_percentage;
+		uint32_t engine_clk_ss_percentage;
+	} feature;
+
+	uint32_t default_display_engine_pll_frequency; /* in KHz */
+	uint32_t external_clock_source_frequency_for_dp; /* in KHz */
+	uint32_t smu_gpu_pll_output_freq; /* in KHz */
+	uint8_t min_allowed_bl_level;
+	uint8_t remote_display_config;
+};
+
+/* direct HW (mmBIOS_SCRATCH_2) translation! */
+union tv_standard_support {
+	uint8_t u_all;
+	struct {
+		bool TV_SUPPORT_NTSC:1;
+		bool TV_SUPPORT_NTSCJ:1;
+
+		bool TV_SUPPORT_PAL:1;
+		bool TV_SUPPORT_PALM:1;
+		bool TV_SUPPORT_PALCN:1;
+		bool TV_SUPPORT_PALN:1;
+		bool TV_SUPPORT_PAL60:1;
+
+		bool TV_SUPPORT_SECAM:1;
+	} bits;
+};
+
+struct analog_tv_info {
+	union tv_standard_support tv_suppported;
+	union tv_standard_support tv_boot_up_default;
+};
+
+struct spread_spectrum_info {
+	struct spread_spectrum_type {
+		bool CENTER_MODE:1;
+		bool EXTERNAL:1;
+		bool STEP_AND_DELAY_INFO:1;
+	} type;
+
+	/* in unit of 0.01% (spreadPercentageDivider = 100),
+	otherwise in 0.001% units (spreadPercentageDivider = 1000); */
+	uint32_t spread_spectrum_percentage;
+	uint32_t spread_percentage_divider; /* 100 or 1000 */
+	uint32_t spread_spectrum_range; /* modulation freq (HZ)*/
+
+	union {
+		struct step_and_delay_info {
+			uint32_t step;
+			uint32_t delay;
+			uint32_t recommended_ref_div;
+		} step_and_delay_info;
+		/* For mem/engine/uvd, Clock Out frequence (VCO ),
+		in unit of kHz. For TMDS/HDMI/LVDS, it is pixel clock,
+		for DP, it is link clock ( 270000 or 162000 ) */
+		uint32_t target_clock_range; /* in KHz */
+	};
+
+};
+
+struct graphics_object_encoder_cap_info {
+	uint32_t dp_hbr2_cap:1;
+	uint32_t dp_hbr2_validated:1;
+	uint32_t reserved:15;
+};
+
+struct din_connector_info {
+	uint32_t gpio_id;
+	bool gpio_tv_active_state;
+};
+
+/* Invalid channel mapping */
+enum { INVALID_DDI_CHANNEL_MAPPING = 0x0 };
+
+/**
+ * DDI PHY channel mapping reflecting XBAR setting
+ */
+union ddi_channel_mapping {
+	struct mapping {
+		uint8_t lane0:2;	/* Mapping for lane 0 */
+		uint8_t lane1:2;	/* Mapping for lane 1 */
+		uint8_t lane2:2;	/* Mapping for lane 2 */
+		uint8_t lane3:2;	/* Mapping for lane 3 */
+	} mapping;
+	uint8_t raw;
+};
+
+/**
+* Transmitter output configuration description
+*/
+struct transmitter_configuration_info {
+	/* DDI PHY ID for the transmitter */
+	enum transmitter transmitter_phy_id;
+	/* DDI PHY channel mapping reflecting crossbar setting */
+	union ddi_channel_mapping output_channel_mapping;
+};
+
+struct transmitter_configuration {
+	/* Configuration for the primary transmitter */
+	struct transmitter_configuration_info primary_transmitter_config;
+	/* Secondary transmitter configuration for Dual-link DVI */
+	struct transmitter_configuration_info secondary_transmitter_config;
+};
+
+
+/* These size should be sufficient to store info coming from BIOS */
+#define NUMBER_OF_UCHAR_FOR_GUID 16
+#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
+#define NUMBER_OF_CSR_M3_ARB 10
+#define NUMBER_OF_DISP_CLK_VOLTAGE 4
+#define NUMBER_OF_AVAILABLE_SCLK 5
+
+/* V6 */
+struct integrated_info {
+	struct clock_voltage_caps {
+		/* The Voltage Index indicated by FUSE, same voltage index
+		shared with SCLK DPM fuse table */
+		uint32_t voltage_index;
+		/* Maximum clock supported with specified voltage index */
+		uint32_t max_supported_clk; /* in KHz */
+	} disp_clk_voltage[NUMBER_OF_DISP_CLK_VOLTAGE];
+
+	struct display_connection_info {
+		struct external_display_path {
+			/* A bit vector to show what devices are supported */
+			uint32_t device_tag;
+			/* 16bit device ACPI id. */
+			uint32_t device_acpi_enum;
+			/* A physical connector for displays to plug in,
+			using object connector definitions */
+			struct graphics_object_id device_connector_id;
+			/* An index into external AUX/DDC channel LUT */
+			uint8_t ext_aux_ddc_lut_index;
+			/* An index into external HPD pin LUT */
+			uint8_t ext_hpd_pin_lut_index;
+			/* external encoder object id */
+			struct graphics_object_id ext_encoder_obj_id;
+			/* XBAR mapping of the PHY channels */
+			union ddi_channel_mapping channel_mapping;
+		} path[MAX_NUMBER_OF_EXT_DISPLAY_PATH];
+
+		uint8_t gu_id[NUMBER_OF_UCHAR_FOR_GUID];
+		uint8_t checksum;
+	} ext_disp_conn_info; /* exiting long long time */
+
+	struct available_s_clk_list {
+		/* Maximum clock supported with specified voltage index */
+		uint32_t supported_s_clk; /* in KHz */
+		/* The Voltage Index indicated by FUSE for specified SCLK */
+		uint32_t voltage_index;
+		/* The Voltage ID indicated by FUSE for specified SCLK */
+		uint32_t voltage_id;
+	} avail_s_clk[NUMBER_OF_AVAILABLE_SCLK];
+
+	uint8_t memory_type;
+	uint8_t ma_channel_number;
+	uint32_t boot_up_engine_clock; /* in KHz */
+	uint32_t dentist_vco_freq; /* in KHz */
+	uint32_t boot_up_uma_clock; /* in KHz */
+	uint32_t boot_up_req_display_vector;
+	uint32_t other_display_misc;
+	uint32_t gpu_cap_info;
+	uint32_t sb_mmio_base_addr;
+	uint32_t system_config;
+	uint32_t cpu_cap_info;
+	uint32_t max_nb_voltage;
+	uint32_t min_nb_voltage;
+	uint32_t boot_up_nb_voltage;
+	uint32_t ext_disp_conn_info_offset;
+	uint32_t csr_m3_arb_cntl_default[NUMBER_OF_CSR_M3_ARB];
+	uint32_t csr_m3_arb_cntl_uvd[NUMBER_OF_CSR_M3_ARB];
+	uint32_t csr_m3_arb_cntl_fs3d[NUMBER_OF_CSR_M3_ARB];
+	uint32_t gmc_restore_reset_time;
+	uint32_t minimum_n_clk;
+	uint32_t idle_n_clk;
+	uint32_t ddr_dll_power_up_time;
+	uint32_t ddr_pll_power_up_time;
+	/* start for V6 */
+	uint32_t pcie_clk_ss_type;
+	uint32_t lvds_ss_percentage;
+	uint32_t lvds_sspread_rate_in_10hz;
+	uint32_t hdmi_ss_percentage;
+	uint32_t hdmi_sspread_rate_in_10hz;
+	uint32_t dvi_ss_percentage;
+	uint32_t dvi_sspread_rate_in_10_hz;
+	uint32_t sclk_dpm_boost_margin;
+	uint32_t sclk_dpm_throttle_margin;
+	uint32_t sclk_dpm_tdp_limit_pg;
+	uint32_t sclk_dpm_tdp_limit_boost;
+	uint32_t boost_engine_clock;
+	uint32_t boost_vid_2bit;
+	uint32_t enable_boost;
+	uint32_t gnb_tdp_limit;
+	/* Start from V7 */
+	uint32_t max_lvds_pclk_freq_in_single_link;
+	uint32_t lvds_misc;
+	uint32_t lvds_pwr_on_seq_dig_on_to_de_in_4ms;
+	uint32_t lvds_pwr_on_seq_de_to_vary_bl_in_4ms;
+	uint32_t lvds_pwr_off_seq_vary_bl_to_de_in4ms;
+	uint32_t lvds_pwr_off_seq_de_to_dig_on_in4ms;
+	uint32_t lvds_off_to_on_delay_in_4ms;
+	uint32_t lvds_pwr_on_seq_vary_bl_to_blon_in_4ms;
+	uint32_t lvds_pwr_off_seq_blon_to_vary_bl_in_4ms;
+	uint32_t lvds_reserved1;
+	uint32_t lvds_bit_depth_control_val;
+};
+
+/**
+* Power source ids.
+*/
+enum power_source {
+	POWER_SOURCE_AC = 0,
+	POWER_SOURCE_DC,
+	POWER_SOURCE_LIMITED_POWER,
+	POWER_SOURCE_LIMITED_POWER_2,
+	POWER_SOURCE_MAX
+};
+
+struct bios_event_info {
+	uint32_t thermal_state;
+	uint32_t backlight_level;
+	enum power_source powerSource;
+	bool has_thermal_state_changed;
+	bool has_power_source_changed;
+	bool has_forced_mode_changed;
+	bool forced_mode;
+	bool backlight_changed;
+};
+
+union stereo_3d_support {
+	struct {
+		/* HW can alter left and right image sequentially */
+		uint32_t FRAME_ALTERNATE:1;
+		/* Frame Alternate + HW can integrate stereosync
+		signal into TMDS stream */
+		uint32_t DVI_FRAME_ALT:1;
+		/* Frame Alternate + HW can integrate stereosync
+		signal into DP stream */
+		uint32_t DISPLAY_PORT_FRAME_ALT:1;
+		/* Frame Alternate + HW can drive stereosync signal
+		on separate line */
+		uint32_t SIDEBAND_FRAME_ALT:1;
+		/* SW allowed to pack left and right image into single frame.
+		Used for HDMI only, DP has it's own flags. */
+		uint32_t SW_FRAME_PACK:1;
+		/* HW can pack left and right image into single HDMI frame */
+		uint32_t PROGRESSIVE_FRAME_PACK:1;
+		/* HW can pack left and right interlaced images into
+		single HDMI frame */
+		uint32_t INTERLACE_FRAME_PACK:1;
+		/* HW can pack left and right images into single DP frame */
+		uint32_t DISPLAY_PORT_FRAME_PACK:1;
+		/* SW can pack left and right images into single DP frame */
+		uint32_t DISPLAY_PORT_SW_FRAME_PACK:1;
+		/* HW can mix left and right images into single image */
+		uint32_t INTERLEAVE:1;
+		/* HW can mix left and right interlaced images
+		into single image */
+		uint32_t INTERLACE_INTERLEAVE:1;
+		/* Allow display-based formats (whatever supported)
+		in WS stereo mode */
+		uint32_t DISPLAY_3DIN_WS_MODE:1;
+		/* Side-by-side, packed by application/driver into 2D frame */
+		uint32_t SIDE_BY_SIDE_SW_PACKED:1;
+		/* Top-and-bottom, packed by application/driver into 2D frame */
+		uint32_t TOP_AND_BOTTOM_SW_PACKED:1;
+	} bits;
+	uint32_t u_all;
+};
+
+/* Bitvector and bitfields of possible optimizations
+ #IMPORTANT# Keep bitfields match bitvector! */
+enum optimization_feature {
+	/* Don't do HW programming on panels that were enabled by VBIOS */
+	OF_SKIP_HW_PROGRAMMING_ON_ENABLED_EMBEDDED_DISPLAY = 0x1,
+	OF_SKIP_RESET_OF_ALL_HW_ON_S3RESUME = 0x2,
+	OF_SKIP_HW_RESET_OF_EMBEDDED_DISPLAY_ON_S3RESUME = 0x4,
+	OF_SKIP_POWER_UP_VBIOS_ENABLED_ENCODER = 0x8,
+	/* Do not turn off VCC while powering down on boot or resume */
+	OF_KEEP_VCC_DURING_POWER_DOWN_ON_BOOT_OR_RESUME = 0x10,
+	/* Do not turn off VCC while performing SetMode */
+	OF_KEEP_VCC_DURING_SET_MODE = 0x20,
+	OF_DO_NOT_WAIT_FOR_HPD_LOW = 0x40,
+	OF_SKIP_POWER_DOWN_INACTIVE_ENCODER = 0x80
+};
+
+union optimization_flags {
+	struct {
+		/* Don't do HW programming if panels were enabled by VBIOS */
+		uint32_t SKIP_HW_PROGRAMMING_ON_ENABLED_EMBEDDED_DISPLAY:1;
+		uint32_t SKIP_RESET_OF_ALL_HW_ON_S3RESUME:1;
+		uint32_t SKIP_HW_RESET_OF_EMBEDDED_DISPLAY_ON_S3RESUME:1;
+		uint32_t SKIP_POWER_UP_VBIOS_ENABLED_ENCODER:1;
+		/* Do not turn off VCC while powering down on boot or resume */
+		uint32_t KEEP_VCC_DURING_POWER_DOWN_ON_BOOT_OR_RESUME:1;
+		/* Do not turn off VCC while performing SetMode */
+		uint32_t KEEP_VCC_DURING_SET_MODE:1;
+		uint32_t DO_NOT_WAIT_FOR_HPD_LOW:1;
+	} bits;
+	uint32_t u_all;
+};
+
+/* Bitvector and bitfields of performance measurements
+ #IMPORTANT# Keep bitfields match bitvector! */
+enum perf_measure {
+	PERF_MEASURE_ADAPTER_POWER_STATE = 0x1,
+	PERF_MEASURE_DISPLAY_POWER_STATE = 0x2,
+	PERF_MEASURE_SET_MODE_SEQ = 0x4,
+	PERF_MEASURE_DETECT_AT_RESUME = 0x8,
+	PERF_MEASURE_MEMORY_READ_CONTROL = 0x10,
+};
+
+union perf_measure_flags {
+	struct {
+		uint32_t ADAPTER_POWER_STATE:1;
+		uint32_t DISPLAY_POWER_STATE:1;
+		uint32_t SET_MODE_SEQ:1;
+		uint32_t DETECT_AT_RESUME:1;
+		uint32_t MEMORY_READ_CONTROL:1;
+
+	} bits;
+	uint32_t u_all;
+};
+
+enum {
+	PERF_MEASURE_POWERCODE_OFFSET = 0x0,
+	PERF_MEASURE_POWER_CODE_MASK = 0xFF,
+	PERF_MEASURE_POWER_STATE_OFFSET = 8,
+	PERF_MEASURE_POWER_STATE_MASK = 0x000FF00,
+	PERF_MEASURE_PREV_POWER_STATE_OFFSET = 16,
+	PERF_MEASURE_PREV_POWER_STATE_MASK = 0x00FF0000,
+	PERF_MEASURE_DISPLAY_INDEX_OFFSET = 24,
+	PERF_MEASURE_DISPLAY_INDEX_MASK = 0xFF000000
+};
+
+enum {
+	HDMI_PIXEL_CLOCK_IN_KHZ_297 = 297000,
+	TMDS_PIXEL_CLOCK_IN_KHZ_165 = 165000
+};
+
+/*
+ * DFS-bypass flag
+ */
+/* Copy of SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS from atombios.h */
+enum {
+	DFS_BYPASS_ENABLE = 0x10
+};
+
+enum {
+	INVALID_BACKLIGHT = -1
+};
+
+struct panel_backlight_boundaries {
+	uint32_t min_signal_level;
+	uint32_t max_signal_level;
+};
+
+struct panel_backlight_default_levels {
+	uint32_t ac_level_percentage;
+	uint32_t dc_level_percentage;
+};
+
+#endif
diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_defs.h
new file mode 100644
index 000000000000..8ad93857b6b9
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/include/grph_object_defs.h
@@ -0,0 +1,318 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_GRPH_OBJECT_DEFS_H__
+#define __DAL_GRPH_OBJECT_DEFS_H__
+
+#include "grph_object_id.h"
+
+/* ********************************************************************
+ * ********************************************************************
+ *
+ *  These defines shared between All Graphics Objects
+ *
+ * ********************************************************************
+ * ********************************************************************
+ */
+
+/* HPD unit id - HW direct translation */
+enum hpd_source_id {
+	HPD_SOURCEID1 = 0,
+	HPD_SOURCEID2,
+	HPD_SOURCEID3,
+	HPD_SOURCEID4,
+	HPD_SOURCEID5,
+	HPD_SOURCEID6,
+
+	HPD_SOURCEID_COUNT,
+	HPD_SOURCEID_UNKNOWN
+};
+
+/* DDC unit id - HW direct translation */
+enum channel_id {
+	CHANNEL_ID_UNKNOWN = 0,
+	CHANNEL_ID_DDC1,
+	CHANNEL_ID_DDC2,
+	CHANNEL_ID_DDC3,
+	CHANNEL_ID_DDC4,
+	CHANNEL_ID_DDC5,
+	CHANNEL_ID_DDC6,
+	CHANNEL_ID_DDC_VGA,
+	CHANNEL_ID_I2C_PAD,
+	CHANNEL_ID_COUNT
+};
+
+enum transmitter {
+	TRANSMITTER_UNKNOWN = (-1L),
+	TRANSMITTER_UNIPHY_A,
+	TRANSMITTER_UNIPHY_B,
+	TRANSMITTER_UNIPHY_C,
+	TRANSMITTER_UNIPHY_D,
+	TRANSMITTER_UNIPHY_E,
+	TRANSMITTER_UNIPHY_F,
+	TRANSMITTER_NUTMEG_CRT,
+	TRANSMITTER_TRAVIS_CRT,
+	TRANSMITTER_TRAVIS_LCD,
+	TRANSMITTER_UNIPHY_G,
+	TRANSMITTER_COUNT
+};
+
+enum physical_phy_id {
+	PHY_ID_UNKNOWN = (-1L),
+	PHY_ID_0,
+	PHY_ID_1,
+	PHY_ID_2,
+	PHY_ID_3,
+	PHY_ID_4,
+	PHY_ID_5,
+	PHY_ID_6,
+	PHY_ID_7,
+	PHY_ID_8,
+	PHY_ID_9,
+	PHY_ID_COUNT
+};
+
+/* Generic source of the synchronisation input/output signal */
+/* Can be used for flow control, stereo sync, timing sync, frame sync, etc */
+enum sync_source {
+	SYNC_SOURCE_NONE = 0,
+
+	/* Source based on controllers */
+	SYNC_SOURCE_CONTROLLER0,
+	SYNC_SOURCE_CONTROLLER1,
+	SYNC_SOURCE_CONTROLLER2,
+	SYNC_SOURCE_CONTROLLER3,
+	SYNC_SOURCE_CONTROLLER4,
+	SYNC_SOURCE_CONTROLLER5,
+
+	/* Source based on GSL group */
+	SYNC_SOURCE_GSL_GROUP0,
+	SYNC_SOURCE_GSL_GROUP1,
+	SYNC_SOURCE_GSL_GROUP2,
+
+	/* Source based on GSL IOs */
+	/* These IOs normally used as GSL input/output */
+	SYNC_SOURCE_GSL_IO_FIRST,
+	SYNC_SOURCE_GSL_IO_GENLOCK_CLOCK = SYNC_SOURCE_GSL_IO_FIRST,
+	SYNC_SOURCE_GSL_IO_GENLOCK_VSYNC,
+	SYNC_SOURCE_GSL_IO_SWAPLOCK_A,
+	SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
+	SYNC_SOURCE_GSL_IO_LAST = SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
+
+	/* Source based on regular IOs */
+	SYNC_SOURCE_IO_FIRST,
+	SYNC_SOURCE_IO_GENERIC_A = SYNC_SOURCE_IO_FIRST,
+	SYNC_SOURCE_IO_GENERIC_B,
+	SYNC_SOURCE_IO_GENERIC_C,
+	SYNC_SOURCE_IO_GENERIC_D,
+	SYNC_SOURCE_IO_GENERIC_E,
+	SYNC_SOURCE_IO_GENERIC_F,
+	SYNC_SOURCE_IO_HPD1,
+	SYNC_SOURCE_IO_HPD2,
+	SYNC_SOURCE_IO_HSYNC_A,
+	SYNC_SOURCE_IO_VSYNC_A,
+	SYNC_SOURCE_IO_HSYNC_B,
+	SYNC_SOURCE_IO_VSYNC_B,
+	SYNC_SOURCE_IO_LAST = SYNC_SOURCE_IO_VSYNC_B,
+
+	/* Misc. flow control sources */
+	SYNC_SOURCE_DUAL_GPU_PIN
+};
+
+enum trigger_edge {
+	TRIGGER_EDGE_RISING = 0,
+	TRIGGER_EDGE_FALLING,
+	TRIGGER_EDGE_BOTH,
+	TRIGGER_EDGE_DEFAULT
+};
+
+/* Parameters to enable CRTC trigger */
+struct trigger_params {
+	enum sync_source source;
+	enum trigger_edge edge;
+};
+
+/* CRTC Static Screen event triggers */
+struct static_screen_events {
+	union {
+		/* event mask to enable/disable various
+		   trigger sources for static screen detection */
+		struct {
+			/* Force event high */
+			uint32_t FRAME_START:1;
+			/* Cursor register change */
+			uint32_t CURSOR_MOVE:1;
+			/* Memory write to any client other than MCIF */
+			uint32_t MEM_WRITE:1;
+			/* Memory write to hit memory region 0 */
+			uint32_t MEM_REGION0_WRITE:1;
+			/* Memory write to hit memory region 1 */
+			uint32_t MEM_REGION1_WRITE:1;
+			/* Memory write to hit memory region 2 */
+			uint32_t MEM_REGION2_WRITE:1;
+			/* Memory write to hit memory region 3 */
+			uint32_t MEM_REGION3_WRITE:1;
+			/* Graphics Surface Update Pending */
+			uint32_t GFX_UPDATE:1;
+			/* Overlay Surface Update Pending */
+			uint32_t OVL_UPDATE:1;
+			/* Compressed surface invalidated in FBC */
+			uint32_t INVALIDATE_FBC_SURFACE:1;
+			/* Register pending update in any double buffered
+			register group in the display pipe
+			(i.e. Blender, DCP, or SCL) */
+			uint32_t REG_PENDING_UPDATE:1;
+			/* Crtc_trig_a: Based on signal from any other CRTC */
+			uint32_t CRTC_TRIG_A:1;
+			/* Crtc_trig_b: Based on signal from any other CRTC */
+			uint32_t CRTC_TRIG_B:1;
+			/* Readback of CRTC nominal vertical count register
+			by driver  indicates that OS may be trying to change
+			mode or contents of the display therefore need to
+			switch to higher refresh rate */
+			uint32_t READBACK_NOMINAL_VERTICAL:1;
+			/* Readback of CRTC dynamic vertical count register
+			by driver  indicates that OS may be trying to change
+			mode or contents of the display therefore need to
+			switch to higher refresh rate */
+			uint32_t READBACK_DYNAMIC_VERTICAL:1;
+			/* Reserved */
+			uint32_t RESERVED:1;
+		} bits;
+		uint32_t u_all;
+	};
+};
+
+
+/*
+ * ***************************************************************
+ * ********************* Register programming sequences ********
+ * ***************************************************************
+ */
+
+/* GPIO/Register access sequences */
+enum io_register_sequence {
+	/* GLSync sequences to access SwapReady & SwapRequest
+	GPIOs - GLSync Connector parameter */
+	IO_REG_SEQUENCE_SWAPREADY_SET = 0,
+	IO_REG_SEQUENCE_SWAPREADY_RESET,
+	IO_REG_SEQUENCE_SWAPREADY_READ,
+	IO_REG_SEQUENCE_SWAPREQUEST_SET,
+	IO_REG_SEQUENCE_SWAPREQUEST_RESET,
+	IO_REG_SEQUENCE_SWAPREQUEST_READ,
+
+	/* Frame synchronization start/stop - display index parameter */
+	IO_REG_SEQUENCE_FRAMELOCK_STOP,
+	IO_REG_SEQUENCE_FRAMELOCK_START,
+
+	/* Flip lock/unlock - GLSync Connector parameter */
+	IO_REG_SEQUENCE_GLOBALSWAP_LOCK,
+	IO_REG_SEQUENCE_GLOBALSWAP_UNLOCK,
+
+	IO_REG_SEQUENCEENUM_MAX
+};
+
+#define IO_REGISTER_SEQUENCE_MAX_LENGTH 5
+
+/*
+ *****************************************************************************
+ *                             struct io_register
+ *****************************************************************************
+ * Generic struct for read/write register or GPIO.
+ * It allows controlling only some bit section of register, rather then the
+ * whole one.
+ * For write operation should be used as following:
+ *   1. data  = READ(Base + RegisterOffset)
+ *   2. data &= ANDMask
+ *   3. data |= ORMask
+ *   4. WRITE(Base + RegisterOffset, data)
+ *
+ * Note: In case of regular register, ANDMask will be typically 0.
+ *	In case of GPIO, ANDMask will have typically all bits set
+ *	except the specific GPIO bit.
+ *
+ * For read operation should be used as following:
+ *   1. data   = READ(Base + RegisterOffset)
+ *   2. data  &= ANDMask
+ *   3. data >>= BitShift
+ *
+ * Note: In case of regular register, ANDMask will be typically 0xFFFFFFFF.
+ *	In case of GPIO, ANDMask will have typically only specific GPIO bit set
+ *
+ * Note: Base Address is not exposed in this structure due to
+ *	security consideration.
+ */
+
+/*
+ * The generic sequence to program/access registers or GPIOs.
+ * There could be 2 types of sequences - read and write.
+ * Read sequence may have 0 or more writes and in the end one read
+ * Write sequence may have 1 or more writes.
+ */
+struct io_reg_sequence {
+	/* Ordered array of register to program */
+	struct {
+		/* Offset of memory mapped register or GPIO */
+		uint32_t register_offset;
+		/* Mask to use at AND operation (Mandatory, comes
+		before OR operation) */
+		uint32_t and_mask;
+		union {
+			/* Mask to use at OR operation (For write
+			sequence only, comes after AND operation) */
+			uint32_t or_mask;
+			/* Number of bits to shift to get the actual value
+			(For read  sequence only, comes after AND operation) */
+			uint32_t bit_shift;
+		};
+	} io_registers[IO_REGISTER_SEQUENCE_MAX_LENGTH];
+
+	uint32_t steps_num; /* Total number of r/w steps in the sequence */
+};
+
+/* Sequence ID - uniqly defines sequence on single adapter */
+struct io_reg_sequence_id {
+	enum io_register_sequence sequence; /* Sequence enumeration Index/ID */
+	union {
+		/* Refers to object to which the sequence applies.*/
+		uint32_t index;
+		uint32_t display_index;
+		uint32_t controller_index;
+		uint32_t glsync_connector_index;
+	};
+};
+
+struct fbc_info {
+	bool fbc_enable;
+	bool lpt_enable;
+};
+
+/* Event to request TM change IRQ registration state */
+struct hotplug_irq_data {
+	bool disable;
+	struct graphics_object_id connector;
+};
+
+#endif
diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_id.h b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
new file mode 100644
index 000000000000..4305cbfebf40
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
@@ -0,0 +1,293 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_GRPH_OBJECT_ID_H__
+#define __DAL_GRPH_OBJECT_ID_H__
+
+/* Types of graphics objects */
+enum object_type {
+	OBJECT_TYPE_UNKNOWN  = 0,
+
+	/* Direct ATOM BIOS translation */
+	OBJECT_TYPE_GPU,
+	OBJECT_TYPE_ENCODER,
+	OBJECT_TYPE_CONNECTOR,
+	OBJECT_TYPE_ROUTER,
+	OBJECT_TYPE_GENERIC,
+
+	/* Driver specific */
+	OBJECT_TYPE_AUDIO,
+	OBJECT_TYPE_CONTROLLER,
+	OBJECT_TYPE_CLOCK_SOURCE,
+	OBJECT_TYPE_ENGINE,
+
+	OBJECT_TYPE_COUNT
+};
+
+/* Enumeration inside one type of graphics objects */
+enum object_enum_id {
+	ENUM_ID_UNKNOWN = 0,
+	ENUM_ID_1,
+	ENUM_ID_2,
+	ENUM_ID_3,
+	ENUM_ID_4,
+	ENUM_ID_5,
+	ENUM_ID_6,
+	ENUM_ID_7,
+
+	ENUM_ID_COUNT
+};
+
+/* Generic object ids */
+enum generic_id {
+	GENERIC_ID_UNKNOWN = 0,
+	GENERIC_ID_MXM_OPM,
+	GENERIC_ID_GLSYNC,
+	GENERIC_ID_STEREO,
+
+	GENERIC_ID_COUNT
+};
+
+/* Controller object ids */
+enum controller_id {
+	CONTROLLER_ID_UNDEFINED = 0,
+	CONTROLLER_ID_D0,
+	CONTROLLER_ID_D1,
+	CONTROLLER_ID_D2,
+	CONTROLLER_ID_D3,
+	CONTROLLER_ID_D4,
+	CONTROLLER_ID_D5,
+	CONTROLLER_ID_UNDERLAY0,
+	CONTROLLER_ID_MAX = CONTROLLER_ID_UNDERLAY0
+};
+
+#define IS_UNDERLAY_CONTROLLER(ctrlr_id) (ctrlr_id >= CONTROLLER_ID_UNDERLAY0)
+
+/*
+ * ClockSource object ids.
+ * We maintain the order matching (more or less) ATOM BIOS
+ * to improve optimized acquire
+ */
+enum clock_source_id {
+	CLOCK_SOURCE_ID_UNDEFINED = 0,
+	CLOCK_SOURCE_ID_PLL0,
+	CLOCK_SOURCE_ID_PLL1,
+	CLOCK_SOURCE_ID_PLL2,
+	CLOCK_SOURCE_ID_EXTERNAL, /* ID (Phy) ref. clk. for DP */
+	CLOCK_SOURCE_ID_DCPLL,
+	CLOCK_SOURCE_ID_DFS,	/* DENTIST */
+	CLOCK_SOURCE_ID_VCE,	/* VCE does not need a real PLL */
+	CLOCK_SOURCE_ID_DP_DTO,	/* Used to distinguish between */
+	/* programming pixel clock */
+	/* and ID (Phy) clock */
+};
+
+
+/* Encoder object ids */
+enum encoder_id {
+	ENCODER_ID_UNKNOWN = 0,
+
+	/* Radeon Class Display Hardware */
+	ENCODER_ID_INTERNAL_LVDS,
+	ENCODER_ID_INTERNAL_TMDS1,
+	ENCODER_ID_INTERNAL_TMDS2,
+	ENCODER_ID_INTERNAL_DAC1,
+	ENCODER_ID_INTERNAL_DAC2,	/* TV/CV DAC */
+	ENCODER_ID_INTERNAL_SDVOA,
+	ENCODER_ID_INTERNAL_SDVOB,
+
+	/* External Third Party Encoders */
+	ENCODER_ID_EXTERNAL_SI170B,
+	ENCODER_ID_EXTERNAL_CH7303,
+	ENCODER_ID_EXTERNAL_CH7301,	/* 10 in decimal */
+	ENCODER_ID_INTERNAL_DVO1,	/* Belongs to Radeon Display Hardware */
+	ENCODER_ID_EXTERNAL_SDVOA,
+	ENCODER_ID_EXTERNAL_SDVOB,
+	ENCODER_ID_EXTERNAL_TITFP513,
+	ENCODER_ID_INTERNAL_LVTM1,	/* not used for Radeon */
+	ENCODER_ID_EXTERNAL_VT1623,
+	ENCODER_ID_EXTERNAL_SI1930,	/* HDMI */
+	ENCODER_ID_INTERNAL_HDMI,
+
+	/* Kaledisope (KLDSCP) Class Display Hardware */
+	ENCODER_ID_INTERNAL_KLDSCP_TMDS1,
+	ENCODER_ID_INTERNAL_KLDSCP_DVO1,
+	ENCODER_ID_INTERNAL_KLDSCP_DAC1,
+	ENCODER_ID_INTERNAL_KLDSCP_DAC2,	/* Shared with CV/TV and CRT */
+	/* External TMDS (dual link) */
+	ENCODER_ID_EXTERNAL_SI178,
+	ENCODER_ID_EXTERNAL_MVPU_FPGA,	/* MVPU FPGA chip */
+	ENCODER_ID_INTERNAL_DDI,
+	ENCODER_ID_EXTERNAL_VT1625,
+	ENCODER_ID_EXTERNAL_SI1932,
+	ENCODER_ID_EXTERNAL_AN9801,	/* External Display Port */
+	ENCODER_ID_EXTERNAL_DP501,	/* External Display Port */
+	ENCODER_ID_INTERNAL_UNIPHY,
+	ENCODER_ID_INTERNAL_KLDSCP_LVTMA,
+	ENCODER_ID_INTERNAL_UNIPHY1,
+	ENCODER_ID_INTERNAL_UNIPHY2,
+	ENCODER_ID_EXTERNAL_NUTMEG,
+	ENCODER_ID_EXTERNAL_TRAVIS,
+
+	ENCODER_ID_INTERNAL_WIRELESS,	/* Internal wireless display encoder */
+	ENCODER_ID_INTERNAL_UNIPHY3,
+
+	ENCODER_ID_EXTERNAL_GENERIC_DVO = 0xFF
+};
+
+
+/* Connector object ids */
+enum connector_id {
+	CONNECTOR_ID_UNKNOWN = 0,
+	CONNECTOR_ID_SINGLE_LINK_DVII,
+	CONNECTOR_ID_DUAL_LINK_DVII,
+	CONNECTOR_ID_SINGLE_LINK_DVID,
+	CONNECTOR_ID_DUAL_LINK_DVID,
+	CONNECTOR_ID_VGA,
+	CONNECTOR_ID_COMPOSITE,
+	CONNECTOR_ID_SVIDEO,
+	CONNECTOR_ID_YPBPR,
+	CONNECTOR_ID_DCONNECTOR,
+	CONNECTOR_ID_9PIN_DIN,
+	CONNECTOR_ID_SCART,
+	CONNECTOR_ID_HDMI_TYPE_A,
+	CONNECTOR_ID_NOT_USED,
+	CONNECTOR_ID_LVDS,
+	CONNECTOR_ID_7PIN_DIN,
+	CONNECTOR_ID_PCIE,
+	CONNECTOR_ID_CROSSFIRE,
+	CONNECTOR_ID_HARDCODE_DVI,
+	CONNECTOR_ID_DISPLAY_PORT,
+	CONNECTOR_ID_EDP,
+	CONNECTOR_ID_MXM,
+	CONNECTOR_ID_WIRELESS,		/* wireless display pseudo-connector */
+	CONNECTOR_ID_MIRACAST,		/* used for VCE encode display path
+					 * for Miracast */
+
+	CONNECTOR_ID_COUNT
+};
+
+
+/* Audio object ids */
+enum audio_id {
+	AUDIO_ID_UNKNOWN = 0,
+	AUDIO_ID_INTERNAL_AZALIA
+};
+
+
+/* Engine object ids */
+enum engine_id {
+	ENGINE_ID_DIGA,
+	ENGINE_ID_DIGB,
+	ENGINE_ID_DIGC,
+	ENGINE_ID_DIGD,
+	ENGINE_ID_DIGE,
+	ENGINE_ID_DIGF,
+	ENGINE_ID_DIGG,
+	ENGINE_ID_DVO,
+	ENGINE_ID_DACA,
+	ENGINE_ID_DACB,
+	ENGINE_ID_VCE,	/* wireless display pseudo-encoder */
+
+	ENGINE_ID_COUNT,
+	ENGINE_ID_UNKNOWN = (-1L)
+};
+
+union supported_stream_engines {
+	struct {
+		uint32_t ENGINE_ID_DIGA:1;
+		uint32_t ENGINE_ID_DIGB:1;
+		uint32_t ENGINE_ID_DIGC:1;
+		uint32_t ENGINE_ID_DIGD:1;
+		uint32_t ENGINE_ID_DIGE:1;
+		uint32_t ENGINE_ID_DIGF:1;
+		uint32_t ENGINE_ID_DIGG:1;
+		uint32_t ENGINE_ID_DVO:1;
+		uint32_t ENGINE_ID_DACA:1;
+		uint32_t ENGINE_ID_DACB:1;
+		uint32_t ENGINE_ID_VCE:1;
+	} engine;
+	uint32_t u_all;
+};
+
+
+/*
+ *****************************************************************************
+ * graphics_object_id struct
+ *
+ * graphics_object_id is a very simple struct wrapping 32bit Graphics
+ * Object identication
+ *
+ * This struct should stay very simple
+ *  No dependencies at all (no includes)
+ *  No debug messages or asserts
+ *  No #ifndef and preprocessor directives
+ *  No grow in space (no more data member)
+ *****************************************************************************
+ */
+
+struct graphics_object_id {
+	uint32_t  id:8;
+	uint32_t  enum_id:4;
+	uint32_t  type:4;
+	uint32_t  reserved:16; /* for padding. total size should be u32 */
+};
+
+/* some simple functions for convenient graphics_object_id handle */
+
+static inline struct graphics_object_id dal_graphics_object_id_init(
+	uint32_t id,
+	enum object_enum_id enum_id,
+	enum object_type type)
+{
+	struct graphics_object_id result = {
+		id, enum_id, type, 0
+	};
+
+	return result;
+}
+
+bool dal_graphics_object_id_is_valid(
+	struct graphics_object_id id);
+bool dal_graphics_object_id_is_equal(
+	struct graphics_object_id id1,
+	struct graphics_object_id id2);
+uint32_t dal_graphics_object_id_to_uint(
+	struct graphics_object_id id);
+
+
+enum controller_id dal_graphics_object_id_get_controller_id(
+	struct graphics_object_id id);
+enum clock_source_id dal_graphics_object_id_get_clock_source_id(
+	struct graphics_object_id id);
+enum encoder_id dal_graphics_object_id_get_encoder_id(
+	struct graphics_object_id id);
+enum connector_id dal_graphics_object_id_get_connector_id(
+	struct graphics_object_id id);
+enum audio_id dal_graphics_object_id_get_audio_id(
+	struct graphics_object_id id);
+enum engine_id dal_graphics_object_id_get_engine_id(
+	struct graphics_object_id id);
+#endif
diff --git a/drivers/gpu/drm/amd/dal/include/irq_types.h b/drivers/gpu/drm/amd/dal/include/irq_types.h
new file mode 100644
index 000000000000..f615fed6eece
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/include/irq_types.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_IRQ_TYPES_H__
+#define __DAL_IRQ_TYPES_H__
+
+struct dal_context;
+
+typedef void (*interrupt_handler)(void *);
+
+typedef void *irq_handler_idx;
+#define DAL_INVALID_IRQ_HANDLER_IDX NULL
+
+
+/* The order of the IRQ sources is important and MUST match the one's
+of base driver */
+enum dal_irq_source {
+	/* Use as mask to specify invalid irq source */
+	DAL_IRQ_SOURCE_INVALID = 0,
+
+	DAL_IRQ_SOURCE_HPD1,
+	DAL_IRQ_SOURCE_HPD2,
+	DAL_IRQ_SOURCE_HPD3,
+	DAL_IRQ_SOURCE_HPD4,
+	DAL_IRQ_SOURCE_HPD5,
+	DAL_IRQ_SOURCE_HPD6,
+
+	DAL_IRQ_SOURCE_HPD1RX,
+	DAL_IRQ_SOURCE_HPD2RX,
+	DAL_IRQ_SOURCE_HPD3RX,
+	DAL_IRQ_SOURCE_HPD4RX,
+	DAL_IRQ_SOURCE_HPD5RX,
+	DAL_IRQ_SOURCE_HPD6RX,
+
+	DAL_IRQ_SOURCE_I2C_DDC1,
+	DAL_IRQ_SOURCE_I2C_DDC2,
+	DAL_IRQ_SOURCE_I2C_DDC3,
+	DAL_IRQ_SOURCE_I2C_DDC4,
+	DAL_IRQ_SOURCE_I2C_DDC5,
+	DAL_IRQ_SOURCE_I2C_DDC6,
+
+	DAL_IRQ_SOURCE_AZALIA0,
+	DAL_IRQ_SOURCE_AZALIA1,
+	DAL_IRQ_SOURCE_AZALIA2,
+	DAL_IRQ_SOURCE_AZALIA3,
+	DAL_IRQ_SOURCE_AZALIA4,
+	DAL_IRQ_SOURCE_AZALIA5,
+
+	DAL_IRQ_SOURCE_DPSINK1,
+	DAL_IRQ_SOURCE_DPSINK2,
+	DAL_IRQ_SOURCE_DPSINK3,
+	DAL_IRQ_SOURCE_DPSINK4,
+	DAL_IRQ_SOURCE_DPSINK5,
+	DAL_IRQ_SOURCE_DPSINK6,
+
+	DAL_IRQ_SOURCE_CRTC1VSYNC,
+	DAL_IRQ_SOURCE_CRTC2VSYNC,
+	DAL_IRQ_SOURCE_CRTC3VSYNC,
+	DAL_IRQ_SOURCE_CRTC4VSYNC,
+	DAL_IRQ_SOURCE_CRTC5VSYNC,
+	DAL_IRQ_SOURCE_CRTC6VSYNC,
+	DAL_IRQ_SOURCE_TIMER,
+
+	DAL_IRQ_SOURCE_PFLIP_FIRST,
+	DAL_IRQ_SOURCE_PFLIP1 = DAL_IRQ_SOURCE_PFLIP_FIRST,
+	DAL_IRQ_SOURCE_PFLIP2,
+	DAL_IRQ_SOURCE_PFLIP3,
+	DAL_IRQ_SOURCE_PFLIP4,
+	DAL_IRQ_SOURCE_PFLIP5,
+	DAL_IRQ_SOURCE_PFLIP6,
+	DAL_IRQ_SOURCE_PFLIP_UNDERLAY0,
+	DAL_IRQ_SOURCE_PFLIP_LAST = DAL_IRQ_SOURCE_PFLIP_UNDERLAY0,
+
+	DAL_IRQ_SOURCE_GPIOPAD0,
+	DAL_IRQ_SOURCE_GPIOPAD1,
+	DAL_IRQ_SOURCE_GPIOPAD2,
+	DAL_IRQ_SOURCE_GPIOPAD3,
+	DAL_IRQ_SOURCE_GPIOPAD4,
+	DAL_IRQ_SOURCE_GPIOPAD5,
+	DAL_IRQ_SOURCE_GPIOPAD6,
+	DAL_IRQ_SOURCE_GPIOPAD7,
+	DAL_IRQ_SOURCE_GPIOPAD8,
+	DAL_IRQ_SOURCE_GPIOPAD9,
+	DAL_IRQ_SOURCE_GPIOPAD10,
+	DAL_IRQ_SOURCE_GPIOPAD11,
+	DAL_IRQ_SOURCE_GPIOPAD12,
+	DAL_IRQ_SOURCE_GPIOPAD13,
+	DAL_IRQ_SOURCE_GPIOPAD14,
+	DAL_IRQ_SOURCE_GPIOPAD15,
+	DAL_IRQ_SOURCE_GPIOPAD16,
+	DAL_IRQ_SOURCE_GPIOPAD17,
+	DAL_IRQ_SOURCE_GPIOPAD18,
+	DAL_IRQ_SOURCE_GPIOPAD19,
+	DAL_IRQ_SOURCE_GPIOPAD20,
+	DAL_IRQ_SOURCE_GPIOPAD21,
+	DAL_IRQ_SOURCE_GPIOPAD22,
+	DAL_IRQ_SOURCE_GPIOPAD23,
+	DAL_IRQ_SOURCE_GPIOPAD24,
+	DAL_IRQ_SOURCE_GPIOPAD25,
+	DAL_IRQ_SOURCE_GPIOPAD26,
+	DAL_IRQ_SOURCE_GPIOPAD27,
+	DAL_IRQ_SOURCE_GPIOPAD28,
+	DAL_IRQ_SOURCE_GPIOPAD29,
+	DAL_IRQ_SOURCE_GPIOPAD30,
+
+	DAL_IRQ_SOURCE_DC1UNDERFLOW,
+	DAL_IRQ_SOURCE_DC2UNDERFLOW,
+	DAL_IRQ_SOURCE_DC3UNDERFLOW,
+	DAL_IRQ_SOURCE_DC4UNDERFLOW,
+	DAL_IRQ_SOURCE_DC5UNDERFLOW,
+	DAL_IRQ_SOURCE_DC6UNDERFLOW,
+
+	DAL_IRQ_SOURCE_DMCU_SCP,
+	DAL_IRQ_SOURCE_VBIOS_SW,
+
+	DAL_IRQ_SOURCES_NUMBER
+};
+
+#define DAL_VALID_IRQ_SRC_NUM(src) \
+	((src) <= DAL_IRQ_SOURCES_NUMBER && (src) > DAL_IRQ_SOURCE_INVALID)
+
+/* Number of Page Flip IRQ Sources. */
+#define DAL_PFLIP_IRQ_SRC_NUM \
+	(DAL_IRQ_SOURCE_PFLIP_LAST - DAL_IRQ_SOURCE_PFLIP_FIRST + 1)
+
+/* the number of contexts may be expanded in the future based on needs */
+enum dal_interrupt_context {
+	INTERRUPT_LOW_IRQ_CONTEXT = 0,
+	INTERRUPT_HIGH_IRQ_CONTEXT,
+	INTERRUPT_CONTEXT_NUMBER
+};
+
+enum dal_interrupt_porlarity {
+	INTERRUPT_POLARITY_DEFAULT = 0,
+	INTERRUPT_POLARITY_LOW = INTERRUPT_POLARITY_DEFAULT,
+	INTERRUPT_POLARITY_HIGH,
+	INTERRUPT_POLARITY_BOTH
+};
+
+#define DAL_DECODE_INTERRUPT_POLARITY(int_polarity) \
+	(int_polarity == INTERRUPT_POLARITY_LOW) ? "Low" : \
+	(int_polarity == INTERRUPT_POLARITY_HIGH) ? "High" : \
+	(int_polarity == INTERRUPT_POLARITY_BOTH) ? "Both" : "Invalid"
+
+struct dal_timer_interrupt_params {
+	uint64_t micro_sec_interval;
+	enum dal_interrupt_context int_context;
+	bool no_mutex_wait;
+};
+
+struct dal_interrupt_params {
+	/* The polarity *change* which will trigger an interrupt.
+	 * If 'requested_polarity == INTERRUPT_POLARITY_BOTH', then
+	 * 'current_polarity' must be initialised. */
+	enum dal_interrupt_porlarity requested_polarity;
+	/* If 'requested_polarity == INTERRUPT_POLARITY_BOTH',
+	 * 'current_polarity' should contain the current state, which means
+	 * the interrupt will be triggered when state changes from what is,
+	 * in 'current_polarity'. */
+	enum dal_interrupt_porlarity current_polarity;
+	enum dal_irq_source irq_source;
+	enum dal_interrupt_context int_context;
+	bool no_mutex_wait;
+	bool one_shot;/* true - trigger once and automatically disable
+			false - trigger every time without disabling
+			Note that timer interrupt is always 'one shot'. */
+};
+
+#endif
diff --git a/drivers/gpu/drm/amd/dal/include/logger_interface.h b/drivers/gpu/drm/amd/dal/include/logger_interface.h
new file mode 100644
index 000000000000..18fcf6a22cd0
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/include/logger_interface.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_LOGGER_INTERFACE_H__
+#define __DAL_LOGGER_INTERFACE_H__
+
+#include "logger_types.h"
+
+struct dal_logger;
+struct dal_context;
+union logger_flags;
+
+/*
+ * TODO: This logger functionality needs to be implemented and reworked.
+ */
+
+
+/*
+ *
+ * DAL logger functionality
+ *
+ */
+
+struct dal_logger *dal_logger_create(void);
+
+uint32_t dal_logger_destroy(struct dal_logger **logger);
+
+uint32_t dal_logger_get_mask(
+	struct dal_logger *logger,
+	enum log_major lvl_major, enum log_minor lvl_minor);
+
+uint32_t dal_logger_set_mask(
+		struct dal_logger *logger,
+		enum log_major lvl_major, enum log_minor lvl_minor);
+
+uint32_t dal_logger_get_masks(
+	struct dal_logger *logger,
+	enum log_major lvl_major);
+
+void dal_logger_set_masks(
+	struct dal_logger *logger,
+	enum log_major lvl_major, uint32_t log_mask);
+
+uint32_t dal_logger_unset_mask(
+		struct dal_logger *logger,
+		enum log_major lvl_major, enum log_minor lvl_minor);
+
+bool dal_logger_should_log(
+		struct dal_logger *logger,
+		enum log_major major,
+		enum log_minor minor);
+
+uint32_t dal_logger_get_flags(
+		struct dal_logger *logger);
+
+void dal_logger_set_flags(
+		struct dal_logger *logger,
+		union logger_flags flags);
+
+void dal_logger_write(
+		struct dal_logger *logger,
+		enum log_major major,
+		enum log_minor minor,
+		const char *msg,
+		...);
+
+void dal_logger_append(
+		struct log_entry *entry,
+		const char *msg,
+		...);
+
+uint32_t dal_logger_read(
+		struct dal_logger *logger,
+		uint32_t output_buffer_size,
+		char *output_buffer,
+		uint32_t *bytes_read,
+		bool single_line);
+
+void dal_logger_open(
+		struct dal_logger *logger,
+		struct log_entry *entry,
+		enum log_major major,
+		enum log_minor minor);
+
+void dal_logger_close(struct log_entry *entry);
+
+uint32_t dal_logger_get_buffer_size(struct dal_logger *logger);
+
+uint32_t dal_logger_set_buffer_size(
+		struct dal_logger *logger,
+		uint32_t new_size);
+
+const struct log_major_info *dal_logger_enum_log_major_info(
+		struct dal_logger *logger,
+		unsigned int enum_index);
+
+const struct log_minor_info *dal_logger_enum_log_minor_info(
+		struct dal_logger *logger,
+		enum log_major major,
+		unsigned int enum_index);
+
+/* Any function which is empty or have incomplete implementation should be
+ * marked by this macro.
+ * Note that the message will be printed exactly once for every function
+ * it is used in order to avoid repeating of the same message. */
+#define DAL_LOGGER_NOT_IMPL(log_minor, fmt, ...) \
+{ \
+	static bool print_not_impl = true; \
+\
+	if (print_not_impl == true) { \
+		print_not_impl = false; \
+		dal_logger_write(dal_context->logger, LOG_MAJOR_WARNING, \
+		log_minor, "DAL_NOT_IMPL: " fmt, ##__VA_ARGS__); \
+	} \
+}
+
+#endif /* __DAL_LOGGER_INTERFACE_H__ */
diff --git a/drivers/gpu/drm/amd/dal/include/logger_types.h b/drivers/gpu/drm/amd/dal/include/logger_types.h
new file mode 100644
index 000000000000..006e378af035
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/include/logger_types.h
@@ -0,0 +1,344 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_LOGGER_TYPES_H__
+#define __DAL_LOGGER_TYPES_H__
+
+
+/*
+ * TODO: This logger functionality needs to be implemented and reworked.
+ */
+
+
+struct dal_logger;
+
+enum log_major {
+/*00*/
+	LOG_MAJOR_ERROR = 0,	/*< DAL subcomponent error MSG*/
+/*01*/  LOG_MAJOR_WARNING,	/*< DAL subcomponent warning MSG*/
+/*02*/  LOG_MAJOR_INTERFACE_TRACE,/*< DAL subcomponent interface tracing*/
+/*03*/  LOG_MAJOR_HW_TRACE,	/*< Log ASIC register read/write,
+				* ATOMBIOS exec table call and delays*/
+
+/*04*/  LOG_MAJOR_MST,		/*< related to multi-stream*/
+/*05*/  LOG_MAJOR_DCS,		/*< related to Dcs*/
+/*06*/  LOG_MAJOR_DCP,		/*< related to Dcp grph and ovl,gamam and csc*/
+/*07*/  LOG_MAJOR_BIOS,		/*< related to BiosParser*/
+/*08*/  LOG_MAJOR_REGISTER,	/*< register access*/
+/*09*/  LOG_MAJOR_INFO_PACKETS,	/*< info packets*/
+/*10*/  LOG_MAJOR_DSAT,		/*< related
+				*	to Display System Analysis Tool*/
+/*11*/  LOG_MAJOR_EC,		/*< External Components - MCIL Events/queries,
+				*	PPLib notifications/queries*/
+/*12*/  LOG_MAJOR_BWM,		/*< related to Bandwidth Manager*/
+/*13*/  LOG_MAJOR_MODE_ENUM,	/*< related to mode enumeration*/
+/*14*/  LOG_MAJOR_I2C_AUX,	/*< i2c and aux channel log*/
+/*15*/  LOG_MAJOR_LINE_BUFFER,	/*< Line Buffer object logging activity*/
+/*16*/  LOG_MAJOR_HWSS,		/*< HWSS object logging activity*/
+/*17*/  LOG_MAJOR_OPTIMIZATION,	/*< Optimization code path*/
+/*18*/  LOG_MAJOR_PERF_MEASURE,	/*< Perfomance measurement dumps*/
+/*19*/  LOG_MAJOR_SYNC,		/*< related to HW and SW Synchronization*/
+/*20*/  LOG_MAJOR_BACKLIGHT,	/*< related to backlight */
+/*21*/  LOG_MAJOR_INTERRUPTS,	/*< logging for all interrupts */
+
+/*22*/  LOG_MAJOR_TM,		/*< related to Topology Manager*/
+/*23*/  LOG_MAJOR_DISPLAY_SERVICE, /*< related to Display Service*/
+/*24*/	LOG_MAJOR_FEATURE_OVERRIDE,	/*< related to features*/
+	LOG_MAJOR_COUNT,	/*< count of the Major categories*/
+};
+
+/**
+* @brief defines minor switch for logging.  each of these define sub category
+*        of log message per LogMajor
+*/
+
+
+enum log_minor {
+
+	/* Special case for 'all' checkbox */
+	LOG_MINOR_MASK_ALL = (uint32_t)-1, /* 0xFFFFFFFF */
+/**
+* @brief defines minor category for
+*         LOG_MAJOR_ERROR,
+*         LOG_MAJOR_WARNING,
+*         LOG_MAJOR_INTERFACE_TRACE
+*
+* @note  each DAL subcomponent should have a corresponding enum
+*/
+	LOG_MINOR_COMPONENT_LINK_SERVICE = 0,
+	LOG_MINOR_COMPONENT_DAL_INTERFACE,
+	LOG_MINOR_COMPONENT_HWSS,
+	LOG_MINOR_COMPONENT_ADAPTER_SERVICE,
+	LOG_MINOR_COMPONENT_DISPLAY_SERVICE,
+	LOG_MINOR_COMPONENT_TOPOLOGY_MANAGER,
+	LOG_MINOR_COMPONENT_ENCODER,
+	LOG_MINOR_COMPONENT_I2C_AUX,
+	LOG_MINOR_COMPONENT_AUDIO,
+	LOG_MINOR_COMPONENT_DISPLAY_CAPABILITY_SERVICE,
+	LOG_MINOR_COMPONENT_DMCU,
+	LOG_MINOR_COMPONENT_GPU,
+	LOG_MINOR_COMPONENT_CONTROLLER,
+	LOG_MINOR_COMPONENT_ISR,
+	LOG_MINOR_COMPONENT_BIOS,
+	LOG_MINOR_COMPONENT_IRQ_SERVICE,
+
+/**
+* @brief define minor category for LogMajor_HardwareTrace
+*
+* @note  defines functionality based HW programming trace
+*/
+	LOG_MINOR_HW_TRACE_MST = 0,
+	LOG_MINOR_HW_TRACE_TRAVIS,
+	LOG_MINOR_HW_TRACE_HOTPLUG,
+	LOG_MINOR_HW_TRACE_LINK_TRAINING,
+	LOG_MINOR_HW_TRACE_SET_MODE,
+	LOG_MINOR_HW_TRACE_RESUME_S3,
+	LOG_MINOR_HW_TRACE_RESUME_S4,
+	LOG_MINOR_HW_TRACE_BOOTUP,
+	LOG_MINOR_HW_TRACE_AUDIO,
+	LOG_MINOR_HW_TRACE_HPD_IRQ,
+	LOG_MINOR_HW_TRACE_INTERRUPT,
+	LOG_MINOR_HW_TRACE_MPO,
+
+/**
+* @brief defines minor category for LogMajor_Mst
+*
+* @note  define sub functionality related to MST
+*/
+	LOG_MINOR_MST_IRQ_HPD_RX = 0,
+	LOG_MINOR_MST_IRQ_TIMER,
+	LOG_MINOR_MST_NATIVE_AUX,
+	LOG_MINOR_MST_SIDEBAND_MSG,
+	LOG_MINOR_MST_MSG_TRANSACTION,
+	LOG_MINOR_MST_SIDEBAND_MSG_PARSED,
+	LOG_MINOR_MST_MSG_TRANSACTION_PARSED,
+	LOG_MINOR_MST_AUX_MSG_DPCD_ACCESS,
+	LOG_MINOR_MST_PROGRAMMING,
+	LOG_MINOR_MST_TOPOLOGY_DISCOVERY,
+	LOG_MINOR_MST_CONVERTER_CAPS,
+
+/**
+* @brief defines minor category for LogMajor_DCS
+*
+* @note  should define sub functionality related to Dcs
+*/
+	LOG_MINOR_DCS_EDID_EMULATOR = 0,
+	LOG_MINOR_DCS_DONGLE_DETECTION,
+
+/**
+* @brief defines minor category for DCP
+*
+* @note  should define sub functionality related to Dcp
+*/
+	LOG_MINOR_DCP_GAMMA_GRPH = 0,
+	LOG_MINOR_DCP_GAMMA_OVL,
+	LOG_MINOR_DCP_CSC_GRPH,
+	LOG_MINOR_DCP_CSC_OVL,
+	LOG_MINOR_DCP_SCALER,
+	LOG_MINOR_DCP_SCALER_TABLES,
+/**
+* @brief defines minor category for LogMajor_Bios
+*
+* @note define sub functionality related to BiosParser
+*/
+	LOG_MINOR_BIOS_CMD_TABLE = 0,
+/**
+* @brief defines minor category for LogMajor_Bios
+*
+* @note define sub functionality related to BiosParser
+*/
+	LOG_MINOR_REGISTER_INDEX = 0,
+/**
+* @brief defines minor category for info packets
+*
+*/
+	LOG_MINOR_INFO_PACKETS_HDMI = 0,
+
+/**
+* @brief defines minor category for LOG_MAJOR_DSAT
+*
+* @note define sub functionality related to Display System Analysis Tool
+*/
+	LOG_MINOR_DSAT_LOGGER = 0,
+	LOG_MINOR_DSAT_GET_EDID,
+	LOG_MINOR_DSAT_EDID_OVERRIDE,
+	LOG_MINOR_DSAT_SET_ADJUSTMENTS,
+	LOG_MINOR_DSAT_GET_ADJUSTMENTS,
+
+/**
+* @brief defines minor category for LOG_MAJOR_EC
+*
+* @note define sub functionality related to External components notifications
+*/
+	LOG_MINOR_EC_PPLIB_NOTIFY = 0,
+	LOG_MINOR_EC_PPLIB_QUERY,
+
+/**
+* @brief defines minor category for LOG_MAJOR_BWM
+*
+* @note define sub functionality related to Bandwidth Manager
+*/
+	LOG_MINOR_BWM_MODE_VALIDATION = 0,
+	LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
+
+/**
+* @brief define minor category for LogMajor_ModeEnum
+*
+* @note  defines functionality mode enumeration trace
+*/
+	LOG_MINOR_MODE_ENUM_BEST_VIEW_CANDIDATES = 0,
+	LOG_MINOR_MODE_ENUM_VIEW_SOLUTION,
+	LOG_MINOR_MODE_ENUM_TS_LIST_BUILD,
+	LOG_MINOR_MODE_ENUM_TS_LIST,
+	LOG_MINOR_MODE_ENUM_MASTER_VIEW_LIST,
+	LOG_MINOR_MODE_ENUM_MASTER_VIEW_LIST_UPDATE,
+
+/**
+* @brief defines minor category for LogMajor_I2C_AUX
+*
+* @note define sub functionality related to I2c and Aux Channel Log
+*/
+	LOG_MINOR_I2C_AUX_LOG = 0,
+	LOG_MINOR_I2C_AUX_AUX_TIMESTAMP,
+
+/**
+* @brief defines minor category for LogMajor_LineBuffer
+*
+* @note define sub functionality related to LineBuffer
+*/
+	LOG_MINOR_LINE_BUFFER_POWERGATING = 0,
+
+/**
+* @brief defines minor category for LogMajor_HWSS
+*
+* @note define sub functionality related to HWSS
+*/
+	LOG_MINOR_HWSS_TAPS_VALIDATION = 0,
+
+/**
+* @brief defines minor category for LogMajor_Optimization
+*
+* @note define sub functionality related to Optimization
+*/
+	LOG_MINOR_OPTMZ_GENERAL = 0,
+	LOG_MINOR_OPTMZ_DO_NOT_TURN_OFF_VCC_DURING_SET_MODE,
+
+/**
+* @brief defines minor category for LogMajor_PerfMeasure
+*
+* @note define sub functionality related to Performance measurement dumps
+*/
+	LOG_MINOR_PERF_MEASURE_GENERAL = 0,
+	LOG_MINOR_PERF_MEASURE_HEAP_MEMORY,
+
+/**
+* @brief defines minor category for LogMajor_Sync
+*
+* @note define sub functionality related to HW and SW Synchronization
+*/
+	LOG_MINOR_SYNC_HW_CLOCK_ADJUST = 0,
+
+/**
+* @brief defines minor category for LogMajor_Backlight
+*
+* @note define sub functionality related to backlight (including VariBright)
+*/
+	LOG_MINOR_BACKLIGHT_BRIGHTESS_CAPS = 0,
+	LOG_MINOR_BACKLIGHT_DMCU_DELTALUT,
+	LOG_MINOR_BACKLIGHT_DMCU_BUILD_DELTALUT,
+	LOG_MINOR_BACKLIGHT_INTERFACE,
+	LOG_MINOR_BACKLIGHT_LID,
+
+/**
+* @brief defines minor category for LOG_MAJOR_TM
+*
+* @note define sub functionality related to Topology Manager
+*/
+	LOG_MINOR_TM_INFO = 0,
+	LOG_MINOR_TM_IFACE_TRACE,
+	LOG_MINOR_TM_RESOURCES,
+	LOG_MINOR_TM_ENCODER_CTL,
+	LOG_MINOR_TM_ENG_ASN,
+	LOG_MINOR_TM_CONTROLLER_ASN,
+	LOG_MINOR_TM_PWR_GATING,
+	LOG_MINOR_TM_BUILD_DSP_PATH,
+	LOG_MINOR_TM_DISPLAY_DETECT,
+	LOG_MINOR_TM_LINK_SRV,
+	LOG_MINOR_TM_NOT_IMPLEMENTED,
+	LOG_MINOR_TM_COFUNC_PATH,
+
+/**
+* @brief defines minor category for LOG_MAJOR_DISPLAY_SERVICE
+*
+* @note define sub functionality related to Display Service
+*/
+	LOG_MINOR_DS_MODE_SETTING = 0,
+
+/**
+* @brief defines minor category for LOG_MAJOR_FEATURE_OVERRIDE
+*
+* @note define sub functionality related to features in adapter service
+*/
+	LOG_MINOR_FEATURE_OVERRIDE = 0,
+};
+
+union logger_flags {
+	struct {
+		uint32_t ENABLE_CONSOLE:1; /* Print to console */
+		uint32_t ENABLE_BUFFER:1; /* Print to buffer */
+		uint32_t RESERVED:30;
+	} bits;
+	uint32_t value;
+};
+
+struct log_entry {
+
+	struct dal_logger *logger;
+	enum log_major major;
+	enum log_minor minor;
+
+	char *buf;
+	uint32_t buf_offset;
+	uint32_t max_buf_bytes;
+};
+
+/**
+* Structure for enumerating LogMajors and LogMinors
+*/
+
+#define MAX_MAJOR_NAME_LEN 32
+#define MAX_MINOR_NAME_LEN 32
+
+struct log_major_info {
+	enum log_major major;
+	char major_name[MAX_MAJOR_NAME_LEN];
+};
+
+struct log_minor_info {
+	enum log_minor minor;
+	char minor_name[MAX_MINOR_NAME_LEN];
+};
+
+#endif /* __DAL_LOGGER_TYPES_H__ */
diff --git a/drivers/gpu/drm/amd/dal/include/signal_types.h b/drivers/gpu/drm/amd/dal/include/signal_types.h
new file mode 100644
index 000000000000..8dbd14737ef3
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/include/signal_types.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_SIGNAL_TYPES_H__
+#define __DAL_SIGNAL_TYPES_H__
+
+enum signal_type {
+	SIGNAL_TYPE_NONE		= 0L,		/* no signal */
+	SIGNAL_TYPE_DVI_SINGLE_LINK	= (1 << 0),
+	SIGNAL_TYPE_DVI_SINGLE_LINK1	= (1 << 1),
+	SIGNAL_TYPE_DVI_DUAL_LINK	= (1 << 2),
+	SIGNAL_TYPE_HDMI_TYPE_A		= (1 << 3),
+	SIGNAL_TYPE_LVDS		= (1 << 4),
+	SIGNAL_TYPE_RGB			= (1 << 5),
+	SIGNAL_TYPE_YPBPR		= (1 << 6),
+	SIGNAL_TYPE_SCART		= (1 << 7),
+	SIGNAL_TYPE_COMPOSITE		= (1 << 8),
+	SIGNAL_TYPE_SVIDEO		= (1 << 9),
+	SIGNAL_TYPE_DISPLAY_PORT	= (1 << 10),
+	SIGNAL_TYPE_DISPLAY_PORT_MST	= (1 << 11),
+	SIGNAL_TYPE_EDP			= (1 << 12),
+	SIGNAL_TYPE_DVO			= (1 << 13),	/* lower 12 bits */
+	SIGNAL_TYPE_DVO24		= (1 << 14),	/* 24 bits */
+	SIGNAL_TYPE_MVPU_A		= (1 << 15),	/* lower 12 bits */
+	SIGNAL_TYPE_MVPU_B		= (1 << 16),	/* upper 12 bits */
+	SIGNAL_TYPE_MVPU_AB		= (1 << 17),	/* 24 bits */
+	SIGNAL_TYPE_WIRELESS		= (1 << 18),	/* Wireless Display */
+
+	SIGNAL_TYPE_COUNT		= 19,
+	SIGNAL_TYPE_ALL			= (1 << SIGNAL_TYPE_COUNT) - 1
+};
+
+/* help functions for signal types manipulation */
+bool dal_is_hdmi_signal(enum signal_type signal);
+bool dal_is_dp_sst_signal(enum signal_type signal);
+bool dal_is_dp_signal(enum signal_type signal);
+bool dal_is_dp_external_signal(enum signal_type signal);
+bool dal_is_analog_signal(enum signal_type signal);
+bool dal_is_embedded_signal(enum signal_type signal);
+bool dal_is_dvi_signal(enum signal_type signal);
+bool dal_is_dvo_signal(enum signal_type signal);
+bool dal_is_mvpu_signal(enum signal_type signal);
+bool dal_is_cf_signal(enum signal_type signal);
+bool dal_is_dvi_single_link_signal(enum signal_type signal);
+bool dal_is_dual_link_signal(enum signal_type signal);
+bool dal_is_audio_capable_signal(enum signal_type signal);
+bool dal_is_digital_encoder_compatible_signal(enum signal_type signal);
+
+#endif
diff --git a/drivers/gpu/drm/amd/dal/include/vector.h b/drivers/gpu/drm/amd/dal/include/vector.h
new file mode 100644
index 000000000000..e10543f8f775
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/include/vector.h
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_VECTOR_H__
+#define __DAL_VECTOR_H__
+
+struct vector {
+	uint8_t *container;
+	uint32_t struct_size;
+	uint32_t count;
+	uint32_t capacity;
+};
+
+bool dal_vector_construct(
+	struct vector *vector,
+	uint32_t capacity,
+	uint32_t struct_size);
+
+struct vector *dal_vector_create(
+	uint32_t capacity,
+	uint32_t struct_size);
+
+/* 'initial_value' is optional. If initial_value not supplied,
+ * each "structure" in the vector will contain zeros by default. */
+struct vector *dal_vector_presized_create(
+	uint32_t size,
+	void *initial_value,
+	uint32_t struct_size);
+
+void dal_vector_destruct(
+	struct vector *vector);
+
+void dal_vector_destroy(
+	struct vector **vector);
+
+uint32_t dal_vector_get_count(
+	const struct vector *vector);
+
+/* dal_vector_insert_at
+ * reallocate container if necessary
+ * then shell items at right and insert
+ * return if the container modified
+ * do not check that index belongs to container
+ * since the function is private and index is going to be calculated
+ * either with by function or as get_count+1 */
+bool dal_vector_insert_at(
+	struct vector *vector,
+	const void *what,
+	uint32_t position);
+
+bool dal_vector_append(
+	struct vector *vector,
+	const void *item);
+
+/* operator[] */
+void *dal_vector_at_index(
+	const struct vector *vector,
+	uint32_t index);
+
+void dal_vector_set_at_index(
+	const struct vector *vector,
+	const void *what,
+	uint32_t index);
+
+/* create a clone (copy) of a vector */
+struct vector *dal_vector_clone(
+	const struct vector *vector_other);
+
+/* dal_vector_remove_at_index
+ * Shifts elements on the right from remove position to the left,
+ * removing an element at position by overwrite means*/
+bool dal_vector_remove_at_index(
+	struct vector *vector,
+	uint32_t index);
+
+uint32_t dal_vector_capacity(const struct vector *vector);
+
+bool dal_vector_reserve(struct vector *vector, uint32_t capacity);
+
+void dal_vector_clear(struct vector *vector);
+
+/***************************************************************************
+ * Macro definitions of TYPE-SAFE versions of vector set/get functions.
+ ***************************************************************************/
+
+#define DAL_VECTOR_INSERT_AT(vector_type, type_t) \
+	static bool vector_type##_vector_insert_at( \
+		struct vector *vector, \
+		type_t what, \
+		uint32_t position) \
+{ \
+	return dal_vector_insert_at(vector, what, position); \
+}
+
+#define DAL_VECTOR_APPEND(vector_type, type_t) \
+	static bool vector_type##_vector_append( \
+		struct vector *vector, \
+		type_t item) \
+{ \
+	return dal_vector_append(vector, item); \
+}
+
+/* Note: "type_t" is the ONLY token accepted by "checkpatch.pl" and by
+ * "checkcommit" as *return type*.
+ * For uniformity reasons "type_t" is used for all type-safe macro
+ * definitions here. */
+#define DAL_VECTOR_AT_INDEX(vector_type, type_t) \
+	static type_t vector_type##_vector_at_index( \
+		const struct vector *vector, \
+		uint32_t index) \
+{ \
+	return dal_vector_at_index(vector, index); \
+}
+
+#define DAL_VECTOR_SET_AT_INDEX(vector_type, type_t) \
+	static void vector_type##_vector_set_at_index( \
+		const struct vector *vector, \
+		type_t what, \
+		uint32_t index) \
+{ \
+	dal_vector_set_at_index(vector, what, index); \
+}
+
+#endif /* __DAL_VECTOR_H__ */