diff options
| author | Abdiel Janulgue <abdiel.janulgue@linux.intel.com> | 2015-04-15 09:41:53 +0300 |
|---|---|---|
| committer | Abdiel Janulgue <abdiel.janulgue@linux.intel.com> | 2015-09-11 11:22:57 +0300 |
| commit | 312b09e63edf0bcf7a243468bc4e236a1e463251 (patch) | |
| tree | e44a1f0ff938f7be6c3381aafb7d03c8f27c456a | |
| parent | 76b68eaec1a050cb17b72dcc3ba6173fdccd4b15 (diff) | |
i965/vec4: Append uniform entries to the gather table
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4.cpp | 12 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4.h | 1 |
2 files changed, 13 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 85dc37238d..f2b03f8d25 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -595,6 +595,17 @@ vec4_visitor::pack_uniform_registers() } } +void +vec4_visitor::generate_gather_table() +{ + int num_consts = ALIGN(stage_prog_data->nr_params, 4) / 4; + for (int i = 0; i < num_consts; i++) { + int p = stage_prog_data->nr_gather_table++; + stage_prog_data->gather_table[p].reg = -1; + stage_prog_data->gather_table[p].channel_mask = 0xf; + } +} + /** * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a). * @@ -1832,6 +1843,7 @@ vec4_visitor::run() return false; setup_payload(); + generate_gather_table(); if (unlikely(INTEL_DEBUG & DEBUG_SPILL_VEC4)) { /* Debug of register spilling: Go spill everything. */ diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h index 01c6e8492c..534f1b1987 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_vec4.h @@ -206,6 +206,7 @@ public: bool is_dep_ctrl_unsafe(const vec4_instruction *inst); void opt_set_dependency_control(); void opt_schedule_instructions(); + void generate_gather_table(); vec4_instruction *emit(vec4_instruction *inst); |